IT1148807B - Substrato vetroceramica a piu' strati per il montaggio di un dispositivo semiconduttore - Google Patents

Substrato vetroceramica a piu' strati per il montaggio di un dispositivo semiconduttore

Info

Publication number
IT1148807B
IT1148807B IT20407/80A IT2040780A IT1148807B IT 1148807 B IT1148807 B IT 1148807B IT 20407/80 A IT20407/80 A IT 20407/80A IT 2040780 A IT2040780 A IT 2040780A IT 1148807 B IT1148807 B IT 1148807B
Authority
IT
Italy
Prior art keywords
assembly
ceramic substrate
glass ceramic
layer glass
semiconductive device
Prior art date
Application number
IT20407/80A
Other languages
English (en)
Other versions
IT8020407A0 (it
Inventor
Bernt Narken
Ramamahara Tummala Rao
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8020407A0 publication Critical patent/IT8020407A0/it
Application granted granted Critical
Publication of IT1148807B publication Critical patent/IT1148807B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
IT20407/80A 1979-03-23 1980-03-07 Substrato vetroceramica a piu' strati per il montaggio di un dispositivo semiconduttore IT1148807B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/023,113 US4221047A (en) 1979-03-23 1979-03-23 Multilayered glass-ceramic substrate for mounting of semiconductor device

Publications (2)

Publication Number Publication Date
IT8020407A0 IT8020407A0 (it) 1980-03-07
IT1148807B true IT1148807B (it) 1986-12-03

Family

ID=21813203

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20407/80A IT1148807B (it) 1979-03-23 1980-03-07 Substrato vetroceramica a piu' strati per il montaggio di un dispositivo semiconduttore

Country Status (6)

Country Link
US (1) US4221047A (it)
EP (1) EP0016306B1 (it)
JP (1) JPS55128856A (it)
CA (1) CA1123116A (it)
DE (1) DE3068834D1 (it)
IT (1) IT1148807B (it)

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926228A (en) * 1981-03-30 1990-05-15 Secretary Of State For Defence (G.B.) Photoconductive detector arranged for bias field concentration at the output bias contact
US4446477A (en) * 1981-08-21 1984-05-01 Sperry Corporation Multichip thin film module
DE3269083D1 (en) * 1981-10-22 1986-03-27 Bbc Brown Boveri & Cie Electrical contact for a silicon semiconductor
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
JPS59995A (ja) * 1982-06-16 1984-01-06 富士通株式会社 銅導体多層構造体の製造方法
DE3225178A1 (de) * 1982-07-06 1984-01-12 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Mehrebenenschaltung und verfahren zu ihrer herstellung
JPS599992A (ja) * 1982-07-08 1984-01-19 株式会社日立製作所 多層配線基板の製造方法
US4504007A (en) * 1982-09-14 1985-03-12 International Business Machines Corporation Solder and braze fluxes and processes for using the same
JPS6022396A (ja) * 1983-07-19 1985-02-04 日本電気株式会社 回路基板
US4504340A (en) * 1983-07-26 1985-03-12 International Business Machines Corporation Material and process set for fabrication of molecular matrix print head
US4646129A (en) * 1983-09-06 1987-02-24 General Electric Company Hermetic power chip packages
US4526859A (en) * 1983-12-12 1985-07-02 International Business Machines Corporation Metallization of a ceramic substrate
US4478677A (en) * 1983-12-22 1984-10-23 International Business Machines Corporation Laser induced dry etching of vias in glass with non-contact masking
US4490211A (en) * 1984-01-24 1984-12-25 International Business Machines Corporation Laser induced chemical etching of metals with excimer lasers
US4490210A (en) * 1984-01-24 1984-12-25 International Business Machines Corporation Laser induced dry chemical etching of metals
JPS60178695A (ja) * 1984-02-17 1985-09-12 インタ−ナシヨナル　ビジネス　マシ−ンズ　コ−ポレ−シヨン 電気的相互接続パツケ−ジ
JPS60208886A (ja) * 1984-03-31 1985-10-21 株式会社東芝 電子部品の製造方法
JPS60221358A (ja) * 1984-04-13 1985-11-06 日本碍子株式会社 電気絶縁体用セラミック組成物
US4630096A (en) * 1984-05-30 1986-12-16 Motorola, Inc. High density IC module assembly
FR2567709B1 (fr) * 1984-07-11 1990-11-09 Nec Corp Ensemble a paillette comprenant un substrat de cablage multi-couche
US4705606A (en) * 1985-01-31 1987-11-10 Gould Inc. Thin-film electrical connections for integrated circuits
US4996584A (en) * 1985-01-31 1991-02-26 Gould, Inc. Thin-film electrical connections for integrated circuits
EP0193782A3 (en) * 1985-03-04 1987-11-25 Olin Corporation Multi-layer and pin grid arrays
US4840654A (en) * 1985-03-04 1989-06-20 Olin Corporation Method for making multi-layer and pin grid arrays
US4712161A (en) * 1985-03-25 1987-12-08 Olin Corporation Hybrid and multi-layer circuitry
JPS61239649A (ja) * 1985-04-13 1986-10-24 Fujitsu Ltd 高速集積回路パツケ−ジ
US4679938A (en) * 1985-06-03 1987-07-14 International Business Machines Corporation Defect detection in films on ceramic substrates
US4633366A (en) * 1985-08-07 1986-12-30 Sprague Electric Company Laminar electrical component with magnesium orthoborate
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
US4663186A (en) * 1986-04-24 1987-05-05 International Business Machines Corporation Screenable paste for use as a barrier layer on a substrate during maskless cladding
US4879156A (en) * 1986-05-02 1989-11-07 International Business Machines Corporation Multilayered ceramic substrate having solid non-porous metal conductors
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
JPS63265493A (ja) * 1987-04-23 1988-11-01 Fujitsu Ltd 多層セラミツク基板
US4788046A (en) * 1987-08-13 1988-11-29 Ceramics Process Systems Corporation Method for producing materials for co-sintering
GB2209867B (en) * 1987-09-16 1990-12-19 Advanced Semiconductor Package Method of forming an integrated circuit chip carrier
JP2608449B2 (ja) * 1988-03-02 1997-05-07 サーマルプリンタヘッドの製造方法
US4805683A (en) * 1988-03-04 1989-02-21 International Business Machines Corporation Method for producing a plurality of layers of metallurgy
US4853349A (en) * 1988-05-26 1989-08-01 Corning Glass Works Glass-ceramics suitable for dielectric substrates
US5170245A (en) * 1988-06-15 1992-12-08 International Business Machines Corp. Semiconductor device having metallic interconnects formed by grit blasting
US5027062A (en) * 1988-06-20 1991-06-25 General Dynamics Corporation, Air Defense Systems Division Electroformed chemically milled probes for chip testing
US4878294A (en) * 1988-06-20 1989-11-07 General Dynamics Corp., Pomona Division Electroformed chemically milled probes for chip testing
US5013605A (en) * 1988-08-11 1991-05-07 Gritz David N Cordierite-type glass-ceramic with controlled coloration
JPH02168662A (ja) * 1988-09-07 1990-06-28 Hitachi Ltd チップキャリア
US4914813A (en) * 1988-11-25 1990-04-10 Innovative Packing Technology Refurbishing of prior used laminated ceramic packages
JPH02148862A (ja) * 1988-11-30 1990-06-07 Hitachi Ltd 回路素子パッケージ、キャリヤ基板および製造方法
GB2229572A (en) * 1989-03-14 1990-09-26 Oxley Dev Co Ltd Ceramic multilayer structure
US5089880A (en) * 1989-06-07 1992-02-18 Amdahl Corporation Pressurized interconnection system for semiconductor chips
DE3923533A1 (de) * 1989-07-15 1991-01-24 Diehl Gmbh & Co Anordnung eines integrierten schaltkreises auf einem schaltungstraeger
US4991000A (en) * 1989-08-31 1991-02-05 Bone Robert L Vertically interconnected integrated circuit chip system
US5102720A (en) * 1989-09-22 1992-04-07 Cornell Research Foundation, Inc. Co-fired multilayer ceramic tapes that exhibit constrained sintering
JPH0719964B2 (ja) * 1990-08-08 1995-03-06 日本電気株式会社 銀系配線セラミック基板
US5198008A (en) * 1990-11-09 1993-03-30 National Semiconductor Corporation Method of fabricating an optical interconnect structure
US5132613A (en) * 1990-11-30 1992-07-21 International Business Machines Corporation Low inductance side mount decoupling test structure
US5073180A (en) * 1991-03-20 1991-12-17 International Business Machines Corporation Method for forming sealed co-fired glass ceramic structures
JP3547146B2 (ja) * 1991-06-10 2004-07-28 日本特殊陶業株式会社 集積回路用パッケージ
JP2765673B2 (ja) * 1992-06-04 1998-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション メタライゼーション層及びその形成方法
US5512710A (en) * 1992-08-21 1996-04-30 Cts Corporation Multilayer package with second layer via test connections
US5371654A (en) * 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US20050062492A1 (en) * 2001-08-03 2005-03-24 Beaman Brian Samuel High density integrated circuit apparatus, test probe and methods of use thereof
FR2700659B1 (fr) * 1993-01-18 1995-03-24 Matra Sep Imagerie Inf Procédé de fabrication de circuits multicouches er circuits ainsi obtenus.
US5766670A (en) * 1993-11-17 1998-06-16 Ibm Via fill compositions for direct attach of devices and methods for applying same
US5512765A (en) * 1994-02-03 1996-04-30 National Semiconductor Corporation Extendable circuit architecture
FR2716037B1 (fr) * 1994-02-10 1996-06-07 Matra Marconi Space France Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.
TW276356B (it) * 1994-06-24 1996-05-21 Ibm
AU3415095A (en) * 1994-09-06 1996-03-27 Sheldahl, Inc. Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture
EP0732735B1 (en) * 1995-03-16 2005-12-14 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic device and method of manufacturing same
JP2812358B2 (ja) * 1996-03-18 1998-10-22 日本電気株式会社 Ｌｓｉパッケージおよびｌｓｉパッケージ製造方法
JPH09283654A (ja) * 1996-04-17 1997-10-31 Nec Corp ガラスセラミック基板とその製造方法
US5822856A (en) * 1996-06-28 1998-10-20 International Business Machines Corporation Manufacturing circuit board assemblies having filled vias
US5740605A (en) * 1996-07-25 1998-04-21 Texas Instruments Incorporated Bonded z-axis interface
US6058780A (en) * 1997-03-20 2000-05-09 Alliedsignal Inc. Capacitive pressure sensor housing having a ceramic base
US6324914B1 (en) 1997-03-20 2001-12-04 Alliedsignal, Inc. Pressure sensor support base with cavity
US6262478B1 (en) * 1997-04-08 2001-07-17 Amitec-Advanced Multilayer Interconnect Technologies Ltd. Electronic interconnect structure and method for manufacturing it
IL133091A0 (en) * 1997-05-23 2001-03-19 Alpine Microsystems Inc A system and method for packaging integrated circuits
US6387318B1 (en) 1997-12-05 2002-05-14 Alliedsignal, Inc. Glass-ceramic pressure sensor support base and its fabrication
EP1061784B1 (en) * 1998-07-20 2006-09-27 Samsung Electronics Co., Ltd. Radio-electronic unit
JP3445511B2 (ja) * 1998-12-10 2003-09-08 株式会社東芝 絶縁基板、その製造方法およびそれを用いた半導体装置
US6432564B1 (en) * 1999-08-12 2002-08-13 Mini Systems, Inc. Surface preparation of a substrate for thin film metallization
US6507113B1 (en) * 1999-11-19 2003-01-14 General Electric Company Electronic interface structures and methods of fabrication
JP2001168227A (ja) * 1999-12-08 2001-06-22 Mitsubishi Electric Corp 多ピン・ボールグリッドアレイ・パッケージ用の基板、多ピン・ボールグリッドアレイ・パッケージ及び半導体装置
US6570250B1 (en) * 2000-02-24 2003-05-27 Honeywell International Inc. Power conditioning substrate stiffener
JP2003304065A (ja) * 2002-04-08 2003-10-24 Sony Corp 回路基板装置及びその製造方法、並びに半導体装置及びその製造方法
JP4125644B2 (ja) * 2002-07-05 2008-07-30 松下電器産業株式会社 多層回路基板の形成方法および多層回路基板
DE10309689B4 (de) * 2003-02-27 2005-04-07 Bundesanstalt für Materialforschung und -Prüfung (BAM) Keramische Platte mit monolithischem Schichtaufbau und Verfahren zu seiner Herstellung
US8569142B2 (en) * 2003-11-28 2013-10-29 Blackberry Limited Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same
JP4311376B2 (ja) 2005-06-08 2009-08-12 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、電子部品、回路基板及び電子機器
US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
US9420707B2 (en) * 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
CN103534802A (zh) 2011-06-01 2014-01-22 E.I.内穆尔杜邦公司 用于高频应用的低温共烧陶瓷结构及其制造方法
US9445496B2 (en) 2012-03-07 2016-09-13 Intel Corporation Glass clad microelectronic substrate
US9001520B2 (en) 2012-09-24 2015-04-07 Intel Corporation Microelectronic structures having laminated or embedded glass routing structures for high density packaging
US9615453B2 (en) 2012-09-26 2017-04-04 Ping-Jung Yang Method for fabricating glass substrate package
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
JP6505726B2 (ja) 2014-01-31 2019-04-24 コーニング インコーポレイテッド 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置
US11489038B2 (en) * 2017-08-29 2022-11-01 Micron Technology, Inc. Capacitors having vertical contacts extending through conductive tiers
US11195789B2 (en) * 2018-11-30 2021-12-07 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer
US11647582B1 (en) 2020-08-26 2023-05-09 Ian Getreu Rapid implementation of high-temperature analog interface electronics

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE557975A (it) * 1956-06-04 1957-11-30
BE562405A (it) * 1956-11-15
US3113009A (en) * 1958-10-17 1963-12-03 Corning Glass Works Method of making and treating a semicrystalline ceramic body
US3560256A (en) * 1966-10-06 1971-02-02 Western Electric Co Combined thick and thin film circuits
US3604082A (en) * 1968-10-30 1971-09-14 Corning Glass Works Method of making a capacitor
US3988405A (en) * 1971-04-07 1976-10-26 Smith Robert D Process for forming thin walled articles or thin sheets
US3726002A (en) * 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
US3774232A (en) * 1971-11-11 1973-11-20 Circuit Stik Inc Package for integrated circuit chip
US3864159A (en) * 1972-12-04 1975-02-04 Owens Illinois Inc Capacitor having thick-film glass-ceramic dielectric layer and method for manufacture
DE2315797C3 (de) * 1973-03-29 1981-07-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Keramiksubstraten für Dünnschichtschaltungen
US3956052A (en) * 1974-02-11 1976-05-11 International Business Machines Corporation Recessed metallurgy for dielectric substrates
US4068022A (en) * 1974-12-10 1978-01-10 Western Electric Company, Inc. Methods of strengthening bonds
US4104345A (en) * 1975-06-23 1978-08-01 International Business Machines Corporation Ceramic dielectrics
US4029605A (en) * 1975-12-08 1977-06-14 Hercules Incorporated Metallizing compositions
US4109377A (en) * 1976-02-03 1978-08-29 International Business Machines Corporation Method for preparing a multilayer ceramic
US4030190A (en) * 1976-03-30 1977-06-21 International Business Machines Corporation Method for forming a multilayer printed circuit board
US4301324A (en) * 1978-02-06 1981-11-17 International Business Machines Corporation Glass-ceramic structures and sintered multilayer substrates thereof with circuit patterns of gold, silver or copper

Also Published As

Publication number Publication date
IT8020407A0 (it) 1980-03-07
US4221047A (en) 1980-09-09
CA1123116A (en) 1982-05-04
DE3068834D1 (en) 1984-09-13
EP0016306A1 (de) 1980-10-01
EP0016306B1 (de) 1984-08-08
JPS5746664B2 (it) 1982-10-05
JPS55128856A (en) 1980-10-06

Similar Documents

Publication Publication Date Title
IT1148807B (it) Substrato vetroceramica a piu' strati per il montaggio di un dispositivo semiconduttore
IT8247990A0 (it) Procedimento e dispositivo per laproduzione di tavole a piu' strati
IT7867404A0 (it) Procedimento per il rivestimentodel vetro con uno strato di silicio
FR2593930B1 (fr) Dispositif opto-electronique pour montage en surface
DE3856475D1 (de) Monokristallines Dünnschichtsubstrat
NO171781C (no) Fremgangsmaate for fremstilling av en selvbaerende keramiskstruktur
KR860006132A (ko) 반도체 장치용 기판 구조체
DK215387D0 (da) Keramisk chromoxid belaegning
DE3480628D1 (de) Metallisierung eines keramischen substrates.
KR900008069A (ko) 실리콘 단결정의 제조장치
KR920701529A (ko) 실리콘 단결정 제조장치
DK97288D0 (da) Antihypercholesterolemisk tetrazolforbindelse
IT1125584B (it) Dispositivo per l'applicazione di un nastro di materia sotile continuo per il relativo accoppiamento termico con un substrato
FI821021A0 (fi) Foerfarande foer framstaellning av nya oxazafosforin-4-tio-alkansulfonsyror och deras neutrala salter
FR2532465B1 (fr) Condensateur ceramique
JPS5717474A (en) Multilayer ceramic substrate
IT1204035B (it) Dispositivo per patinare un nastro di carta sulle due facce
IT1140883B (it) Procedimento per il trattamento di pannelli per circuiti stampati a piu' strati
DE3473972D1 (en) Semiconductor device comprising a substrate
DE69116422D1 (de) Supraleitendes Mehrschichtkeramiksubstrat
EP0273397A3 (en) A substrate for an optical element
FR2449053B1 (fr) Installation pour l'acheminement d'elements ceramiques
JPS55109289A (en) Glazed ceramic substrate
IT1187629B (it) Dispositivo per l'abbassamento della rugosita'
BR8605153A (pt) Substrato fino de ceramica

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950330