FR2716037B1 - Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu. - Google Patents

Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.

Info

Publication number
FR2716037B1
FR2716037B1 FR9401511A FR9401511A FR2716037B1 FR 2716037 B1 FR2716037 B1 FR 2716037B1 FR 9401511 A FR9401511 A FR 9401511A FR 9401511 A FR9401511 A FR 9401511A FR 2716037 B1 FR2716037 B1 FR 2716037B1
Authority
FR
France
Prior art keywords
chip module
substrate
electronic circuits
connecting electronic
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9401511A
Other languages
English (en)
Other versions
FR2716037A1 (fr
Inventor
Givry Jacques De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Matra Marconi Space France SA
Original Assignee
Matra Marconi Space France SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matra Marconi Space France SA filed Critical Matra Marconi Space France SA
Priority to FR9401511A priority Critical patent/FR2716037B1/fr
Priority to GB9502266A priority patent/GB2287132B/en
Priority to US08/385,720 priority patent/US5562837A/en
Publication of FR2716037A1 publication Critical patent/FR2716037A1/fr
Application granted granted Critical
Publication of FR2716037B1 publication Critical patent/FR2716037B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
FR9401511A 1994-02-10 1994-02-10 Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu. Expired - Lifetime FR2716037B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9401511A FR2716037B1 (fr) 1994-02-10 1994-02-10 Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.
GB9502266A GB2287132B (en) 1994-02-10 1995-02-06 A method for connecting electronic circuits in a multi-chip module having a co-fired substrate, and multi-chip module obtained thereby
US08/385,720 US5562837A (en) 1994-02-10 1995-02-08 Method for connecting electronic circuits in a multi-chip module having a co-fired substrate and multi-chip module obtained thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9401511A FR2716037B1 (fr) 1994-02-10 1994-02-10 Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.

Publications (2)

Publication Number Publication Date
FR2716037A1 FR2716037A1 (fr) 1995-08-11
FR2716037B1 true FR2716037B1 (fr) 1996-06-07

Family

ID=9459961

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9401511A Expired - Lifetime FR2716037B1 (fr) 1994-02-10 1994-02-10 Procédé pour connecter des circuits électoniques dans un module multi-puces à substrat co-cuit, et module multi-puces ainsi obtenu.

Country Status (3)

Country Link
US (1) US5562837A (fr)
FR (1) FR2716037B1 (fr)
GB (1) GB2287132B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19632200C2 (de) * 1996-08-09 2002-09-05 Bosch Gmbh Robert Multichipmodul
US7345316B2 (en) * 2000-10-25 2008-03-18 Shipley Company, L.L.C. Wafer level packaging for optoelectronic devices
US6932519B2 (en) 2000-11-16 2005-08-23 Shipley Company, L.L.C. Optical device package
US6827503B2 (en) * 2000-12-01 2004-12-07 Shipley Company, L.L.C. Optical device package having a configured frame
US6883977B2 (en) 2000-12-14 2005-04-26 Shipley Company, L.L.C. Optical device package for flip-chip mounting
US6787926B2 (en) * 2001-09-05 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Wire stitch bond on an integrated circuit bond pad and method of making the same
DE102007018914B4 (de) * 2007-04-19 2019-01-17 Infineon Technologies Ag Halbleiterbauelement mit einem Halbleiterchipstapel und Verfahren zur Herstellung desselben

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US4806188A (en) * 1988-03-04 1989-02-21 E. I. Du Pont De Nemours And Company Method for fabricating multilayer circuits
US5176772A (en) * 1989-10-05 1993-01-05 Asahi Glass Company Ltd. Process for fabricating a multilayer ceramic circuit board
EP0535711A3 (en) * 1991-10-04 1993-12-01 Matsushita Electric Ind Co Ltd Method for producing multilayered ceramic substrate
US5239448A (en) * 1991-10-28 1993-08-24 International Business Machines Corporation Formulation of multichip modules
US5378313A (en) * 1993-12-22 1995-01-03 Pace; Benedict G. Hybrid circuits and a method of manufacture

Also Published As

Publication number Publication date
FR2716037A1 (fr) 1995-08-11
GB9502266D0 (en) 1995-03-29
US5562837A (en) 1996-10-08
GB2287132A (en) 1995-09-06
GB2287132B (en) 1997-10-15

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