JPS57184239A - Substrate for semiconductor device - Google Patents

Substrate for semiconductor device

Info

Publication number
JPS57184239A
JPS57184239A JP6900981A JP6900981A JPS57184239A JP S57184239 A JPS57184239 A JP S57184239A JP 6900981 A JP6900981 A JP 6900981A JP 6900981 A JP6900981 A JP 6900981A JP S57184239 A JPS57184239 A JP S57184239A
Authority
JP
Japan
Prior art keywords
substrate
lead pins
semiconductor device
thermal expansion
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6900981A
Other languages
Japanese (ja)
Inventor
Kazuo Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6900981A priority Critical patent/JPS57184239A/en
Publication of JPS57184239A publication Critical patent/JPS57184239A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of a solder crack based on the difference of the thermal expansion of the substrate and the semiconductor device by mounting lead pins to both surfaces of the substrate. CONSTITUTION:The lead pins 23 are also set up to the surface to which the semiconductor device of the insulating substrate 21 is mounted. Accordingly, since the semiconductor device can be soldered on the lead pins 22, only said lead pins are deformed even when there is the difference of thermal expansion, and a crack is not generated in solder. Both surfaces of the substrate have the lead pins. When the substrate is made of ceramics such as alumina, sections where the lead pins 22 are mounted on the substrate are metallized 24, and the lead pins 22 are brazed onto the metallized sections.
JP6900981A 1981-05-08 1981-05-08 Substrate for semiconductor device Pending JPS57184239A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6900981A JPS57184239A (en) 1981-05-08 1981-05-08 Substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6900981A JPS57184239A (en) 1981-05-08 1981-05-08 Substrate for semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184239A true JPS57184239A (en) 1982-11-12

Family

ID=13390161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6900981A Pending JPS57184239A (en) 1981-05-08 1981-05-08 Substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184239A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038842A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor device
JPS6390862U (en) * 1986-12-01 1988-06-13

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6038842A (en) * 1983-08-12 1985-02-28 Hitachi Ltd Semiconductor device
JPH0532907B2 (en) * 1983-08-12 1993-05-18 Hitachi Ltd
JPS6390862U (en) * 1986-12-01 1988-06-13

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