JPH0532907B2 - - Google Patents
Info
- Publication number
- JPH0532907B2 JPH0532907B2 JP58146324A JP14632483A JPH0532907B2 JP H0532907 B2 JPH0532907 B2 JP H0532907B2 JP 58146324 A JP58146324 A JP 58146324A JP 14632483 A JP14632483 A JP 14632483A JP H0532907 B2 JPH0532907 B2 JP H0532907B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- semiconductor element
- plastic substrate
- substrate
- sealant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 39
- 239000011521 glass Substances 0.000 claims description 34
- 239000004593 Epoxy Substances 0.000 claims description 24
- 239000004033 plastic Substances 0.000 claims description 13
- 229920003023 plastic Polymers 0.000 claims description 13
- 239000000565 sealant Substances 0.000 claims description 11
- 239000000499 gel Substances 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004590 silicone sealant Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 11
- 238000007789 sealing Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、ピングリツドアレイ型半導体パツケ
ージに関し、特に高信頼性でかつ安価なピングリ
ツドアレイ型半導体パツケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pin grid array type semiconductor package, and particularly to a highly reliable and inexpensive pin grid array type semiconductor package.
半導体パツケージにおいて半導体チツプ（ペレ
ツト）を樹脂（プラスチツク）封止することが行
われている。本発明者の検討によればこの方式に
よりレジンモールドをする場合、半導体素子に応
力がかかつたり、金型からの離型性の良いプラス
チツクスが使用される結果、逆に半導体素子との
接着性を低下させ、当該素子との界面で剥離を起
こしたり、また耐湿性に問題を生じ水分の侵入を
許したりするなど各種問題を生じる。
In semiconductor packages, semiconductor chips (pellets) are encapsulated with resin (plastic). According to the inventor's study, when resin molding is performed using this method, stress is applied to the semiconductor element, and as a result of using plastics that have good release properties from the mold, conversely, adhesion with the semiconductor element may occur. This causes various problems such as deterioration of properties, peeling at the interface with the element, and problems with moisture resistance, allowing moisture intrusion.
一方、半導体パツケージにおいて、半導体素子
を搭載するベースにセラミツク基板を使用し、該
基板にピンを立設するいわゆるピングリツトアレ
イ型パツケージがあり、セラミツク基板に半導体
素子を実装しハーメチツクシールすることも行わ
れている（雑誌Semiconductor World 1982年11
月号P33）。 On the other hand, in semiconductor packages, there is a so-called pin array type package that uses a ceramic substrate as a base on which a semiconductor element is mounted and pins are set upright on the substrate.The semiconductor element is mounted on the ceramic substrate and hermetically sealed. (Magazine Semiconductor World November 1982)
Monthly issue P33).
しかし、セラミツク基板は高価であるなどの問
題があり、コストの安い基板を使用して、しかも
多ピン化を達成できることが望まれていた。 However, ceramic substrates have problems such as being expensive, and it has been desired to use a low-cost substrate and also be able to increase the number of pins.
本発明は、半導体素子およびコネクタワイヤに
応力がかからず当該素子との接合性が良く、耐湿
性に優れた封止を達成したピングリツドアレイ型
半導体パツケージを提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a pin grid array type semiconductor package that does not apply stress to semiconductor elements and connector wires, has good bonding properties with the semiconductor elements, and achieves sealing with excellent moisture resistance.
また、本発明はコストの安い基板により、多ピ
ン化を達成したピングリツドアレイ型半導体パツ
ケージを提供することを目的とする。 Another object of the present invention is to provide a pin grid array type semiconductor package that achieves a large number of pins using a low-cost substrate.
さらに、本発明は実装基板への実装が容易であ
り、実装基板との熱膨張係数差による熱応力のか
からないピングリツドアレイ型半導体パツケージ
を提供することを目的とする。 A further object of the present invention is to provide a pin grid array type semiconductor package that is easy to mount on a mounting board and is not subject to thermal stress due to a difference in thermal expansion coefficient with the mounting board.
本発明の前記ならびにそのほかの目的と新規な
特徴は、本明細書の記述および添付図面からあき
らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば次のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ガラス・エポキシ、ガラス・ポリイ
ミドまたはガラス・フルオロカーボンからなるプ
ラスチツク基板上に取付けた半導体素子と、前記
半導体素子内の配線を外部に引き出す多数のコネ
クタワイヤと、前記プラスチツク基板の貫通孔内
に立設されて半田付けされ、かつ前記プラスチツ
ク基板上に形成されたメタライズ層を介して前記
コネクタワイヤと電気的に接続された多数のピン
と、少なくとも前記半導体素子および前記コネク
タワイヤを覆い気密封止する、加熱することによ
りゲル化するシリコーン系のシーリング剤と、前
記シーリング剤の流れ止めに使用され、その内壁
面の位置が前記ピンの位置よりも内側に配置され
たダムと、前記ダムを介してまたは介さずに直接
前記プラスチツク基板に冠着されたキヤツプとを
有することにより、多ピン化に対応可能な信頼性
の高いピングリツドアレイ型半導体パツケージを
安価に提供することができる。 That is, a semiconductor element mounted on a plastic substrate made of glass epoxy, glass polyimide, or glass fluorocarbon, a large number of connector wires that lead out the wiring inside the semiconductor element to the outside, and a connector wire that is mounted on a plastic substrate made of glass epoxy, glass polyimide, or glass fluorocarbon. covering and hermetically sealing at least the semiconductor element and the connector wire with a large number of pins provided and soldered and electrically connected to the connector wire via a metallized layer formed on the plastic substrate; A silicone-based sealant that gels when heated; a dam used to stop the flow of the sealant and whose inner wall surface is located inside the position of the pin; By having the cap directly attached to the plastic substrate without intervening, it is possible to provide a highly reliable pin grid array type semiconductor package that can accommodate a large number of pins at a low cost.
実施例 １
第１図は本発明の半導体素子の断面図であり、
同図にて、１は半導体素子（半導体チツプ）で、
例えばシリコン単結晶基板から成る。周知の技術
によつて、この半導体チツプ１内には多数の回路
素子が形成され、回路機能を与えている。回路素
子は、例えばCMOS（Complementary Metal
Oxide Semiconductor）構成から成り、これら
の回路素子によつて、例えば隣理回路あるいはメ
モリの回路機能が形成されている。この半導体チ
ツプ１は、ガラス・エポキシ基板２に、接合材料
例えばエポキシ系樹脂接着剤３で接合されてい
る。基板としては、ガラス・ポリイミド基板又は
ガラス・フルオロカーボン基板等を用いることも
できる。Example 1 FIG. 1 is a cross-sectional view of a semiconductor element of the present invention,
In the same figure, 1 is a semiconductor element (semiconductor chip),
For example, it is made of a silicon single crystal substrate. A large number of circuit elements are formed within this semiconductor chip 1 using well-known techniques to provide circuit functions. The circuit elements are, for example, CMOS (Complementary Metal
These circuit elements form an adjacent circuit or a memory circuit function, for example. This semiconductor chip 1 is bonded to a glass epoxy substrate 2 using a bonding material such as an epoxy resin adhesive 3. As the substrate, a glass polyimide substrate, a glass fluorocarbon substrate, or the like can also be used.
半導体チツプ１はそれに設けられた多くのボン
デイングパツト（図示せず）を介して、コネクタ
ワイヤ（例えばAl線）４によつて半導体チツプ
１内の配線を外部へ引き出している。ガラス・エ
ポキシ基板２には、マスク蒸着あるいはプリント
配線などによりメタライズ層例えばAl配線層５
が形成され、半導体チツプ１の配線端部がこの配
線層５とボンデイングされ電気的に接続される。
さらに、このメタライズ層５はガラス・エポキシ
基板２に貫通するように設けたスルーホール６を
介して外部ピン７に電気的に接続される。このピ
ン７は、ガラス・エポキシ基板２にに、融点の高
い半田例えばSn−Pb半田８により、多数立設す
る。そして、半導体素子１をコネクタワイヤ４と
ともに、シリコーン系のシーリング剤９により封
止する。このシリコーン系のシーリング剤（以下
チツプコート材料という）は、通常はゾルの状態
にある。このゾルをポツテイングして半導体素子
１およびコネクタワイヤ４を覆う際に、ゾルの流
れ止めにダム１０を使用する。ダム１０は、シー
リング剤９とピン７との接触を防ぐために、その
内壁面の位置がピン７の位置よりも内側（半導体
チツプ１側）に配置されている。ダム１０として
はガラス・エポキシ材料等基板と同一材料を用い
ればよい。ダム１０によりその流動が抑止された
上記ゾルを加熱すると、このゾルはゲル化する。
この際、半導体素子１にかかる応力は少なくて済
み、また半導体素子およびコネクタワイヤとの接
合性が良く、さらに、耐湿性に優れた封止が行わ
れる。この封止に使用されるチツプコート材料と
しては、例えば信越化学工業(株)社製KJR9010が
代表例として挙げられる。 Semiconductor chip 1 has a number of bonding pads (not shown) provided thereon, and interconnections inside semiconductor chip 1 are led out to the outside by connector wires (for example, Al wires) 4. A metallized layer such as an Al wiring layer 5 is formed on the glass epoxy substrate 2 by mask vapor deposition or printed wiring.
is formed, and the wiring ends of the semiconductor chip 1 are bonded and electrically connected to this wiring layer 5.
Further, this metallized layer 5 is electrically connected to an external pin 7 via a through hole 6 provided to penetrate the glass epoxy substrate 2. A large number of pins 7 are erected on the glass epoxy substrate 2 using a solder having a high melting point, such as Sn--Pb solder 8. Then, the semiconductor element 1 and the connector wire 4 are sealed with a silicone sealant 9. This silicone sealant (hereinafter referred to as chip coat material) is usually in the form of a sol. When this sol is potted to cover the semiconductor element 1 and the connector wire 4, a dam 10 is used to stop the flow of the sol. In order to prevent the sealant 9 from coming into contact with the pins 7, the dam 10 has an inner wall surface located inside the pins 7 (on the semiconductor chip 1 side). The dam 10 may be made of the same material as the substrate, such as glass or epoxy material. When the above-mentioned sol whose flow is suppressed by the dam 10 is heated, this sol becomes a gel.
At this time, the stress applied to the semiconductor element 1 is small, the bondability between the semiconductor element and the connector wire is good, and sealing with excellent moisture resistance is achieved. A representative example of the chip coat material used for this sealing is KJR9010 manufactured by Shin-Etsu Chemical Co., Ltd.
また、第１図にて、１１はキヤツプであり、例
えばガラス・エポキシ基板２と同一熱膨張率とな
るように同一材料すなわちガラス・エポキシより
なるキヤツプを使用することが好ましい。上記ゲ
ルにより確実な気密封止が行れるので、このキヤ
ツプ１１は特に気密封止を意図したものではな
い。もちろん、気密封止としてもさしつかえな
い。ただ、上記ゲルは耐湿性に富むが、膨潤に似
た状態にあるので、コネクタワイヤ４や半導体素
子１を外的環境から機械的に保護する必要上、キ
ヤツプ１１を、少なくともゲル封止部分に冠着し
ている。したがつて、ハーメチツクシールのごと
き鉛ガラスなどによる気密封止を必要とせず、第
１図に示すように、キヤツプ１１とガラス・エポ
キシ基板２とを、単に、エポキシ系樹脂接着剤１
２等を用いて接合しておけばよく、キヤツプ１１
をガラス・エポキシ基板２に嵌合して冠着しても
よい。 Further, in FIG. 1, reference numeral 11 denotes a cap, and it is preferable to use a cap made of the same material, ie, glass epoxy, so as to have the same coefficient of thermal expansion as the glass epoxy substrate 2, for example. This cap 11 is not particularly intended to be hermetically sealed, since the gel provides a reliable hermetic seal. Of course, it can also be hermetically sealed. However, although the above-mentioned gel is highly moisture resistant, it is in a state similar to swelling, and therefore, it is necessary to mechanically protect the connector wire 4 and the semiconductor element 1 from the external environment, so the cap 11 is attached at least to the gel-sealed part. wearing a crown. Therefore, there is no need for hermetic sealing using lead glass or the like, and as shown in FIG.
It is sufficient to connect them using a cap 11.
It is also possible to fit and attach the glass epoxy substrate 2 to the glass epoxy substrate 2.
第２図は第１図のキヤツプを取去つた状態の半
導体装置の平面図であり、第１図と同じ符号を付
した部分の機能は同一でありその説明を省略する
が、第２図にて、ガラス・エポキシ基板２に符号
７で示された部分は当該基板２に多数立設された
ピン７の頭部を表わしてある。 FIG. 2 is a plan view of the semiconductor device with the cap shown in FIG. The portions indicated by the reference numeral 7 on the glass epoxy substrate 2 represent the heads of a large number of pins 7 erected on the substrate 2.
実施例 ２
第３図は本発明の他の実施例を示し、この実施
例はダムを省略して半導体装置を構成してなる例
を示す。すなわち、ガラス・エポキシ基板２の溝
部１３に半導体チツプ１を実施例１と同様にして
固着し、コネクタワイヤ４により当該チツプ１内
のボンデイングパツドをメタライズ層（図示せ
ず）を経由してピン７に電気的に接続し、半導体
チツプ１およびコネクタワイヤ４を包囲して実施
例１と同様のチツプコート材料９９で封止する。
この際、ガラス・エポキシ基板２の段差がダムの
役目をするので、ダムを必要とせずに封止が完了
する。封止後、ガラス・エポキシ基板２上に実施
例１と同様にキヤツプ１１を固着する。Embodiment 2 FIG. 3 shows another embodiment of the present invention, and this embodiment shows an example in which a semiconductor device is constructed by omitting a dam. That is, the semiconductor chip 1 is fixed in the groove 13 of the glass epoxy substrate 2 in the same manner as in Example 1, and the bonding pad in the chip 1 is connected to the pin via the metallized layer (not shown) using the connector wire 4. 7, and the semiconductor chip 1 and connector wire 4 are surrounded and sealed with a chip coat material 99 similar to that of the first embodiment.
At this time, since the step of the glass epoxy substrate 2 serves as a dam, sealing is completed without the need for a dam. After sealing, the cap 11 is fixed onto the glass epoxy substrate 2 in the same manner as in Example 1.
実施例 ３
第４図は本発明のさらに他の実施例を示す。こ
の実施例はダム１０上にキヤツプ１１を載置して
なる半導体装置の例を示す。すなわち、ガラス・
エポキシ基板２の凹部に半導体チツプ１を実施例
１と同様にして固着し、コネクタワイヤ４により
チツプ１内のボンデイングパツドと基板表面上の
メタライズ層（図示せず）を経由してピン７に接
続している。このワイヤ４とチツプ１とを実施例
１と同様のチツプコート材料９で封止する。基板
表面上に設けられたダム１０にキヤツプ１１をエ
ポキシ樹脂等を用いて固着している。これにより
封止された内部にガスが存在しないようにでき、
信頼性を向上できる。Embodiment 3 FIG. 4 shows yet another embodiment of the present invention. This embodiment shows an example of a semiconductor device in which a cap 11 is placed on a dam 10. In other words, glass
The semiconductor chip 1 is fixed in the recess of the epoxy board 2 in the same manner as in Example 1, and the connector wire 4 is connected to the pin 7 via the bonding pad inside the chip 1 and the metallized layer (not shown) on the surface of the board. Connected. The wire 4 and the chip 1 are sealed with the same chip coat material 9 as in the first embodiment. A cap 11 is fixed to a dam 10 provided on the surface of the substrate using epoxy resin or the like. This ensures that no gas exists inside the sealed interior.
Can improve reliability.
ゲル化されたチツプコート材料は半導体チツプ
やコネクタワイヤとの接合性が良く、剥離を生ぜ
ず、湿気の侵入を阻止し、水膜の形成を防止して
極めて耐湿性に富み、不純物イオンの影響を受け
ず、かつ樹脂封止の際にみられるような樹脂注入
圧力によるワイヤ変形、チツプおよびワイヤへの
応力の付与などがみられず、高信頼度の半導体パ
ツケージを提供できる。
Gelled chip coat material has good bonding properties with semiconductor chips and connector wires, does not cause peeling, prevents moisture intrusion, prevents water film formation, is extremely moisture resistant, and is highly resistant to the effects of impurity ions. Furthermore, there is no wire deformation or stress applied to the chip and wires due to resin injection pressure, which occurs during resin sealing, and a highly reliable semiconductor package can be provided.
また、安価なガラス・エポキシ基板、ガラス・
ポリイミド基板、ガラス・フルオロカーボン基板
等を用いているので、従来のセラミツクパツケー
ジに比してコストを低減できる。 We also offer inexpensive glass/epoxy substrates, glass/
Since a polyimide substrate, glass/fluorocarbon substrate, etc. are used, costs can be reduced compared to conventional ceramic packages.
また、半導体装置が増々多ピン化するとき従来
の構造ではその微細化がプロセス上問題となると
予想される。これに対し、本発明は耐湿性の問題
を上記のごとく解消し得るとともに、コネクタワ
イヤなどにかかる応力負担を軽減できるので、多
ピン化に対し有効に対処できる。 Further, as semiconductor devices increase in number of pins, it is expected that miniaturization of conventional structures will become a problem in terms of processing. On the other hand, the present invention can solve the moisture resistance problem as described above, and can also reduce the stress burden on connector wires, so that it can effectively cope with the increase in the number of pins.
さらに、本発明パツケージを実装基板に実装す
る場合、ピンがガラス・エポキシ基板に立設され
ているので、実装も容易であり、この場合実装基
板がガラス・エポキシ基板であるときには両者の
熱膨張係数差による応力がかからないという利点
もある。 Furthermore, when mounting the package of the present invention on a mounting board, the pins are installed upright on the glass/epoxy board, so mounting is easy.In this case, if the mounting board is a glass/epoxy board, the thermal expansion coefficient of both Another advantage is that no stress is applied due to the difference.
さらに、ガラス・エポキシのようなプラスチツ
ク基板を用いたパツケージでは、ピンとスルーホ
ールとの密着が必ずしも良好とは限らず、往々に
してそれらの間に空〓が残つていることがあるた
め、仮に半導体素子およびコネクタワイヤのみな
らずピンの上部までをシーリング剤で覆つてしま
うと、実装時の半田付け等の高温加熱によつてピ
ンを固定する半田が不所望にも溶融されてしまつ
たような場合には、シーリング剤が前述のように
軟質であることから、上記空〓内の気体の膨張に
よつて溶融半田がシーリング剤中に押し出されて
しまい、この溶融半田によるピン間のリーク等に
よつてピン間の電気的特性の信頼性が損なわれて
しまうことがある。 Furthermore, in packages using plastic substrates such as glass epoxy, the pins and through holes do not always adhere well, and there are often spaces left between them. If you cover not only the element and connector wire but also the top of the pin with sealant, the solder that secures the pin may undesirably melt due to high-temperature heating during soldering during mounting. Because the sealant is soft as mentioned above, the expansion of the gas in the space forces the molten solder into the sealant, causing leakage between the pins due to this molten solder. As a result, the reliability of the electrical characteristics between the pins may be impaired.
また、ピンとスルーホールとの間にできた上記
空〓が、不所望にもガラス・エポキシ基板の上下
面間に連続して形成されているような場合には、
充填時（この時、シーリング剤は流動性のあるゾ
ル状態にある）にシーリング剤が上記空〓を通じ
てガラス・エポキシ基板の下面に滲み出し、ピン
の表面を汚すことによつて、半田付けによるピン
と実装基板との接続信頼性が損なわれてしまうこ
とがある。 Furthermore, if the above-mentioned void created between the pin and the through hole is undesirably continuous between the top and bottom surfaces of the glass/epoxy board,
During filling (at this time, the sealant is in a fluid sol state), the sealant oozes out through the above-mentioned void onto the bottom surface of the glass/epoxy board, staining the surface of the pin, and causing the pin to be soldered. Connection reliability with the mounting board may be impaired.
これに対し、本発明はダムの内壁面の位置をピ
ンの位置よりも内側に配置することによつて、シ
ーリング剤とピンとの接触を防ぐようにしている
ので、プラスチツク基板を用いたパツケージ特有
の上記した問題点を解消することもできる。 In contrast, the present invention prevents contact between the sealant and the pins by arranging the inner wall surface of the dam inside the position of the pins, which is unique to packages using plastic substrates. The above problems can also be solved.
以上本発明者によつてなされた発明を実施例に
もとづき具体的に説明したが、本発明は上記実施
例に限定されるものではなく、その要旨を逸脱し
ない範囲で種々変更可能であることはいうまでも
ない。 Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
以上の説明では主として本発明者によつてなさ
れた発明をその背景となつた分野である半導体装
置のパツケージ技術について適用した場合につい
て説明したが、電子部品のパツケージ技術につい
て適用しても差支えない。
In the above explanation, the invention made by the present inventor has been mainly applied to the packaging technology of semiconductor devices, which is the background field, but the invention may also be applied to the packaging technology of electronic components.
本発明パツケージは発熱の小さい、低消費電力
の素子例えば前記したCMOS用途に好適である。 The package of the present invention is suitable for devices that generate little heat and consume low power, such as the CMOS described above.
第１図は本発明の実施例を示す断面図、第２図
はキヤツプを取去つた状態の本発明実施例を示す
平面図、第３図は本発明の他の実施例を示す断面
図、第４図は本発明の変形例を示す断面図であ
る。
１……半導体素子、２……ガラス・エポキシ基
板、３……接合材料、４……コネクタワイヤ、５
……配線層（メタライズ層）、６……スル−ホー
ル、７……ピン、８……半田、９……シリコーン
系ゲル、１０……ダム、１１……キヤツプ、１２
……接合材料、１３……半導体素子搭載部。
FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a plan view showing the embodiment of the invention with the cap removed, and FIG. 3 is a sectional view showing another embodiment of the invention. FIG. 4 is a sectional view showing a modification of the present invention. 1...Semiconductor element, 2...Glass/epoxy substrate, 3...Joining material, 4...Connector wire, 5
...Wiring layer (metallized layer), 6...Through hole, 7...Pin, 8...Solder, 9...Silicone gel, 10...Dam, 11...Cap, 12
...Joining material, 13...Semiconductor element mounting part.
Claims (1)
はガラス・フルオロカーボンからなるプラスチツ
ク基板上に取付けた半導体素子と、前記半導体素
子内の配線を外部に引き出す多数のコネクタワイ
ヤと、前記プラスチツク基板の貫通孔内に立設さ
れて半田付けされ、かつ前記プラスチツク基板上
に形成されたメタライズ層を介して前記コネクタ
ワイヤと電気的に接続された多数のピンと、少な
くとも前記半導体素子および前記コネクタワイヤ
を覆い気密封止する、加熱することによりゲル化
するシリコーン系のシーリング剤と、前記シーリ
ング剤の流れ止めに使用され、その内壁面の位置
が前記ピンの位置よりも内側に配置されたダム
と、前記ダムを介してまたは介さずに直接前記プ
ラスチツク基板に冠着されたキヤツプとを有する
ことを特徴とするピングリツドアレイ型半導体パ
ツケージ。1. A semiconductor element mounted on a plastic substrate made of glass epoxy, glass polyimide, or glass fluorocarbon, a large number of connector wires that lead out the wiring inside the semiconductor element to the outside, and a plurality of connector wires installed in a through hole of the plastic substrate. a plurality of pins that are soldered and electrically connected to the connector wire through a metallized layer formed on the plastic substrate, and at least the semiconductor element and the connector wire, which are covered and hermetically sealed; and heating. A silicone sealant that gels when the sealant is applied, a dam used to stop the flow of the sealant and whose inner wall surface is located inside the position of the pin, and 1. A pin grid array type semiconductor package, comprising a cap directly attached to the plastic substrate without being attached to the plastic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14632483A JPS6038842A (en) | 1983-08-12 | 1983-08-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14632483A JPS6038842A (en) | 1983-08-12 | 1983-08-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6038842A JPS6038842A (en) | 1985-02-28 |
| JPH0532907B2 true JPH0532907B2 (en) | 1993-05-18 |
Family
ID=15405092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14632483A Granted JPS6038842A (en) | 1983-08-12 | 1983-08-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038842A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420667B2 (en) * | 1973-12-30 | 1979-07-24 | ||
| JPS5724554A (en) * | 1980-07-22 | 1982-02-09 | Nec Corp | Semiconductor device |
| JPS57184239A (en) * | 1981-05-08 | 1982-11-12 | Nec Corp | Substrate for semiconductor device |
| JPS57210645A (en) * | 1981-06-19 | 1982-12-24 | Toshiba Corp | Hybrid integrated circuit module and manufacture thereof |
| JPS58159355A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Manufacture of semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS516868U (en) * | 1974-06-29 | 1976-01-19 | ||
| JPS5420667U (en) * | 1977-07-14 | 1979-02-09 | ||
| JPS56139253U (en) * | 1980-03-19 | 1981-10-21 |
-
1983
- 1983-08-12 JP JP14632483A patent/JPS6038842A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420667B2 (en) * | 1973-12-30 | 1979-07-24 | ||
| JPS5724554A (en) * | 1980-07-22 | 1982-02-09 | Nec Corp | Semiconductor device |
| JPS57184239A (en) * | 1981-05-08 | 1982-11-12 | Nec Corp | Substrate for semiconductor device |
| JPS57210645A (en) * | 1981-06-19 | 1982-12-24 | Toshiba Corp | Hybrid integrated circuit module and manufacture thereof |
| JPS58159355A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6038842A (en) | 1985-02-28 |
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