IN2014DN07180A - - Google Patents

Info

Publication number
IN2014DN07180A
IN2014DN07180A IN7180DEN2014A IN2014DN07180A IN 2014DN07180 A IN2014DN07180 A IN 2014DN07180A IN 7180DEN2014 A IN7180DEN2014 A IN 7180DEN2014A IN 2014DN07180 A IN2014DN07180 A IN 2014DN07180A
Authority
IN
India
Prior art keywords
substrate layers
bonding material
layers
layer
electrical circuit
Prior art date
Application number
Other languages
English (en)
Inventor
Ernest Clyde Parker
Philip Joseph Lauriello
Original Assignee
Crane Electronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Crane Electronics filed Critical Crane Electronics
Priority claimed from PCT/US2013/024907 external-priority patent/WO2013119643A1/en
Publication of IN2014DN07180A publication Critical patent/IN2014DN07180A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H05K13/0465—Surface mounting by soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/83204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H01L2224/83211—Applying energy for connecting using a reflow oven with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
IN7180DEN2014 2012-02-08 2013-02-06 IN2014DN07180A (enExample)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261596652P 2012-02-08 2012-02-08
US13/758,843 US9888568B2 (en) 2012-02-08 2013-02-04 Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
PCT/US2013/024907 WO2013119643A1 (en) 2012-02-08 2013-02-06 Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module

Publications (1)

Publication Number Publication Date
IN2014DN07180A true IN2014DN07180A (enExample) 2015-04-24

Family

ID=48902707

Family Applications (1)

Application Number Title Priority Date Filing Date
IN7180DEN2014 IN2014DN07180A (enExample) 2012-02-08 2013-02-06

Country Status (4)

Country Link
US (2) US9888568B2 (enExample)
JP (1) JP6257047B2 (enExample)
KR (1) KR102103196B1 (enExample)
IN (1) IN2014DN07180A (enExample)

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DE102014206608A1 (de) 2014-04-04 2015-10-08 Siemens Aktiengesellschaft Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube
DE102014206606A1 (de) 2014-04-04 2015-10-08 Siemens Aktiengesellschaft Verfahren zum Montieren eines elektrischen Bauelements auf einem Substrat
US9831768B2 (en) 2014-07-17 2017-11-28 Crane Electronics, Inc. Dynamic maneuvering configuration for multiple control modes in a unified servo system
US9230726B1 (en) 2015-02-20 2016-01-05 Crane Electronics, Inc. Transformer-based power converters with 3D printed microchannel heat sink
US9589864B2 (en) * 2015-05-14 2017-03-07 Qorvo Us, Inc. Substrate with embedded sintered heat spreader and process for making the same
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US9780635B1 (en) 2016-06-10 2017-10-03 Crane Electronics, Inc. Dynamic sharing average current mode control for active-reset and self-driven synchronous rectification for power converters
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US9742183B1 (en) 2016-12-09 2017-08-22 Crane Electronics, Inc. Proactively operational over-voltage protection circuit
WO2019040753A1 (en) * 2017-08-23 2019-02-28 Georgia Tech Research Corporation DIRECT LOW TEMPERATURE CONNECTION OF ALUMINUM NITRIDE TO ALSIC SUBSTRATES
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US10425080B1 (en) 2018-11-06 2019-09-24 Crane Electronics, Inc. Magnetic peak current mode control for radiation tolerant active driven synchronous power converters
US10906274B2 (en) * 2018-11-14 2021-02-02 Qorvo Us, Inc. Laminate substrate with sintered components
GB201917680D0 (en) * 2019-12-04 2020-01-15 Sinclair Grant Wafr v1
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EP3840548A1 (en) * 2019-12-20 2021-06-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same
CN111799251B (zh) * 2020-07-09 2023-06-02 华羿微电子股份有限公司 采用多芯片堆叠结构的功率分立器件及其制备方法
US11497112B2 (en) * 2020-12-11 2022-11-08 Toyota Motor Engineering & Manufacturing North America, Inc. Driver board assemblies and methods of forming a driver board assembly
JPWO2022153631A1 (enExample) * 2021-01-14 2022-07-21
TWI796738B (zh) * 2021-07-23 2023-03-21 先豐通訊股份有限公司 具有波導管的線路板結構及其製作方法
US20250107050A1 (en) * 2023-09-25 2025-03-27 Delphi Technologies Ip Limited Systems and methods for a direct printed heat sink
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US9888568B2 (en) 2018-02-06
HK1204204A1 (en) 2015-11-06
JP2015508235A (ja) 2015-03-16
JP6257047B2 (ja) 2018-01-10
HK1203739A1 (en) 2015-10-30
US20130201631A1 (en) 2013-08-08
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US20180146547A1 (en) 2018-05-24

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