HRP20161195T1 - Smanjenje efekta opterećenja izvora kod spin prijenosa sile magnetnootporne memorije s nasumičnim pristupom (stt-mram) - Google Patents

Smanjenje efekta opterećenja izvora kod spin prijenosa sile magnetnootporne memorije s nasumičnim pristupom (stt-mram) Download PDF

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Publication number
HRP20161195T1
HRP20161195T1 HRP20161195TT HRP20161195T HRP20161195T1 HR P20161195 T1 HRP20161195 T1 HR P20161195T1 HR P20161195T T HRP20161195T T HR P20161195TT HR P20161195 T HRP20161195 T HR P20161195T HR P20161195 T1 HRP20161195 T1 HR P20161195T1
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Croatia
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layer
mtj structure
alternating current
memory cell
magnetic field
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HRP20161195TT
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English (en)
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Kangho Lee
Seung H. Kang
Xiaochun Zhu
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QUALCOMM Incorporated, Attn: International IP Administration
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Publication of HRP20161195T1 publication Critical patent/HRP20161195T1/hr

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/10Magnetoresistive devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1675Writing or programming circuits or methods
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/80Constructional details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)

Claims (15)

1. Postupak dizajniranja memorijske ćelije koja obuhvaća MTJ strukturu spojenu s pristupnim odašiljačem, postupak obuhvaća: uporabu računalnog programa za : određivanje izmjeničnog omjera MTJ strukture koja smanjuje efekt opterećenja izvora memorijske ćelije, omjer izmjenične struje predstavlja omjer: prvi omjer izmjenične struje potreban za promjenu MTJ strukture od stanja visokog otpora do stanja niskog otpora; od jačine struje potrebne za drugo prebacivanje za prebacivanje MTJ strukture od stanja niskog otpora do stanja visokog otpora; i prilagođavanja dizajna barem jednog sloja MTJ strukture da modificira offset magnetsko polje koje je vezano za slobodni sloj MTJ strukture, na način da offset magnetsko polje uzrokuje da MTJ struktura pokazuje omjer izmjenične struje.
2. Postupak sukladno zahtjevu 1, pri čemu prilagodba obuhvaća prilagođavanje memorijske ćelije iz prve konfiguracije koja ima pristupni odašiljač električno spojen s pričvršćenim slojem MJT strukture drugoj konfiguraciji koja ima pristupni tranzistor električno spojen sa slobodnim slojem MTJ strukture.
3. Postupak sukladno zahtjevu 2, pri čemu prilagodba memorijske ćelije iz prve do druge konfiguracije uključuje promjenu redoslijeda slaganja slobodnog i pričvršćenog sloja.
4. Postupak sukladno zahtjevu 2, pri čemu prilagodba memorijske ćelije iz prve do druge konfiguracije uključuje promjenu trase vodećeg puta između pristupnog odašiljača i MTJ strukture.
5. Postupak sukladno zahtjevu 1, pri čemu određivanje omjera izmjenične struje obuhvaća: određivanje izmjenične karakteristike memorijske ćelije; i izvođenje analize linije opterećenja prijemnika kako bi se odredio omjer izmjenične struje.
6. Postupak sukladno zahtjevu 1, nadalje obuhvaća: određivanje količine modifikacije offset magnetskog polja temeljem magnitude omjera izmjenične struje.
7. Postupak sukladno zahtjevu 6, pri čemu je količina modifikacije offset magnetskog polja određena pomoću barem jednog od matematičkih modela i empirijskih modela veze između omjera izmjenične struje, offset magnetskog polja, i snage polja izmjenične struje.
8. Postupak sukladno zahtjevu 1, pri čemu prilagodba dizajna barem jednog sloja MTJ strukture obuhvaća prilagodbu debljine pričvršćenog sloja MTJ strukture.
9. Postupak sukladno zahtjevu 8, nadalje obuhvaća, prije prilagođavanja debljine pričvršćenog sloja: proizvodnju memorijske ćelije; mjerenje spin prijenosa sile (STT) mijenjanjem karakteristika memorijske ćelije; provođenje linije opterećenja prijenosnika kako bi se odredio omjer izmjenične struje; primjenu vanjskog magnetnog polja kako bi se simuliralo djelovanje MTJ strukture s prilagođenom debljinom pričvršćenog sloja; i testiranje termalne stabilnosti memorijske ćelije u prisutnostot eksternog magnetskog polja.
10. Postupak sukladno zahtjevu 9, pri čemu je omjer izmjenične struje manji od neprilagođenog omjera izmjenične struje MTJ strukture bez offset magnetskog polja i pri čemu je pričvršćeni sloj sintetički sloj koji uključuje: prvi magnetski sloj koji je odmah uz slobodan sloj; i drugi magnetski sloj koji ima magnetski moment koji je antiparalelan magnetskom momentu prvog magnetskog sloja, pri čemu prilagodba gustoće pričvršćenog sloja obuhvaća smanjenje gustoće drugog magnetskog sloja kako bi se na offset magnetskog polja primijenio negativni pomak.
11. Uređaj obuhvaća: memorijsku ćeliju koja obuhvaća: strukturu magnetskog tunelskog spoja (MTJ) koja uključuje: slobodni sloj spojen na bit liniju; i pričvršćeni sloj, pri čemu je magnetski moment slobodnog sloja supstancijalno paralelan magnetskom momentu pričvršćenog sloja u prvom stanju i supstancijalno antiparalelan magnetskom momentu pričvršćenog sloja u drugom stanju, naznačen time što pričvršćeni sloj ima fizičku dimenziju za proizvodnju offset magnetskog polja koje odgovara prvoj izmjeničnoj struji MTJ strukture kako bi se omogućilo izmjenjivanje između prvog i drugog stanja kada je prvi napon primijenjen iz bit linije na liniju izvora spojenu s pristupnim prijemnikom i druga izmjenična struja omogućuje izmjenjivanje između drugog stanja i prvog stanja kada je prvi napon primijenjen iz linije izvora na bit liniju.
12. Uređaj sukladno zahtjevu 11, pri čemu je prva izmjenična struja niža od prvog praga povezanog s karakteristikama operativne struje pristupnog prijemnika, i pri čemu operativne karakteristike prijemnika obuhvaćaju struju iz odvodnog terminala pristupnog prijemnika na terminal izvora pristupnog prijemnika pod prethodno određenim naponom između ulaznog terminala pristupnog prijemnika i odvodnog terminala pristupnog prijemnika.
13. Uređaj sukladno zahtjevu 11, pri čemu je slobodni sloj smješten na prvoj udaljenosti od odvodnog terminala, i pri čemu vodeći put električno spaja odvodni terminal sa slobodnim slojem.
14. Uređaj sukladno zahtjevu 11 integriran u barem jedan poluvodički element.
15. Opipljivi medij za pohranu podataka koji je moguće računalno čitati i računalnom izvršiti, upute obuhvaćaju: upute koje može izvršiti računalo kako bi se provela metoda sukladno bilo kojem od zahtjeva 1 do 8.
HRP20161195TT 2009-03-02 2016-09-19 Smanjenje efekta opterećenja izvora kod spin prijenosa sile magnetnootporne memorije s nasumičnim pristupom (stt-mram) HRP20161195T1 (hr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/396,295 US8587993B2 (en) 2009-03-02 2009-03-02 Reducing source loading effect in spin torque transfer magnetoresisitive random access memory (STT-MRAM)
PCT/US2010/025834 WO2010101860A2 (en) 2009-03-02 2010-03-02 Reducing source loading effect in spin torque transfer magnetoresitive random access memory (stt-mram)
EP10709600.0A EP2404298B1 (en) 2009-03-02 2010-03-02 Reducing source loading effect in spin torque transfer magnetoresistive random access memory (stt-mram)

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US (4) US8587993B2 (hr)
EP (1) EP2404298B1 (hr)
JP (4) JP5426694B2 (hr)
KR (1) KR101293610B1 (hr)
CN (2) CN104282327B (hr)
BR (1) BRPI1009229A2 (hr)
HR (1) HRP20161195T1 (hr)
SM (1) SMT201600438B (hr)
TW (1) TW201106353A (hr)
WO (1) WO2010101860A2 (hr)

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