ES2499392T3 - Método para apilar circuitos integrados conectados en serie y dispositivo multichip fabricado a partir del mismo - Google Patents

Método para apilar circuitos integrados conectados en serie y dispositivo multichip fabricado a partir del mismo Download PDF

Info

Publication number
ES2499392T3
ES2499392T3 ES08863812.7T ES08863812T ES2499392T3 ES 2499392 T3 ES2499392 T3 ES 2499392T3 ES 08863812 T ES08863812 T ES 08863812T ES 2499392 T3 ES2499392 T3 ES 2499392T3
Authority
ES
Spain
Prior art keywords
chip
terminals
signals
chips
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES08863812.7T
Other languages
English (en)
Spanish (es)
Inventor
Hong Beom Pyeon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/168,354 external-priority patent/US8399973B2/en
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Application granted granted Critical
Publication of ES2499392T3 publication Critical patent/ES2499392T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
ES08863812.7T 2007-12-20 2008-12-18 Método para apilar circuitos integrados conectados en serie y dispositivo multichip fabricado a partir del mismo Active ES2499392T3 (es)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US1534507P 2007-12-20 2007-12-20
US15345 2007-12-20
US3220308P 2008-02-28 2008-02-28
US32203 2008-02-28
US168354 2008-07-07
US12/168,354 US8399973B2 (en) 2007-12-20 2008-07-07 Data storage and stackable configurations
US236874 2008-09-24
US12/236,874 US7791175B2 (en) 2007-12-20 2008-09-24 Method for stacking serially-connected integrated circuits and multi-chip device made from same
PCT/CA2008/002235 WO2009079772A1 (en) 2007-12-20 2008-12-18 Method for stacking serially-connected integrated circuits and multi-chip device made from same

Publications (1)

Publication Number Publication Date
ES2499392T3 true ES2499392T3 (es) 2014-09-29

Family

ID=40800612

Family Applications (1)

Application Number Title Priority Date Filing Date
ES08863812.7T Active ES2499392T3 (es) 2007-12-20 2008-12-18 Método para apilar circuitos integrados conectados en serie y dispositivo multichip fabricado a partir del mismo

Country Status (8)

Country Link
US (3) US7791175B2 (enExample)
EP (1) EP2220681B1 (enExample)
JP (1) JP5633885B2 (enExample)
KR (1) KR20100091164A (enExample)
CN (1) CN101842896B (enExample)
ES (1) ES2499392T3 (enExample)
TW (1) TW200941695A (enExample)
WO (1) WO2009079772A1 (enExample)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005010272A1 (de) * 2005-03-03 2006-09-14 Infineon Technologies Ag Halbleiterbauelement sowie Verfahren zum Herstellen eines Halbleiterbauelements
US7791175B2 (en) * 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
US8399973B2 (en) 2007-12-20 2013-03-19 Mosaid Technologies Incorporated Data storage and stackable configurations
KR100959606B1 (ko) * 2008-03-12 2010-05-27 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
US8174103B2 (en) * 2008-05-01 2012-05-08 International Business Machines Corporation Enhanced architectural interconnect options enabled with flipped die on a multi-chip package
US7741156B2 (en) * 2008-05-27 2010-06-22 Stats Chippac, Ltd. Semiconductor device and method of forming through vias with reflowed conductive material
US7957173B2 (en) 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
KR20100048610A (ko) * 2008-10-31 2010-05-11 삼성전자주식회사 반도체 패키지 및 그 형성 방법
US8674482B2 (en) * 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
US8137995B2 (en) * 2008-12-11 2012-03-20 Stats Chippac, Ltd. Double-sided semiconductor device and method of forming top-side and bottom-side interconnect structures
US8900921B2 (en) * 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
US8082537B1 (en) 2009-01-28 2011-12-20 Xilinx, Inc. Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
US7989959B1 (en) 2009-01-29 2011-08-02 Xilinx, Inc. Method of forming stacked-die integrated circuit
US8987868B1 (en) * 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
JP2011082450A (ja) 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム
US8604593B2 (en) * 2009-10-19 2013-12-10 Mosaid Technologies Incorporated Reconfiguring through silicon vias in stacked multi-die packages
US9219023B2 (en) * 2010-01-19 2015-12-22 Globalfoundries Inc. 3D chip stack having encapsulated chip-in-chip
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
KR101251916B1 (ko) * 2010-08-27 2013-04-08 에스케이하이닉스 주식회사 반도체 집적회로
US8582373B2 (en) 2010-08-31 2013-11-12 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
KR101157032B1 (ko) * 2010-11-17 2012-06-21 에스케이하이닉스 주식회사 반도체 장치
US8618647B2 (en) 2011-08-01 2013-12-31 Tessera, Inc. Packaged microelectronic elements having blind vias for heat dissipation
US9093445B2 (en) 2011-08-26 2015-07-28 International Business Machines Corporation Packaging identical chips in a stacked structure
JP2013077358A (ja) 2011-09-30 2013-04-25 Elpida Memory Inc 半導体装置
JP6053103B2 (ja) * 2012-04-12 2016-12-27 富士電機株式会社 ワイドバンドギャップ半導体装置およびその製造方法
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US8810006B2 (en) * 2012-08-10 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer system and method
US9368489B1 (en) 2013-02-28 2016-06-14 International Business Machines Corporation Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array
US9588937B2 (en) * 2013-02-28 2017-03-07 International Business Machines Corporation Array of processor core circuits with reversible tiers
KR20140112257A (ko) * 2013-03-13 2014-09-23 삼성전자주식회사 반도체 패키지
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
KR20140136201A (ko) * 2013-05-20 2014-11-28 에스케이하이닉스 주식회사 반도체 장치 및 메모리 시스템
US8860229B1 (en) 2013-07-16 2014-10-14 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding with through substrate via (TSV)
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9299640B2 (en) 2013-07-16 2016-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Front-to-back bonding with through-substrate via (TSV)
US9087821B2 (en) 2013-07-16 2015-07-21 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bonding with through substrate via (TSV)
US20150168973A1 (en) * 2013-12-18 2015-06-18 Hashfast LLC Stacked chips powered from shared voltage sources
JP2015176958A (ja) 2014-03-14 2015-10-05 株式会社東芝 半導体装置及びその製造方法
CN104051337B (zh) * 2014-04-24 2017-02-15 上海珏芯光电科技有限公司 立体堆叠集成电路系统芯片封装的制造方法与测试方法
US9859382B2 (en) 2015-12-04 2018-01-02 Globalfoundries Inc. Integrated CMOS wafers
CN107305861B (zh) * 2016-04-25 2019-09-03 晟碟信息科技（上海）有限公司 半导体装置及其制造方法
CN105789918B (zh) * 2016-04-25 2018-03-06 深圳市熙龙玩具有限公司 一种分离电路的元器件堆积式连接实现方法及电路
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US10978426B2 (en) * 2018-12-31 2021-04-13 Micron Technology, Inc. Semiconductor packages with pass-through clock traces and associated systems and methods
CN114334875B (zh) * 2020-09-30 2025-02-18 华为技术有限公司 封装结构及电子器件
JP2023045844A (ja) 2021-09-22 2023-04-03 キオクシア株式会社 半導体デバイス及びメモリシステム
US20240006366A1 (en) * 2022-06-30 2024-01-04 Intel Corporation Microelectronic assemblies including stacked dies coupled by a through dielectric via
CN114967570B (zh) * 2022-07-27 2022-11-11 深圳市汤诚科技有限公司 一种i2c从机地址可编程控制电路结构及控制方法
CN115802602B (zh) * 2023-02-08 2023-09-26 深圳时识科技有限公司 三维堆叠装置及方法、电路板和电子设备

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191405A (en) * 1988-12-23 1993-03-02 Matsushita Electric Industrial Co., Ltd. Three-dimensional stacked lsi
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JPH03291960A (ja) * 1990-04-09 1991-12-24 Hitachi Ltd 半導体装置積層用基板及び積層半導体装置
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
JP3321925B2 (ja) * 1992-09-08 2002-09-09 セイコーエプソン株式会社 液晶表示装置、半導体チップの実装構造、電子光学装置および電子印字装置
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
US5579207A (en) * 1994-10-20 1996-11-26 Hughes Electronics Three-dimensional integrated circuit stacking
CA2196024A1 (en) 1996-02-28 1997-08-28 Craig N. Ernsberger Multilayer electronic assembly utilizing a sinterable composition and related method of forming
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6222276B1 (en) * 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
KR20010104320A (ko) * 1998-12-30 2001-11-24 추후제출 수직 집적 반도체 장치
US6678167B1 (en) * 2000-02-04 2004-01-13 Agere Systems Inc High performance multi-chip IC package
JP4497640B2 (ja) * 2000-03-29 2010-07-07 株式会社日立メディコ 高電圧スイッチ回路及びこれを用いたｘ線装置
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
JP2002359346A (ja) * 2001-05-30 2002-12-13 Sharp Corp 半導体装置および半導体チップの積層方法
JP4917225B2 (ja) * 2001-09-28 2012-04-18 ローム株式会社 半導体装置
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US7081373B2 (en) * 2001-12-14 2006-07-25 Staktek Group, L.P. CSP chip stack with flex circuit
JP2003197854A (ja) * 2001-12-26 2003-07-11 Nec Electronics Corp 両面接続型半導体装置、多段積層型半導体装置、その製造方法および該半導体装置を搭載した電子部品
US6635970B2 (en) * 2002-02-06 2003-10-21 International Business Machines Corporation Power distribution design method for stacked flip-chip packages
KR100486832B1 (ko) * 2002-02-06 2005-05-03 삼성전자주식회사 반도체 칩과 적층 칩 패키지 및 그 제조 방법
TW525273B (en) * 2002-02-07 2003-03-21 Via Tech Inc Elastomer interposer for fixing package onto printed circuit board and fabrication method thereof
TW523890B (en) * 2002-02-07 2003-03-11 Macronix Int Co Ltd Stacked semiconductor packaging device
AU2003298595A1 (en) * 2002-10-08 2004-05-04 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US6876562B2 (en) * 2002-10-17 2005-04-05 Micron Technology, Inc. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
JP3908146B2 (ja) * 2002-10-28 2007-04-25 シャープ株式会社 半導体装置及び積層型半導体装置
TW556961U (en) * 2002-12-31 2003-10-01 Advanced Semiconductor Eng Multi-chip stack flip-chip package
TWI225292B (en) * 2003-04-23 2004-12-11 Advanced Semiconductor Eng Multi-chips stacked package
TWI220781B (en) * 2003-04-28 2004-09-01 Advanced Semiconductor Eng Multi-chip package substrate for flip-chip and wire bonding
TWI225299B (en) * 2003-05-02 2004-12-11 Advanced Semiconductor Eng Stacked flip chip package
US7098541B2 (en) * 2003-05-19 2006-08-29 Hewlett-Packard Development Company, L.P. Interconnect method for directly connected stacked integrated circuits
JP4160447B2 (ja) * 2003-05-28 2008-10-01 シャープ株式会社 電子部品およびモジュールならびにモジュールの組み立て方法、識別方法および環境設定方法
TWI229434B (en) * 2003-08-25 2005-03-11 Advanced Semiconductor Eng Flip chip stacked package
KR100537892B1 (ko) * 2003-08-26 2005-12-21 삼성전자주식회사 칩 스택 패키지와 그 제조 방법
JP4205553B2 (ja) * 2003-11-06 2009-01-07 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
US7173340B2 (en) * 2004-02-25 2007-02-06 Texas Instruments Incorporated Daisy chaining of serial I/O interface on stacking devices
JP4441328B2 (ja) * 2004-05-25 2010-03-31 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP4063796B2 (ja) * 2004-06-30 2008-03-19 日本電気株式会社 積層型半導体装置
JP5354765B2 (ja) * 2004-08-20 2013-11-27 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置の製造方法
JP4622469B2 (ja) * 2004-11-12 2011-02-02 ソニー株式会社 回路基板、回路基板製造方法、及び半導体装置
US7217995B2 (en) * 2004-11-12 2007-05-15 Macronix International Co., Ltd. Apparatus for stacking electrical components using insulated and interconnecting via
JP4354398B2 (ja) * 2004-12-27 2009-10-28 三菱重工業株式会社 半導体装置及びその製造方法
US7271026B2 (en) * 2005-03-14 2007-09-18 Infineon Technologies Ag Method for producing chip stacks and chip stacks formed by integrated devices
US7132754B1 (en) * 2005-03-17 2006-11-07 Alfred E. Mann Foundation For Scientific Research Flip chip stack
US7919844B2 (en) * 2005-05-26 2011-04-05 Aprolase Development Co., Llc Tier structure with tier frame having a feedthrough structure
US7297574B2 (en) * 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
JP4753725B2 (ja) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
KR100743648B1 (ko) * 2006-03-17 2007-07-27 주식회사 하이닉스반도체 웨이퍼 레벨 시스템 인 패키지의 제조방법
DE102006017947B4 (de) * 2006-04-18 2008-02-21 Qimonda Ag Speicherbaustein, entsprechende Baugruppe sowie entsprechendes Herstellungsverfahren
US20080122040A1 (en) * 2006-06-29 2008-05-29 Icemos Technology Corporation Varying Pitch Adapter and a Method of Forming a Varying Pitch Adapter
US7750452B2 (en) * 2007-05-04 2010-07-06 Stats Chippac, Ltd. Same size die stacked package having through-hole vias formed in organic material
US7698470B2 (en) * 2007-08-06 2010-04-13 Qimonda Ag Integrated circuit, chip stack and data processing system
US7791175B2 (en) * 2007-12-20 2010-09-07 Mosaid Technologies Incorporated Method for stacking serially-connected integrated circuits and multi-chip device made from same
TWI389291B (zh) * 2008-05-13 2013-03-11 Ind Tech Res Inst 三維堆疊晶粒封裝結構

Also Published As

Publication number Publication date
CN101842896B (zh) 2013-11-06
US8383514B2 (en) 2013-02-26
US7923370B2 (en) 2011-04-12
CN101842896A (zh) 2010-09-22
JP2011507283A (ja) 2011-03-03
US20110163423A1 (en) 2011-07-07
WO2009079772A1 (en) 2009-07-02
EP2220681A1 (en) 2010-08-25
EP2220681A4 (en) 2011-03-02
US7791175B2 (en) 2010-09-07
WO2009079772A8 (en) 2010-01-14
TW200941695A (en) 2009-10-01
US20090020855A1 (en) 2009-01-22
US20100297812A1 (en) 2010-11-25
KR20100091164A (ko) 2010-08-18
JP5633885B2 (ja) 2014-12-03
EP2220681B1 (en) 2014-06-18

Similar Documents

Publication Publication Date Title
ES2499392T3 (es) Método para apilar circuitos integrados conectados en serie y dispositivo multichip fabricado a partir del mismo
US10643977B2 (en) Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows
US10090280B2 (en) Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
US9502345B2 (en) Ball-grid-array package, electronic system and method of manufacture
US8441111B2 (en) Stub minimization for multi-die wirebond assemblies with parallel windows
US20090321893A1 (en) Multi-die integrated circuit device and method
US9368477B2 (en) Co-support circuit panel and microelectronic packages
US9293444B2 (en) Co-support for XFD packaging
CN104779218B (zh) 芯片封装结构
CN106057748B (zh) 半导体封装