ES2123543T3 - Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados. - Google Patents

Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados.

Info

Publication number
ES2123543T3
ES2123543T3 ES92311252T ES92311252T ES2123543T3 ES 2123543 T3 ES2123543 T3 ES 2123543T3 ES 92311252 T ES92311252 T ES 92311252T ES 92311252 T ES92311252 T ES 92311252T ES 2123543 T3 ES2123543 T3 ES 2123543T3
Authority
ES
Spain
Prior art keywords
self
integrated circuits
manufacturing procedure
contact window
aligning contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92311252T
Other languages
English (en)
Inventor
Kuo-Hua Lee
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2123543T3 publication Critical patent/ES2123543T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

UN CONTACTO AUTOALINEADO AL SUSTRATO (EJ. 1) QUE SE ENCUENTRA EN LA REGION QUE HAY ENTRE DOS ELECTRODOS DE COMPUERTA (EJ. 3) SE FORMA A BASE DE DEPOSITAR UNA CAPA DIELECTRICA CONFORME (EJ. 13) Y DARLE FORMA PARA FORMAR UNA VENTANA DE CONTACTO (EJ. 17). LOS ELEMENTOS CONDUCTORES DEL ELECTRODO DE COMPUERTA (EJ. 3) NO ENTRAN EN CONTACTO DEBIDO A LA DIFERENCIA EN LAS VELOCIDADES DE ATAQUE ENTRE LOS ELEMENTOS DIELECTRICOS CONFORMES (EJ. 13) Y LOS ELEMENTOS AISLANTES (EJ. 11) DE LA ESTRUCTURA DE COMPUERTA (EJ. 3).
ES92311252T 1991-12-30 1992-12-10 Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados. Expired - Lifetime ES2123543T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/815,316 US5880022A (en) 1991-12-30 1991-12-30 Self-aligned contact window

Publications (1)

Publication Number Publication Date
ES2123543T3 true ES2123543T3 (es) 1999-01-16

Family

ID=25217437

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92311252T Expired - Lifetime ES2123543T3 (es) 1991-12-30 1992-12-10 Procedimiento de fabricacion de una ventana de contacto auto-alineable en circuitos integrados.

Country Status (6)

Country Link
US (1) US5880022A (es)
EP (1) EP0550174B1 (es)
JP (1) JPH05259182A (es)
DE (1) DE69227438T2 (es)
ES (1) ES2123543T3 (es)
HK (1) HK1003460A1 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6103612A (en) * 1998-09-02 2000-08-15 Micron Technology, Inc. Isolated interconnect studs and method for forming the same
US6767797B2 (en) 2002-02-01 2004-07-27 Agere Systems Inc. Method of fabricating complementary self-aligned bipolar transistors
JP2004200400A (ja) * 2002-12-18 2004-07-15 Toshiba Corp 半導体装置およびその製造方法
US7169676B1 (en) * 2005-05-23 2007-01-30 Advanced Micro Devices, Inc. Semiconductor devices and methods for forming the same including contacting gate to source

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57130461A (en) * 1981-02-06 1982-08-12 Hitachi Ltd Semiconductor memory storage
JP2681887B2 (ja) * 1987-03-06 1997-11-26 シ−メンス、アクチエンゲゼルシヤフト ３次元１トランジスタメモリセル構造とその製法
US4844776A (en) * 1987-12-04 1989-07-04 American Telephone And Telegraph Company, At&T Bell Laboratories Method for making folded extended window field effect transistor
US4944682A (en) * 1988-10-07 1990-07-31 International Business Machines Corporation Method of forming borderless contacts
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
US4996167A (en) * 1990-06-29 1991-02-26 At&T Bell Laboratories Method of making electrical contacts to gate structures in integrated circuits
US5037777A (en) * 1990-07-02 1991-08-06 Motorola Inc. Method for forming a multi-layer semiconductor device using selective planarization
KR920003461A (ko) * 1990-07-30 1992-02-29 김광호 접촉영역 형성방법 및 그를 이용한 반도체장치의 제조방법
US4997790A (en) * 1990-08-13 1991-03-05 Motorola, Inc. Process for forming a self-aligned contact structure
US5049517A (en) * 1990-11-07 1991-09-17 Micron Technology, Inc. Method for formation of a stacked capacitor
US5114879A (en) * 1990-11-30 1992-05-19 Texas Instruments Incorporated Method of forming a microelectronic contact
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure
DE69222390T2 (de) * 1991-10-31 1998-03-19 Sgs Thomson Microelectronics Herstellungsverfahren eines selbstjustierenden Kontakts
US5200358A (en) * 1991-11-15 1993-04-06 At&T Bell Laboratories Integrated circuit with planar dielectric layer

Also Published As

Publication number Publication date
DE69227438D1 (de) 1998-12-03
EP0550174A2 (en) 1993-07-07
EP0550174B1 (en) 1998-10-28
JPH05259182A (ja) 1993-10-08
DE69227438T2 (de) 1999-05-06
EP0550174A3 (es) 1994-01-12
US5880022A (en) 1999-03-09
HK1003460A1 (en) 1998-10-30

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