ES2110960T3 - Procedimiento de planarizacion de topologias en estructuras de circuitos integrados. - Google Patents

Procedimiento de planarizacion de topologias en estructuras de circuitos integrados.

Info

Publication number
ES2110960T3
ES2110960T3 ES90306496T ES90306496T ES2110960T3 ES 2110960 T3 ES2110960 T3 ES 2110960T3 ES 90306496 T ES90306496 T ES 90306496T ES 90306496 T ES90306496 T ES 90306496T ES 2110960 T3 ES2110960 T3 ES 2110960T3
Authority
ES
Spain
Prior art keywords
integrated circuit
circuit structure
oxide layer
portions
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES90306496T
Other languages
English (en)
Inventor
Steven C Avanzino
Jacob D Haskell
Subhash Gupta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ES2110960T3 publication Critical patent/ES2110960T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/959—Mechanical polishing of wafer

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Amplifiers (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

SE EXPONE UN METODO PARA HACER UNA ESTRUCTURA DE CIRCUITOS INTEGRADOS MUY PLANA QUE TIENE DEPOSITADAS PARTES DE OXIDO PLANAS CON RESPECTO AL NIVEL DE PARTES ADYACENTES DE LA ESTRUCTURA DEL CIRCUITO INTEGRADO, QUE COMPRENDE: DEPOSITAR, SOBRE UNA ESTRUCTURA DE CIRCUITO INTEGRADO QUE TIENE UNAS PRIMERAS PARTES A ALTURA SUPERIOR QUE EL RESTO DE LA ESTRUCTURA DE CIRCUITO INEGRADO, UNA CAPA DE OXIDO CONFORMADO QUE TIENE UN GROSOR QUE EXCEDE LA ALTURA DE LAS CITADAS PRIMERAS PARTES POR ENCIMA DEL RESTO DE LA ESTRUCTURA DEL CIRCUITO INTEGRADO; FORMAR UNA CAPA DE MASCARA CON PATRON SOBRE LA CITADA CAPA DE OXIDO DEPOSITADA CON UNA O MAS APERTURAS EN ESTA A NIVEL CON LAS PRIMERAS PARTES DE ALTURA SUPERIOR DE LA ESTRUCTURA DE CICUITO INTEGRADO; ATACAR QUIMICAMENTE PARTES EXPUESTAS DE LA CITADA CAPA DE OXIDO CONFORMADO A TRAVES DE LOS ORIFICIOS DE LA MASCARA HASTA UN NIVEL APROXIMADAMENTE IGUAL A UN NIVEL DE LA PARTE NO EXPUESTA DE LA CAPA DE OXIDO CONFORMADO ; RETIRAR LA CAPA DE MASCAR; Y PULIMENTAR LACAPA DE OXIDO PARA ELIMINAR LAS PARTES ELEVADAS DE LA CAPA DE OXIDO CONFORMADO QUE SOBRESALGAN DESPUES DE LA OPERACION DE ATAQUE PAR FORMAR UNA ESTRUCTURA MUY PLANA. OPCIONALMENTE, LA CAPA DE OXIDO PUEDE ATACARSE ADEMAS ANISOTROPICAMENTE HASTA QUE SE EXPONGAN LAS SUPERFICIES SUPERIORES DE LA ESTRUCTURA DE CIRCUITO INTEGRADO INFERIOR
ES90306496T 1989-07-03 1990-06-14 Procedimiento de planarizacion de topologias en estructuras de circuitos integrados. Expired - Lifetime ES2110960T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/376,176 US4954459A (en) 1988-05-12 1989-07-03 Method of planarization of topologies in integrated circuit structures

Publications (1)

Publication Number Publication Date
ES2110960T3 true ES2110960T3 (es) 1998-03-01

Family

ID=23484000

Family Applications (1)

Application Number Title Priority Date Filing Date
ES90306496T Expired - Lifetime ES2110960T3 (es) 1989-07-03 1990-06-14 Procedimiento de planarizacion de topologias en estructuras de circuitos integrados.

Country Status (6)

Country Link
US (1) US4954459A (es)
EP (1) EP0407047B9 (es)
JP (1) JPH03116753A (es)
AT (1) ATE161656T1 (es)
DE (1) DE69031849T2 (es)
ES (1) ES2110960T3 (es)

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US5212106A (en) * 1992-05-07 1993-05-18 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
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Also Published As

Publication number Publication date
ATE161656T1 (de) 1998-01-15
DE69031849D1 (de) 1998-02-05
EP0407047A3 (en) 1991-01-30
EP0407047B1 (en) 1997-12-29
EP0407047B9 (en) 2005-11-30
US4954459A (en) 1990-09-04
EP0407047A2 (en) 1991-01-09
DE69031849T2 (de) 1998-07-30
JPH03116753A (ja) 1991-05-17

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