WO1997048132A1 - Method for forming co-planar conductor and insulator features using chemical mechanical planarization - Google Patents

Method for forming co-planar conductor and insulator features using chemical mechanical planarization Download PDF

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Publication number
WO1997048132A1
WO1997048132A1 PCT/US1997/001714 US9701714W WO9748132A1 WO 1997048132 A1 WO1997048132 A1 WO 1997048132A1 US 9701714 W US9701714 W US 9701714W WO 9748132 A1 WO9748132 A1 WO 9748132A1
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WO
WIPO (PCT)
Prior art keywords
layer
metal
oxide
interconnects
dielectπc
Prior art date
Application number
PCT/US1997/001714
Other languages
French (fr)
Inventor
Kashmir S. Sahota
Subramanian Venkatkrishnan
Original Assignee
Advanced Micro Devices, Inc.
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Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1997048132A1 publication Critical patent/WO1997048132A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention relates generally to chemical mechanical polishing or chemical mechanical plananzalion (CMP) More particularly, the present invention relates to polishing adjacent conductor and insu ⁇ lator surfaces such that the conductor and insulator surfaces are level or co-planar
  • CMP is used lo planarize the surfaces of conducting and insulating layers such as metal and oxide which arc supported over a semiconductor wafer
  • the main benefit of performing chemical mechanical polishing is to achieve global as well as local planarity.
  • Local planarity corresponds lo providing plana ⁇ zation over small regions of the wafer surface less lhan about 100 micrometers wide, while global planarity corresponds to providing plana ⁇ zation over one step ⁇ per field or over the entire wafer surface
  • CMP is employed in the formation of multilayer interconnects, i.e., conducting inter ⁇ connects used to form electrical connection to integrated circuit devices formed in a semiconductor wafer.
  • Each level of conducting interconnects is supported over the semiconductor wafer by a layer of dielectric.
  • the semiconductor wafer is coated with the layer of dielectric (e.g., a layer of oxide) and conducting lines (e.g., metal lines) arc laid down on the layer of dielectric.
  • Additional levels of conducting lines i.e., metal lines
  • Contact between each level of metal lines is formed through vias in each of the interlevel dielectric layers.
  • conducting interconnects corresponds to conducting lines, contacts, and/or vias.
  • metal interconnects corresponds to metal lines, contacts, and/or vias
  • Chemical-mechanical polishing is used to planarize the layers of dielectric which isolate the conduct ⁇ ing interconnects. Chemical-mechanical polishing is also employed to form the conducting interconnects using a damascene process, e.g.. damascene metallization.
  • damascene metallization is meant a process in which trenches or contact/via openings arc formed and then filled with metal, followed by polishing to remove any overfilled areas The term is based on a process developed by goldsmiths in ancient Damascus, comp ⁇ sing crafting a pattern or design on a hard surface and then hammenng fine gold wires onto the designed pattern
  • a typical damascene metal process is described in, e g , U S Patent 4,944,836
  • a layer of dielectnc such as a layer of oxide is first deposited Trenches are cut into the oxide using a mask which enables the layer of oxide to be etched to form trenches having a shape and size idenucal to the shape and size of the metal inter ⁇ connects to be formed therein
  • a metal film is deposited thereby filling the trenches with metal
  • the metal film is polished to remove metal outside the trenches and to form a surface on the metal which is planar
  • the metal is polished selecuvely with respect to the surrounding oxide, i e , the metal is polished at a rate that is larger than the rate at which the oxide is polished Accordingly, control is maintained over the thickness of the oxide Ideally, the thickness of the layer of oxide is not reduced or is minimally reduced Since the rate at which the oxide is polished is smaller than the rate at which the metal is polished, the oxide effecUvely serves as a polish stop which assists in and eases the requirements for endpoint
  • an insulator film comp ⁇ sing e g , an addi ⁇ onal layer of oxide
  • an addi ⁇ onal layer of oxide is formed over the metal and oxide in order to electrically isolate the metal interconnects
  • This additional layer of oxide conforms to the shape of the layer of metal thereunder
  • the steps or undula ons in the surface of the metal are typically replicated in the insulator film deposited thereon It is convenuonal, consequently, to polish the addiUonal layer of oxide to produce an insulator film which is planar
  • This insulator film is polished pnor to performing any additional processing steps which are directed to a contact/via mask formation and subsequent etching
  • a method for forming at least one conducUng intercon ⁇ nect embedded in a dielectric which resides over an integrated circuit structure
  • the method comp ⁇ ses the steps of (a) forming a laver of dielect ⁇ c having a surface which is not polished over the integrated circuit structure,
  • the conducung interconnects may be conducung lines, contacts, and/or vias comp ⁇ sing metal or polysilicon
  • metal suitably employed in the method of the present invention include tungsten aluminum, copper, gold, silver, and allovs thereof
  • dielectncs which mav be emploved in the method of the present mvenuon include undoped oxide doped oxide, nit ⁇ dc. and lovv-k dielect ⁇ c
  • a one-step CMP process which polishes both the intercon ⁇ nect matenal and the dielectnc at the same rate both locallv and globalh is emplo ed to simultaneously polish the layer of interconnect matenal and the layer of dielect ⁇ c
  • the one-step CMP process effectively combines two CMP processing steps into one
  • the method of the present invention advantageouslv reduces the cost of anufactu ⁇ ng for processes which require CMP processing such as damascene processing
  • the surface of the conducung interconnects is level or co-planar with the surface of the laver of di ⁇ elect ⁇ c
  • FIGS la-lh are cross-secuonal views of an integrated circuit structure depicting vanous stages of a p ⁇ or art method for forming metal interconnects which employs convenuonal damascene processing.
  • FIGS 2a-2c are cross-sectional views at vanous stages in the processing of an integrated circuit structure in accordance with one embodiment of the present invention.
  • FIGS 3a-3e are cross-sertional views at vanous stages in the processing of an integrated circuit structure in accordance with another embodiment of the present invention
  • the method of the present mvenuon is directed to forming conducting interconnects embedded in a layer of dielect ⁇ c which resides over an integrated circuit structure
  • the conducting interconnects form electri ⁇ cal connecuon to integrated circuit devices formed in the integrated circuit structure (Typically, the integrated circuit devices are formed in a semiconductor wafer from which the integrated circuit structure is built )
  • the conducting interconnects mav comp ⁇ sc conducung lines, contacts, and/or vias (i e . conducung plugs formed in contact and/or via openings)
  • the method of the present mvenuon comp ⁇ ses the steps of
  • the method of the present mvenuon can be repeated to form muluple levels of conducung tntcrcon- nects, each level of conducung interconnects being electrically isolated bv a layer of dielectnc
  • the conducung interconnects comp ⁇ se metal
  • the conducung interconnects may altemauvely comp ⁇ se polysilicon
  • metal suitably emploved in the method of the present mvenuon include tungsten, aluminum, copper, gold, silver, and alloys thereof
  • the layer of dielectnc comp ⁇ ses oxide (undoped oxide such as silicon dioxide), however. the layer of dielect ⁇ c may alternately comp ⁇ se other dielect ⁇ cs
  • dielect ⁇ cs which may be em ⁇ ployed in the method of the present invention include doped oxide (c g , boron silanc-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phosphorous tetra-ethyl orthosilicate), ni- tnde (e g , silicon nit ⁇ de), and lovv-k dielectnc (e g , deposited lovv-k dielectnc or low-k spin-on dielectnc)
  • Bv "low-k dielect ⁇ c" is meant a dielect ⁇ c having a dielect ⁇ c constant, k. that is less than that of silicon dioxide, or less than about 4 0
  • FIGS la-lh wherein like reference numerals designate like elements throughout, a p ⁇ or art process for forming conducung interconnects (I e , metal lines and metal plugs) using conventional damascene processing is shown First, the metal lines which are isolated by a first insulator film are created Then, the metal plugs which are su ⁇ ounded by a second insulator film (1 e , an interlevel dielect ⁇ c layer) are formed In this pnor art process, both the metal lines and the metal plugs are fab ⁇ cated using a damascene metal process
  • FIG la depicts an integrated circuit structure 10 having a first insulator film 12 which is patterned. formed thereon In forming the first insulator film 12. a dielect ⁇ c, e g , oxide, is deposited and trenches 14 are cut therein using a mask (not shown) The first insulator film 12 is etched to create the trenches 14 which have a shape and size idenucal to the shape and size of metal lines 16 (shown in FIG lc) to be formed therein
  • a first metal film 18 (see FIG lb) is deposited on the first insulator film 12 thereby filling the trenches 14 with metal As depicted in FIG lb, the first metal film 18 conforms to the shape of the first msula- tor film 12 Fluctuauons in the surface 20 of the first metal film 18 (such as indicated by arrows 22) exist above the trenches 14 The trenches 14 which are wider produce larger fluctuauons in the surface 20 of the first metal film 18 The first metal film 18 is polished to remove metal outside the trenches 14.
  • polishing the first metal film 18 also forms a surface 24 on some of the metal lines 16 which is planar
  • Conventional metal CMP is used to polish the first metal film 18
  • Commercially available polishing slurnes and a convenuonal CMP polish tool are employed As is convenuonal in the pnor art.
  • the metal com ⁇ p ⁇ sing the first metal film 18 is polished selccuvely with respect to the surrounding oxide comp ⁇ sing the first insulator film 12, that is, the metal is polished at a rate which is larger than the rate at which the oxide is pol ⁇ ished Accordingly, control is maintained over the thickness of the first insulator film 12 Ideally the thickness of the first insulator film 12 is not reduced or is mimmallv reduced Since the rate at which the oxide is pol ⁇ ished is smaller than the rate at which the metal is polished, the first insulator film 12 effecuvelv serves as a polish stop which assists in and eases the requirements for endpoint detecuon the metal in the trenches 14 which are wider is dished out due to polishing Steps or undulauons are thus caused to be formed in the surface 24 of some of the metal lines 16 using the pnor art process Arrow 26 points to the recessed surface 24 of one of the metal lines 16 shown in FIG lc which is caused by dishing
  • a second insulator film 28 (see FIG Id) is then formed over the first insulalor film 12 and the metal lines 16
  • the second insulator film 28 serves as an interlevel dielectnc layer which electrically isolates the metal lines 16
  • This second insulator film 28 conforms to the shape of the first insulator film 12 and the metal lines 16 which reside thereunder
  • the steps or undulauons in the surface 24 of some of the metal lines 16 are typically replicated in the second insulator film 28 deposited thereon
  • the second insulator film 28 is polished pnor to performing anv addiUonal processing steps which arc directed to con- tact a mask formation and subsequent etching
  • the second insulator film 28 is patterned to form opemngs or vias 32 therein
  • a second metal film 34 is deposited over the second insulator film 28 and into the opemngs or vias 32 formed therein, see FIG lg
  • the second metal film 34 is polished to remove a portion of the metal and to expose the second insulator film 28
  • Metal plugs 36 are thereby formed in the opemngs or vias 32 as shown in FIG lh
  • FIGS 2a-2c depict one embodiment of the present mvenuon wherein conducung interconnects 38 comp ⁇ sing metal (shown in FIG 2c) are formed in a laver of dielect ⁇ c 40
  • the conducting interconnects 38 may comp ⁇ sc, for example, conducung lines (metal lines 16) or conducung plugs (metal plugs 36) formed in contact or via opemngs 32
  • FIG 2a depicts an integrated circuit structure 10 having a laver of dielectnc 40 which is patterned formed thereon To form the laver of dielectnc 40, a dielect ⁇ c comp ⁇ sing, e g , oxide, is deposited and open- ings or vias 32 are cut therein using a mask (not shown) The laver of dielectric 40 is etched e g , using reac-
  • the layer of dielect ⁇ c 40 is not pol ⁇ ished
  • the laver of dielectric 40 is instead dircctlv patterned to form opemngs or vias 32 therein
  • the opemngs or vias 32 are patterned in the laver of dielect ⁇ c 40 using a mask (not shown) and an etching process convenuonally emploved for etching the dielectnc. e , oxide While three opemngs or vias 32 are shown, it will be readily apparent to those skilled in the art that in fact anv number of such opemngs or vias can be employed
  • a layer of interconnect matenal (layer of metal) 42 is deposited over the layer of dielect ⁇ c 40 and into the opemngs or vias 32 formed therein as shown in FIG 2b
  • the layer of interconnect matenal or laver of metal 42 may be deposited usmg convenuonal deposiuon techniques such as chemical vapor deposiuon, hot metal deposiuon, physical vapor deposiuon (PVD) sputte ⁇ ng, electroplaUng, or elcctroless depos ons
  • metals suitably employed as the layer of metal 32 include tungsten, aluminum, copper, gold, silver, and alloys thereof Other metals may be suitably employed as the layer of metal 42 as well
  • the layer of metal 42 is polished to remove a portion of the metal and to expose the laver of dielectnc
  • Metal interconnects (conducting interconnects) 38 are therebv formed in the openings or vias 32. see FIG 2c Each of the metal interconnects 38 w hich is formed has a surface 44 that is planar as a result of the chemi ⁇ cal mechanical polishing of the layer of metal 42 While three metal interconnects 38 are shown it will be readily apparent to those skilled in the art that in fact any number of such metal interconnects can be em ⁇ ployed
  • polishing slur ⁇ es and a conventional CMP polish tool can be employed in the method of the present mvenuon It will be appreciated, however, that the method of the present invention does not employ conventional metal CMP which is used in pnor art to form metal interconnects 38 via damascene metal processing With convenuonal metal CMP, polishing stops partly on metal and partly on dielectnc.
  • FIG 2c depicts the laver of dielect ⁇ c 40 having a surface 46 which is planar (It will be appreciated that the rate of polishing of the metal and the dielect ⁇ c is controlled by the rate of polishing of the metal and the dielect ⁇ c is controlled by the rate of polishing of the metal and the dielect ⁇ c is controlled by the rate of polishing of the metal and the dielect ⁇ c is controlled by the rate of polishing of the metal and the dielect ⁇ c is controlled by the
  • the surface 44 of the metal interconnects 38 is level or co-planar with the surface 46 of the laver of dielect ⁇ c 40 In other words, the surface 44 of the metal interconnects 38 is fiush with the surface 46 of the surrounding oxide comp ⁇ sing the layer of dielect ⁇ c 40
  • the one-step CMP process which polishes both metal and dielect ⁇ c at the same rate and thereby si ⁇ multaneously plana ⁇ zes both the metal interconnects 38 and die laver of dielect ⁇ c 40 effecuvely combines two CMP processing steps into one
  • the method of the present invention advantageouslv reduces the cost of manufactu ⁇ g for processes which require CMP processing such as damascene metal processing
  • the conducuve interconnects 38 may alternauvely comp ⁇ se polysili- con
  • the method of the present invenUon may be employed to form conductive interconnects 38 comp ⁇ sing polysilicon embedded in a layer of dielect ⁇ c 40 comp ⁇ sing, e.g , o ide
  • dielect ⁇ cs may be employed in the practice of the present mvenuon
  • dielect ⁇ cs suitably employed as the layer of dielectric 40 include doped o ide (e g , boron silane- based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phosphorous tetra-eth l orthosilicate), nitnde (e g . silicon mt ⁇ de), or lovv-k dielect ⁇ c (c g , deposited lovv-k dielectnc or low-k spin-on dielect ⁇ c)
  • doped o ide e g , boron silane- based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phosphorous tetra-eth l orthosilicate
  • nitnde e g . silicon mt ⁇ de
  • lovv-k dielect ⁇ c
  • the method of the present invention is employed to form conducung interconnects 38 which contact metal lines 16 wherein the metal lines are formed by patterning metal with a mask First, the metal lines 16 which are electncallv isolated by a laver of dielectnc 40 comp ⁇ sing, e g , oxide, are created, then the metal interconnects 38 are formed
  • an integrated circuit structure 10 is depicted having metal lines 16 formed thereon
  • metal is deposited over the integrated circuit structure 10 and subse- quently patterned using a mask (not shown) While five metal lines 16 are shown, it will be readily apparent to those skilled in the art that in fact any number of such metal lines can be employed
  • a layer of oxide (layer of dielect ⁇ c) 40 is formed over the integrated circuit structure 10 and the metal lines 16 as shown in FIG 3b
  • the laver of oxide 40 serves as an interlevel dielect ⁇ c layer which electncallv isolates the metal lines 16
  • This laver of oxide 40 conforms to the shape of the integrated circuit structure 10 and the metal lines 16 formed thereon Fluctuauons in the surface 46 of the layer of oxide 40 (such as indicated by arrows 48) are caused by the non-planar topography produced bv the metal lines 16 formed on the inte ⁇ grated circuit structure 10
  • the laver of oxide 40 is not pol- ished As shown in FIG 3c. the laver of oxide 40 is instead directlv patterned to form opemngs or vias 32 therein
  • the opemngs or vias 32 are patterned in the laver of oxide 40 using a via mask (not shown) and a via etch process convenuonally employed for etching oxide While four opemngs or vias 32 are shown it will be readily apparent to those skilled in the art that in fact anv number of such opemngs or vias can be employed
  • the thickness of the oxide is substanually the same over each of the metal lines 18 Consequently, via etch control is simplified as va ⁇ auon in the thickness of the di ⁇ elect ⁇ c, l e , the oxide, is minimized or eliminated
  • a layer of metal (layer of interconnect matenal) 42 comp ⁇ sing plug metal is deposited over the layer of oxide 40 and into the opemngs or vias 32 formed therein as depicted in FIG 3d
  • the layer of metal 42 av be deposited using convenuonal deposiuon techniques such as chemical vapor deposiuon, hot metal deposiuon.
  • PVD physical vapor deposiuon
  • E.xamples of metals suitably employed as the layer of metal 42 include tungsten, aluminum copper, gold, silver, and allovs thereof
  • Other interconnect mate ⁇ als mav be suitably employed as the laver of interconnect matenal 42 as well (As desc ⁇ bed above, conducting interconnects 38 may alternatively comp ⁇ se polysilicon in which case the laver of interconnect matenal 42 also comp ⁇ ses polysiiicon )
  • the layer of metal 42 is polished to remove a portion of the metal and to expose the layer of o ide 40, see FIG 3e
  • Metal interconnects 38 such as via plugs 16 are thereby formed in the openings or vias 32 in the layer of oxide 40
  • Each of the metal interconnects 38 which is formed has a surface 44 which is planar as a re- suit of the chemical mechamcal polishing of the layer of metal 42 While four metal interconnects 38 are shown, it will be readily apparent to those skilled in the art that in fact any number of such metal interconnects can be employed
  • polishing slur ⁇ es and a convenuonal CMP polish tool can be employed in the method of the present mvenuon It will be appreciated, however, that the method of the present mvenuon does not employ convenuonal metal CMP which is used m pnor art to form metal interconnects 38 via damascene metal processing
  • the metal is polished selecUvely with re ⁇ spect to the surrounding oxide; l e , the metal is polished at a rate that is larger than the rate at which the di ⁇ electnc is polished
  • FIG 3e depicts the surface 46 of the la er of oxide 40 as planar As desc ⁇ bed above, the rate of polishing of the metal and the dielect ⁇ c is controlled by the com- position of the polishing slurry
  • the surface 44 of the metal interconnects is level or co-planar with the surface 46 of the layer of oxide
  • endpoint detccuon may be employed as is conventional to determine when to stop polishing
  • the CMP process could be a umed polish process
  • a umed polish process en ⁇ sures that the surface 44 of the metal interconnects 38 is co-planar with the surface 46 of the la er of oxide 40 because polishing is not stopped au the surface of the metal interconnects and the surface of the layer of ox ⁇ ide are co-planar
  • the method of the present mvenuon will ensure that the surface 44 of the con ⁇ ducting interconnects (metal interconnects) 38 and the surface 46 of the layer of dielect ⁇ c (layer of oxide) 40 are co-planar both locally and globally
  • dielectncs suitably employed as the layer of dielectnc 40 include doped oxide (e g . boron silane-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phospho ⁇ rous tetfa-ethyl orthosilicate), nitnde (e g , silicon nitnde). or low-k dielect ⁇ c (e g , deposited low-k dielect ⁇ c or low-k spin-on dielect ⁇ c)
  • doped oxide e g boron silane-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phospho ⁇ rous tetfa-ethyl orthosilicate
  • nitnde e g , silicon nitnde
  • low-k dielect ⁇ c e g , deposited low-k dielect ⁇ c or low-k spin-on dielect ⁇ c
  • the method of the present invention is applicable to IC technology having feature sizes of 0 5 ⁇ m and smaller
  • the advantages of the method of the present mvenuon include the following First, the thickness of the layer of dielect ⁇ c 40 is substantially the same over each of the metal lines 16 at the stage when the via etch is performed Consequently, via etch control is simplified as va ⁇ ation in the thickness of the layer of dielectnc 40 which is to be etched is minimized
  • the process of the present invenUon simplifies manufactu ⁇ ng and construcUon of conducung interconnects 38 and makes the via etch process easy, thereby lowe ⁇ ng cost and improving efficiency
  • the throughput of the process of the present mvenuon is high in compa ⁇ son with pnor art damascene processes since one less CMP process is employed Consequently, the process of the present invenUon is more economical than pnor art damascene processes
  • the method of the present mvenuon desenbed above can be repeated to build mululayer ter- connects comp ⁇ sing addiUonal levels of conducting interconnects 38 electncally isolated by layers of dielectnc 40 which serve as interlevel dielect ⁇ c layers
  • the method of the present invention is expected to find use in the fabncation of deep sub-micrometer

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Abstract

A method is provided for forming conducting interconnects embedded in a layer of dielectric (38) such as an interlevel dielectric layer which resides over an integrated circuit structure (10). The conducting interconnects (38) and the layer of dielectric (40) may comprise, for example, metal and oxide, respectively. A CMP process which polishes both the interconnect material (i.e., the metal) and the dielectric (i.e., the oxide) at the same rate both locally and globally is employed to simultaneously polish the conducting interconnects (38) and the layer of dielectric (40). The CMP process effectively combines two CMP processing steps into one. Thus, the method of the present invention advantageously reduces the cost of manufacturing. Additionally, since both the layer of dielectric (40) and the conducting interconnects (38) are planarized in a single polishing step which polishes the interconnect material and the dielectric (e.g., metal and oxide) at rates which are essentially the same, the surface of the conducting interconnects (44) is level or co-planar with the surface of the layer of dielectric (46). The method of the present invention can be repeated to build multiple levels of conducting interconnects (38).

Description

METHOD FOR FORMING CO-PLANAR CONDUCTOR AND INSULATOR FEATURES USING CHEMICAL MECHANICAL PLANARIZATION
TECHNICAL FIELD
The present invention relates generally to chemical mechanical polishing or chemical mechanical plananzalion (CMP) More particularly, the present invention relates to polishing adjacent conductor and insu¬ lator surfaces such that the conductor and insulator surfaces are level or co-planar
BACKGROUND ART
Chemical mechanical polishing is widely accepted for polishing semiconductor wafers. In particular,
CMP is used lo planarize the surfaces of conducting and insulating layers such as metal and oxide which arc supported over a semiconductor wafer
The main benefit of performing chemical mechanical polishing is to achieve global as well as local planarity. Local planarity corresponds lo providing planaπzation over small regions of the wafer surface less lhan about 100 micrometers wide, while global planarity corresponds to providing planaπzation over one step¬ per field or over the entire wafer surface
In particular, CMP is employed in the formation of multilayer interconnects, i.e., conducting inter¬ connects used to form electrical connection to integrated circuit devices formed in a semiconductor wafer. Each level of conducting interconnects is supported over the semiconductor wafer by a layer of dielectric. Generally, the semiconductor wafer is coated with the layer of dielectric (e.g., a layer of oxide) and conducting lines (e.g., metal lines) arc laid down on the layer of dielectric. Additional levels of conducting lines (i.e., metal lines) are formed over this layer of dielectric, each separated by an additional layer of dielectric, i.e.. an interlevel dielec¬ tric layer. Contact between each level of metal lines is formed through vias in each of the interlevel dielectric layers. (As used herein, the term conducting interconnects corresponds to conducting lines, contacts, and/or vias. Accordingly, the term metal interconnects corresponds to metal lines, contacts, and/or vias )
Chemical-mechanical polishing is used to planarize the layers of dielectric which isolate the conduct¬ ing interconnects. Chemical-mechanical polishing is also employed to form the conducting interconnects using a damascene process, e.g.. damascene metallization. (By "damascene metallization" is meant a process in which trenches or contact/via openings arc formed and then filled with metal, followed by polishing to remove any overfilled areas The term is based on a process developed by goldsmiths in ancient Damascus, compπsing crafting a pattern or design on a hard surface and then hammenng fine gold wires onto the designed pattern ) A typical damascene metal process is described in, e g , U S Patent 4,944,836
To form a single level of metal interconnects using damascene metallization, a layer of dielectnc such as a layer of oxide is first deposited Trenches are cut into the oxide using a mask which enables the layer of oxide to be etched to form trenches having a shape and size idenucal to the shape and size of the metal inter¬ connects to be formed therein A metal film is deposited thereby filling the trenches with metal The metal film is polished to remove metal outside the trenches and to form a surface on the metal which is planar The metal is polished selecuvely with respect to the surrounding oxide, i e , the metal is polished at a rate that is larger than the rate at which the oxide is polished Accordingly, control is maintained over the thickness of the oxide Ideally, the thickness of the layer of oxide is not reduced or is minimally reduced Since the rate at which the oxide is polished is smaller than the rate at which the metal is polished, the oxide effecUvely serves as a polish stop which assists in and eases the requirements for endpoint detection
Figure imgf000004_0001
the metal in the trenches which are wider is dished out due to polishing (Metal dishing results from the relative softness of the metal in compaπson to the rclativelv hard oxide as well as from the physical nature of the polishing pad employed in polishing ) Dishing is characteπzed bv the recessed sur¬ face of the metal and thus causes steps or undulations to be formed in the surface of the metal
Next, an insulator film compπsing, e g , an addiϋonal layer of oxide, is formed over the metal and oxide in order to electrically isolate the metal interconnects This additional layer of oxide conforms to the shape of the layer of metal thereunder Thus, the steps or undula ons in the surface of the metal are typically replicated in the insulator film deposited thereon It is convenuonal, consequently, to polish the addiUonal layer of oxide to produce an insulator film which is planar This insulator film is polished pnor to performing any additional processing steps which are directed to a contact/via mask formation and subsequent etching
An alternaύve method for planaπzmg a laver of oxide is outlined in U S Patent 4 954.459 The method descπbed therein involves oxide deposiUon followed by masking wherein openings in the mask are in registry with raised portions of the oxide Wet etching is employed to etch the raised portions of the oxide down to approximately the same height as the low portions of the oxide The mask is stripped and polishing is used to remove any remaining raised portions of the oxide This process for planaπzing a layer of oxide, how¬ ever, involves addiUonal masking and etching in addiuon to polishing, and thus, increases process complexity What is needed is a method for forming metal interconnects surrounded by oxide which is simpler and does not require additional polishing steps directed to pianaπzing the oxide
DISCLOSURE OF INVENTION
In accordance with the mvenuon. a method is provided for forming at least one conducUng intercon¬ nect embedded in a dielectric which resides over an integrated circuit structure The method compπses the steps of (a) forming a laver of dielectπc having a surface which is not polished over the integrated circuit structure,
(b) patterning the laver of dielectπc thereby forming openings therein,
(c) deposiUng a layer of interconnect matenal filling the openings, (d) polishing the laver of interconnect matenal using chemical mechanical polishing to re¬ move a portion thereof such that the surface of the laver of dielectnc is exposed and conducting interconnects each having a surface are thereby formed, and
(e) conUnuing polishing to planaπze the layer of dielectπc and the conducung interconnects, both the layer of interconnect material and Ihe laver of dielectπc being polished at rates which are essenUallv the same such that the surface of the laver of dielectπc which is exposed is level with the surface of the con¬ ducung interconnects
The conducung interconnects may be conducung lines, contacts, and/or vias compπsing metal or polysilicon Examples of metal suitably employed in the method of the present invention include tungsten aluminum, copper, gold, silver, and allovs thereof Examples of dielectncs which mav be emploved in the method of the present mvenuon include undoped oxide doped oxide, nitπdc. and lovv-k dielectπc
It will be appreciated that the above steps can be repeated to build multiple levels of conducung inter¬ connects
With the method of the present invention, a one-step CMP process which polishes both the intercon¬ nect matenal and the dielectnc at the same rate both locallv and globalh is emplo ed to simultaneously polish the layer of interconnect matenal and the layer of dielectπc The one-step CMP process effectively combines two CMP processing steps into one Thus, the method of the present invention advantageouslv reduces the cost of anufactuπng for processes which require CMP processing such as damascene processing
Addiuonally, since both the laver of dielectnc and the conducung interconnects are pianaπzed in a single polishing step which polishes the dielectnc and the interconnect matenal at rates which are essenUallv the same, the surface of the conducung interconnects is level or co-planar with the surface of the laver of di¬ electπc
Other objects, features, and advantages of the present mvenuon will become apparent upon consid- craϋon of the following detailed descπpuon and accompanying drawings, in which like reference designauons represent like features throughout the Figures
BRIEF DESCRIPTION OF THE DRAWINGS
The drawings referred to in this desenpuon should be understood as not being drawn to scale except if specifically noted Moreover, the drawings are intended to illustrate only one portion of an integrated circuit fabπcated in accordance with the present invention
FIGS la-lh are cross-secuonal views of an integrated circuit structure depicting vanous stages of a pπor art method for forming metal interconnects which employs convenuonal damascene processing. FIGS 2a-2c are cross-sectional views at vanous stages in the processing of an integrated circuit structure in accordance with one embodiment of the present invention, and
FIGS 3a-3e are cross-sertional views at vanous stages in the processing of an integrated circuit structure in accordance with another embodiment of the present invention
BEST MODES FOR CARRYING OUT THE INVENTION
Reference is now made in detail to a specific embodiment of the present mvenuon, which illustrates the best mode presently contemplated by the inventors for pracucing the invention Altemauve embodiments are also bnefly descπbed as applicable
The method of the present mvenuon is directed to forming conducting interconnects embedded in a layer of dielectπc which resides over an integrated circuit structure The conducting interconnects form electri¬ cal connecuon to integrated circuit devices formed in the integrated circuit structure (Typically, the integrated circuit devices are formed in a semiconductor wafer from which the integrated circuit structure is built ) In accordance with the present inv ention, the conducting interconnects mav compπsc conducung lines, contacts, and/or vias (i e . conducung plugs formed in contact and/or via openings) The method of the present mvenuon compπses the steps of
(a) forming a laver of dielectπc having a surface which is not polished ov er the integrated circuit structure, (b) patterning the laver of dielectπc thereby forming openings therein
(c) depositing a laver of interconnect matenal filling the openings,
(d) polishing the laver of interconnect matenal using chemical mechanical polishing to re¬ move a portion thereof such that the surface of the laver of dielectπc is exposed and conducting interconnects each having a surface are thereby formed, and (e) conUnuing polishing to plananzc the laver of dielectnc and the conducting interconnects, both the layer of interconnect matenal and the laver of dielectnc being polished at rates which are essentiallv the same such that the surface of the laver of dielectπc which is exposed is level with the surface of the con¬ ducung interconnects
The method of the present mvenuon can be repeated to form muluple levels of conducung tntcrcon- nects, each level of conducung interconnects being electrically isolated bv a layer of dielectnc
Preferably, the conducung interconnects compπse metal, however, the conducung interconnects may altemauvely compπse polysilicon Examples of metal suitably emploved in the method of the present mvenuon include tungsten, aluminum, copper, gold, silver, and alloys thereof
Preferably, the layer of dielectnc compπses oxide (undoped oxide such as silicon dioxide), however. the layer of dielectπc may alternately compπse other dielectπcs Examples of dielectπcs which may be em¬ ployed in the method of the present invention include doped oxide (c g , boron silanc-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phosphorous tetra-ethyl orthosilicate), ni- tnde (e g , silicon nitπde), and lovv-k dielectnc (e g , deposited lovv-k dielectnc or low-k spin-on dielectnc) Bv "low-k dielectπc" is meant a dielectπc having a dielectπc constant, k. that is less than that of silicon dioxide, or less than about 4 0
Referπng now to FIGS la-lh, wherein like reference numerals designate like elements throughout, a pπor art process for forming conducung interconnects (I e , metal lines and metal plugs) using conventional damascene processing is shown First, the metal lines which are isolated by a first insulator film are created Then, the metal plugs which are suπounded by a second insulator film (1 e , an interlevel dielectπc layer) are formed In this pnor art process, both the metal lines and the metal plugs are fabπcated using a damascene metal process
FIG la depicts an integrated circuit structure 10 having a first insulator film 12 which is patterned. formed thereon In forming the first insulator film 12. a dielectπc, e g , oxide, is deposited and trenches 14 are cut therein using a mask (not shown) The first insulator film 12 is etched to create the trenches 14 which have a shape and size idenucal to the shape and size of metal lines 16 (shown in FIG lc) to be formed therein
A first metal film 18 (see FIG lb) is deposited on the first insulator film 12 thereby filling the trenches 14 with metal As depicted in FIG lb, the first metal film 18 conforms to the shape of the first msula- tor film 12 Fluctuauons in the surface 20 of the first metal film 18 (such as indicated by arrows 22) exist above the trenches 14 The trenches 14 which are wider produce larger fluctuauons in the surface 20 of the first metal film 18 The first metal film 18 is polished to remove metal outside the trenches 14. therebv forming metal lines 16 as shown in FIG lc Polishing the first metal film 18 also forms a surface 24 on some of the metal lines 16 which is planar Conventional metal CMP is used to polish the first metal film 18 Commercially available polishing slurnes and a convenuonal CMP polish tool are employed As is convenuonal in the pnor art. the metal com¬ pπsing the first metal film 18 is polished selccuvely with respect to the surrounding oxide compπsing the first insulator film 12, that is, the metal is polished at a rate which is larger than the rate at which the oxide is pol¬ ished Accordingly, control is maintained over the thickness of the first insulator film 12 Ideally the thickness of the first insulator film 12 is not reduced or is mimmallv reduced Since the rate at which the oxide is pol¬ ished is smaller than the rate at which the metal is polished, the first insulator film 12 effecuvelv serves as a polish stop which assists in and eases the requirements for endpoint detecuon
Figure imgf000007_0001
the metal in the trenches 14 which are wider is dished out due to polishing Steps or undulauons are thus caused to be formed in the surface 24 of some of the metal lines 16 using the pnor art process Arrow 26 points to the recessed surface 24 of one of the metal lines 16 shown in FIG lc which is caused by dishing
A second insulator film 28 (see FIG Id) is then formed over the first insulalor film 12 and the metal lines 16 The second insulator film 28 serves as an interlevel dielectnc layer which electrically isolates the metal lines 16 This second insulator film 28 conforms to the shape of the first insulator film 12 and the metal lines 16 which reside thereunder Thus, the steps or undulauons in the surface 24 of some of the metal lines 16 are typically replicated in the second insulator film 28 deposited thereon
Consequently, it is con enuonal in the pnor art to polish the second insulator film 28 to planaπzc the surface 30 of the second insulator film (It will be appreciated that with the method of the present invention. this polishing step is not required ) In the case where the second insulator film 28 compπses oxide, oxide CMP (which stops on oxide) is typically employed With oxide CMP, oxide on the surface 30 is removed, producing a planar second insulator film 28 above the metal lines 16 as shown in FIG lc Accordingly, metal deposited on the surface 30 of the second insulator film 28, will also be have a planar surface Convenuonally, the second insulator film 28 is polished pnor to performing anv addiUonal processing steps which arc directed to con- tact a mask formation and subsequent etching
As depicted in FIG If, the second insulator film 28 is patterned to form opemngs or vias 32 therein A second metal film 34 is deposited over the second insulator film 28 and into the opemngs or vias 32 formed therein, see FIG lg The second metal film 34 is polished to remove a portion of the metal and to expose the second insulator film 28 Metal plugs 36 are thereby formed in the opemngs or vias 32 as shown in FIG lh
As descnbe above, with the pnor art process shown in FIGS la-lh, the metal in the trenches 14 which are wider (such as indicated bv arrow 26 in FIG lc) is dished out due to polishing With the process of the present mvenuon, however, such metal dishing is minimized
FIGS 2a-2c depict one embodiment of the present mvenuon wherein conducung interconnects 38 compπsing metal (shown in FIG 2c) are formed in a laver of dielectπc 40 The conducting interconnects 38 may compπsc, for example, conducung lines (metal lines 16) or conducung plugs (metal plugs 36) formed in contact or via opemngs 32
FIG 2a depicts an integrated circuit structure 10 having a laver of dielectnc 40 which is patterned formed thereon To form the laver of dielectnc 40, a dielectπc compπsing, e g , oxide, is deposited and open- ings or vias 32 are cut therein using a mask (not shown) The laver of dielectric 40 is etched e g , using reac-
Uve ion etching RIE) to create the opemngs or vias 32 which hav e a shape and size idenϋcal to the shape and size of conducung interconnects 38 to be formed therein
In accordance with the method of the present mvenuon. however, the layer of dielectπc 40 is not pol¬ ished As depicted in FIG 2a, the laver of dielectric 40 is instead dircctlv patterned to form opemngs or vias 32 therein The opemngs or vias 32 are patterned in the laver of dielectπc 40 using a mask (not shown) and an etching process convenuonally emploved for etching the dielectnc. e , oxide While three opemngs or vias 32 are shown, it will be readily apparent to those skilled in the art that in fact anv number of such opemngs or vias can be employed
A layer of interconnect matenal (layer of metal) 42 is deposited over the layer of dielectπc 40 and into the opemngs or vias 32 formed therein as shown in FIG 2b The layer of interconnect matenal or laver of metal 42 may be deposited usmg convenuonal deposiuon techniques such as chemical vapor deposiuon, hot metal deposiuon, physical vapor deposiuon (PVD) sputteπng, electroplaUng, or elcctroless depos ons Ex¬ amples of metals suitably employed as the layer of metal 32 include tungsten, aluminum, copper, gold, silver, and alloys thereof Other metals may be suitably employed as the layer of metal 42 as well The layer of metal 42 is polished to remove a portion of the metal and to expose the laver of dielectnc
40 Metal interconnects (conducting interconnects) 38 are therebv formed in the openings or vias 32. see FIG 2c Each of the metal interconnects 38 w hich is formed has a surface 44 that is planar as a result of the chemi¬ cal mechanical polishing of the layer of metal 42 While three metal interconnects 38 are shown it will be readily apparent to those skilled in the art that in fact any number of such metal interconnects can be em¬ ployed
Commercially available polishing slurπes and a conventional CMP polish tool can be employed in the method of the present mvenuon It will be appreciated, however, that the method of the present invention does not employ conventional metal CMP which is used in pnor art to form metal interconnects 38 via damascene metal processing With convenuonal metal CMP, polishing stops partly on metal and partly on dielectnc. e g , o ide As descπbed above, with metal CMP shown in pnor art, the metal is polished selectively with respect to the surrounding dielectnc, I e , the metal is polished at a rate that is larger than the rate at which the dielectπc matenal is polished In contrast, with the method of the present invenUon, a one-step CMP process which polishes both metal and dielectπc (e g , oxide) at the same rate both locally and globally is employed to simultaneously pol¬ ish the layer of metal 42 and the layer of dielectnc 40 Thus, the layer of dielectnc 40 which is exposed is pol¬ ished as well in this single polishing step This single polishing step plaπaπzcs both the metal interconnects 38 and the layer of dielectπc 40 Accordingly, FIG 2c depicts the laver of dielectπc 40 having a surface 46 which is planar (It will be appreciated that the rate of polishing of the metal and the dielectπc is controlled by the composiuon of the polishing slurry )
Since both the layer of dielectπc 40 and the metal interconnects 38 are planaπzed in a single polish¬ ing step which polishes the metal and dielectπc at rates which are essenually the same, the surface 44 of the metal interconnects 38 is level or co-planar with the surface 46 of the laver of dielectπc 40 In other words, the surface 44 of the metal interconnects 38 is fiush with the surface 46 of the surrounding oxide compπsing the layer of dielectπc 40
The one-step CMP process which polishes both metal and dielectπc at the same rate and thereby si¬ multaneously planaπzes both the metal interconnects 38 and die laver of dielectπc 40 effecuvely combines two CMP processing steps into one Thus, the method of the present invention advantageouslv reduces the cost of manufactuππg for processes which require CMP processing such as damascene metal processing
It will be appreciated that the method of the present mvenuon desenbed above can be repeated to build mululayer interconnects compπsing addiUonal levels of metal interconnects 38 elcctncally isolated by layers of dielectπc 40 which serve as interlevel dielectnc layers
It will further be appreciated that the conducuve interconnects 38 may alternauvely compπse polysili- con For example, the method of the present invenUon may be employed to form conductive interconnects 38 compπsing polysilicon embedded in a layer of dielectπc 40 compπsing, e.g , o ide
Addiuonally, outer suitable dielectπcs may be employed in the practice of the present mvenuon Ex¬ amples of dielectπcs suitably employed as the layer of dielectric 40 include doped o ide (e g , boron silane- based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phosphorous tetra-eth l orthosilicate), nitnde (e g . silicon mtπde), or lovv-k dielectπc (c g , deposited lovv-k dielectnc or low-k spin-on dielectπc)
In an altemauve embodiment, the method of the present invention is employed to form conducung interconnects 38 which contact metal lines 16 wherein the metal lines are formed by patterning metal with a mask First, the metal lines 16 which are electncallv isolated by a laver of dielectnc 40 compπsing, e g , oxide, are created, then the metal interconnects 38 are formed
Refemng now to FIG 3a, an integrated circuit structure 10 is depicted having metal lines 16 formed thereon To form the metal lines 16, metal is deposited over the integrated circuit structure 10 and subse- quently patterned using a mask (not shown) While five metal lines 16 are shown, it will be readily apparent to those skilled in the art that in fact any number of such metal lines can be employed
A layer of oxide (layer of dielectπc) 40 is formed over the integrated circuit structure 10 and the metal lines 16 as shown in FIG 3b The laver of oxide 40 serves as an interlevel dielectπc layer which electncallv isolates the metal lines 16 This laver of oxide 40 conforms to the shape of the integrated circuit structure 10 and the metal lines 16 formed thereon Fluctuauons in the surface 46 of the layer of oxide 40 (such as indicated by arrows 48) are caused by the non-planar topography produced bv the metal lines 16 formed on the inte¬ grated circuit structure 10
It is conventional in the pnor art to polish the laver of oxide 40 using an oxide CMP process to pla- nanze the surface 46 of the laver of dielectπc With oxide CMP, oxide on the surface 46 is removed producing a planar laver of oxide 40 above the metal lines 16 Polishing the laver of oxide 40 at th s stage, as is conven¬ tional, ensures that the surface 48 of the laver of dielectnc 40 is planar both locallv and globally Convenuon¬ ally, the layer of oxide 40 is polished pnor to performing the addiUonal processing steps which are directed to a contact/via mask formation and subsequent etching With pnor an approaches vias 32 are formed in the layer of oxide 40 using a via mask and etch process Metal plugs 36 are formed in the vias 32 by deposiung metal on the layer of oxide 40 and into the openings or vias 32 The metal is subsequently polished using metal CMP lo form the metal plugs 36 With the pnor art approach the metal is polished selectively with respect to the surrounding oxide, that is, the metal is polished at a rate which is larger than the rate at which the dielec¬ tπc is polished
In accordance with the mediod of the present invention however the laver of oxide 40 is not pol- ished As shown in FIG 3c. the laver of oxide 40 is instead directlv patterned to form opemngs or vias 32 therein The opemngs or vias 32 are patterned in the laver of oxide 40 using a via mask (not shown) and a via etch process convenuonally employed for etching oxide While four opemngs or vias 32 are shown it will be readily apparent to those skilled in the art that in fact anv number of such opemngs or vias can be employed
Since the layer of oxide 40 is not polished, the thickness of the oxide is substanually the same over each of the metal lines 18 Consequently, via etch control is simplified as vaπauon in the thickness of the di¬ electπc, l e , the oxide, is minimized or eliminated
A layer of metal (layer of interconnect matenal) 42 compπsing plug metal is deposited over the layer of oxide 40 and into the opemngs or vias 32 formed therein as depicted in FIG 3d The layer of metal 42 av be deposited using convenuonal deposiuon techniques such as chemical vapor deposiuon, hot metal deposiuon. physical vapor deposiuon (PVD) spuitenng, electroplating, or elcctroless deposiuons E.xamples of metals suitably employed as the layer of metal 42 include tungsten, aluminum copper, gold, silver, and allovs thereof Other interconnect mateπals mav be suitably employed as the laver of interconnect matenal 42 as well (As descπbed above, conducting interconnects 38 may alternatively compπse polysilicon in which case the laver of interconnect matenal 42 also compπses polysiiicon )
The layer of metal 42 is polished to remove a portion of the metal and to expose the layer of o ide 40, see FIG 3e Metal interconnects 38 such as via plugs 16 are thereby formed in the openings or vias 32 in the layer of oxide 40 Each of the metal interconnects 38 which is formed has a surface 44 which is planar as a re- suit of the chemical mechamcal polishing of the layer of metal 42 While four metal interconnects 38 are shown, it will be readily apparent to those skilled in the art that in fact any number of such metal interconnects can be employed
Commercially available polishing slurπes and a convenuonal CMP polish tool can be employed in the method of the present mvenuon It will be appreciated, however, that the method of the present mvenuon does not employ convenuonal metal CMP which is used m pnor art to form metal interconnects 38 via damascene metal processing As descπbed above, with convenuonal metal CMP, the metal is polished selecUvely with re¬ spect to the surrounding oxide; l e , the metal is polished at a rate that is larger than the rate at which the di¬ electnc is polished
In conuast. with the mediod of the present mvenuon. a one-step CMP process which polishes both metal and dielectπc (oxide) at the same rate both locally and globally is employed to simultaneously polish the layer of metal 42 and the layer of oxide 40 Thus, the layer of oxide 40 which is exposed is polished as well in this single polishing step This single polishing step planaπzes both the surface 44 of the metal interconnects 38 and the surface 46 of the layer of oxide 40 Accordingly, FIG 3e depicts the surface 46 of the la er of oxide 40 as planar As descπbed above, the rate of polishing of the metal and the dielectπc is controlled by the com- position of the polishing slurry
Since both the metal interconnects 38 and the layer of dielectπc 40 are planaπzed in a single polish¬ ing step which polishes the metal and the dielectnc at rates which are essenUallv the same, the surface 44 of the metal interconnects is level or co-planar with the surface 46 of the layer of oxide
It will be appreciated that endpoint detccuon may be employed as is conventional to determine when to stop polishing Alternately, the CMP process could be a umed polish process A umed polish process en¬ sures that the surface 44 of the metal interconnects 38 is co-planar with the surface 46 of the la er of oxide 40 because polishing is not stopped unul the surface of the metal interconnects and the surface of the layer of ox¬ ide are co-planar In either case, the method of the present mvenuon will ensure that the surface 44 of the con¬ ducting interconnects (metal interconnects) 38 and the surface 46 of the layer of dielectπc (layer of oxide) 40 are co-planar both locally and globally
As descπbed above, other suitable dielectπcs may be employed in the practice of the present inven¬ Uon E.xamples of dielectncs suitably employed as the layer of dielectnc 40 include doped oxide (e g . boron silane-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phospho¬ rous tetfa-ethyl orthosilicate), nitnde (e g , silicon nitnde). or low-k dielectπc (e g , deposited low-k dielectπc or low-k spin-on dielectπc)
The method of the present invention is applicable to IC technology having feature sizes of 0 5 μm and smaller
The advantages of the method of the present mvenuon include the following First, the thickness of the layer of dielectπc 40 is substantially the same over each of the metal lines 16 at the stage when the via etch is performed Consequently, via etch control is simplified as vaπation in the thickness of the layer of dielectnc 40 which is to be etched is minimized
Second, the process of the present invenUon simplifies manufactuπng and construcUon of conducung interconnects 38 and makes the via etch process easy, thereby loweπng cost and improving efficiency Addi¬ tionally, the throughput of the process of the present mvenuon is high in compaπson with pnor art damascene processes since one less CMP process is employed Consequently, the process of the present invenUon is more economical than pnor art damascene processes
Third, the method of the present mvenuon desenbed above can be repeated to build mululayer ter- connects compπsing addiUonal levels of conducting interconnects 38 electncally isolated by layers of dielectnc 40 which serve as interlevel dielectπc layers
INDUSTRIAL APPLICABILITY
The method of the present invention is expected to find use in the fabncation of deep sub-micrometer
IC technology
The foregoing desenpuon of the preferred embodiment of the present mvenuon has been presented for purposes of lllustraUon and desenpuon It is not intended to be exhausuve or to limit the mvenuon to the pre- cise form disclosed Obviously, many modifications and vaπations will be apparent to practiuoners skilled in this art Many vaπauons of films and matenals are possible It is possible that the mvenuon may be pracUced in other fabπcauon technologies in MOS or bipolar processes Similarly, any process steps desenbed might be inter¬ changeable with other steps in order to achieve the same result The embodiment was chosen and descπbed in order to best explain the pπnciples of the mvenuon and its practical apphcauon. thereby enabling others skilled in the art to understand the mvenuon for vanous embodiments and with vanous modtficauons as arc suited to the particular use contemplated It is intended that the scope of the mvenuon be defined bv the claims appended hereto and their equivalents

Claims

What Is Claimed Is
1 A method of forming at least one conducung interconnect (38) embedded in a dielectπc formed over an integrated circuit structure (10), said method compπsing the steps of
(a) forming a layer of dielectnc (40) having a surface (46) which is not polished over said integrated circuit structure (10),
(b) patterning said layer of dielectnc (40) thereby forming opemngs (32) therein, (c) deposiung a layer of interconnect matenal (42) filling said opemngs (32),
(d) polishing said layer of interconnect matenal (42) using chemical mechamcal polishing to remove a portion thereof such that said surface of said laver of dielectnc (46) is exposed and conducung inter¬ connects (38) each having a surface (44) are thereby formed, and
(e) conunuing polishing to planaπze said laver of dielectπc (40) and said conducung inter- connects (38), both said laver of interconnect matenal (42) and said laver of dielectπc (40) being polished at rates which are essenually die same such that said surface of said layer of dielectπc (46) which is exposed is level with said surface of said conducung interconnects (44)
2 The method of Claim 1 wherein said conducting interconnects (38) are selected from the group consisting of conducung lines, contacts, and vias
3 The method of Claim 1 wherein said conducung interconnects (38) compπse matenal selected from the group consisung of metal and polysilicon
4 The method of Claim 3 herein said metal is selected from the group consisting of tungsten, alu¬ minum, copper, gold, silver, and alloys thereof
5 The method of Claim 1 wherein said layer of dielectnc (40) compnses dielectnc matenal selected from the group consisung of oxide, mtπde, and low-k dielectnc
6 The method of Claim 5 wherein said layer of dielectnc (40) compπses dielectric matenal selected from the group consisung of silicon dioxide and silicon nitnde
7 The method of Claim 5 wherein said layer of dielectπc (40) compπses doped oxide
8 The method of Claim 7 wherein said doped oxide is selected from the group consisung of boron silane-based glass, phosphorous silane-based glass, boron phosphorous silane-based glass, and boron phospho¬ rous tetra-ethyl orthosilicate 9 The method of Claim 1 wherein said layer of interconnect matenal (42) is formed by a deposition process selected from the group consisung of chemical vapor deposition, hot metal deposition, physical vapor deposition (PVD) spuitenng, electroplaung, and electroless deposition
10 The method of Claim 1 wherein said steps (a) through (e) are repeated to form mulUple layers of conducung interconnects (38)
PCT/US1997/001714 1996-06-11 1997-02-11 Method for forming co-planar conductor and insulator features using chemical mechanical planarization WO1997048132A1 (en)

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Citations (3)

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