EP3109895A3 - Halbleiterbauelement mit dotierter epitaktischer region und dessen verfahren zur herstellung - Google Patents

Halbleiterbauelement mit dotierter epitaktischer region und dessen verfahren zur herstellung Download PDF

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Publication number
EP3109895A3
EP3109895A3 EP16177334.6A EP16177334A EP3109895A3 EP 3109895 A3 EP3109895 A3 EP 3109895A3 EP 16177334 A EP16177334 A EP 16177334A EP 3109895 A3 EP3109895 A3 EP 3109895A3
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EP
European Patent Office
Prior art keywords
epitaxial region
semiconductor device
epitaxial
region
fabrication
Prior art date
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Granted
Application number
EP16177334.6A
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English (en)
French (fr)
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EP3109895B1 (de
EP3109895A2 (de
Inventor
Anand S. Murthy
Daniel Bourne Aubertine
Tahir Ghani
Abhijit Jayant Pethe
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Intel Corp
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Intel Corp
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Publication of EP3109895A2 publication Critical patent/EP3109895A2/de
Publication of EP3109895A3 publication Critical patent/EP3109895A3/de
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Publication of EP3109895B1 publication Critical patent/EP3109895B1/de
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    • H—ELECTRICITY
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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EP16177334.6A 2009-12-21 2010-11-29 Halbleiterbauelement mit dotierter epitaktischer region Active EP3109895B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/643,912 US8598003B2 (en) 2009-12-21 2009-12-21 Semiconductor device having doped epitaxial region and its methods of fabrication
EP10842433.4A EP2517229B1 (de) 2009-12-21 2010-11-29 Herstellungsverfahren einer halbleitervorrichtung mit dotierter epitaktischer region
PCT/US2010/058199 WO2011084262A2 (en) 2009-12-21 2010-11-29 Semiconductor device having doped epitaxial region and its methods of fabrication

Related Parent Applications (2)

Application Number Title Priority Date Filing Date
EP10842433.4A Division-Into EP2517229B1 (de) 2009-12-21 2010-11-29 Herstellungsverfahren einer halbleitervorrichtung mit dotierter epitaktischer region
EP10842433.4A Division EP2517229B1 (de) 2009-12-21 2010-11-29 Herstellungsverfahren einer halbleitervorrichtung mit dotierter epitaktischer region

Publications (3)

Publication Number Publication Date
EP3109895A2 EP3109895A2 (de) 2016-12-28
EP3109895A3 true EP3109895A3 (de) 2017-02-15
EP3109895B1 EP3109895B1 (de) 2022-11-16

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Application Number Title Priority Date Filing Date
EP17164305.9A Active EP3208833B1 (de) 2009-12-21 2010-11-29 Halbleitervorrichtung mit epitaktischer region und herstellungsverfahren dafür
EP10842433.4A Active EP2517229B1 (de) 2009-12-21 2010-11-29 Herstellungsverfahren einer halbleitervorrichtung mit dotierter epitaktischer region
EP16177334.6A Active EP3109895B1 (de) 2009-12-21 2010-11-29 Halbleiterbauelement mit dotierter epitaktischer region

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Application Number Title Priority Date Filing Date
EP17164305.9A Active EP3208833B1 (de) 2009-12-21 2010-11-29 Halbleitervorrichtung mit epitaktischer region und herstellungsverfahren dafür
EP10842433.4A Active EP2517229B1 (de) 2009-12-21 2010-11-29 Herstellungsverfahren einer halbleitervorrichtung mit dotierter epitaktischer region

Country Status (8)

Country Link
US (4) US8598003B2 (de)
EP (3) EP3208833B1 (de)
JP (1) JP5615933B2 (de)
KR (1) KR101476628B1 (de)
CN (4) CN102687253B (de)
HK (1) HK1176741A1 (de)
TW (1) TWI564965B (de)
WO (1) WO2011084262A2 (de)

Families Citing this family (175)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994104B2 (en) 1999-09-28 2015-03-31 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
US8362575B2 (en) * 2009-09-29 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Controlling the shape of source/drain regions in FinFETs
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8492234B2 (en) * 2010-06-29 2013-07-23 International Business Machines Corporation Field effect transistor device
EP2588650A4 (de) * 2010-07-02 2014-03-19 Matheson Tri Gas Inc Selektive epitaxie si-haltiger materialien und substitutionell dotierter si-haltiger kristall-materialien
KR20120038195A (ko) * 2010-10-13 2012-04-23 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP2012089784A (ja) * 2010-10-22 2012-05-10 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US8778767B2 (en) * 2010-11-18 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits and fabrication methods thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US9484432B2 (en) 2010-12-21 2016-11-01 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
US8901537B2 (en) 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
WO2012108901A1 (en) * 2011-02-08 2012-08-16 Applied Materials, Inc. Epitaxy of high tensile silicon alloy for tensile strain applications
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8962400B2 (en) 2011-07-07 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ doping of arsenic for source and drain epitaxy
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8674433B2 (en) * 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
CN107123676A (zh) * 2011-09-30 2017-09-01 英特尔公司 非平坦晶体管以及其制造的方法
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8658505B2 (en) 2011-12-14 2014-02-25 International Business Machines Corporation Embedded stressors for multigate transistor devices
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
CN107068753B (zh) 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺
CN106887453B (zh) 2011-12-19 2020-08-21 英特尔公司 Ⅲ族-n纳米线晶体管
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
CN104126228B (zh) * 2011-12-23 2016-12-07 英特尔公司 非平面栅极全包围器件及其制造方法
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9466696B2 (en) 2012-01-24 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9171925B2 (en) 2012-01-24 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices with replaced-channels and methods for forming the same
US9281378B2 (en) 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8742509B2 (en) * 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US8785285B2 (en) * 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9224604B2 (en) 2012-04-05 2015-12-29 Globalfoundries Inc. Device and method for forming sharp extension region with controllable junction depth and lateral overlap
JP5833748B2 (ja) 2012-05-18 2015-12-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9368628B2 (en) 2012-07-05 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US8703556B2 (en) * 2012-08-30 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9318567B2 (en) * 2012-09-05 2016-04-19 United Microelectronics Corp. Fabrication method for semiconductor devices
US20140070358A1 (en) * 2012-09-12 2014-03-13 Globalfoundries Inc. Method of tailoring silicon trench profile for super steep retrograde well field effect transistor
US9105741B2 (en) * 2012-09-13 2015-08-11 International Business Machines Corporation Method of replacement source/drain for 3D CMOS transistors
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
KR20140039544A (ko) * 2012-09-24 2014-04-02 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN104854698A (zh) 2012-10-31 2015-08-19 三重富士通半导体有限责任公司 具有低变化晶体管外围电路的dram型器件以及相关方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9443962B2 (en) 2012-11-09 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase fin height in fin-first process
US9349837B2 (en) 2012-11-09 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Recessing STI to increase Fin height in Fin-first process
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US20140167163A1 (en) * 2012-12-17 2014-06-19 International Business Machines Corporation Multi-Fin FinFETs with Epitaxially-Grown Merged Source/Drains
US8900958B2 (en) 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US8853039B2 (en) 2013-01-17 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction for formation of epitaxial layer in source and drain regions
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US10134896B2 (en) * 2013-03-01 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Cyclic deposition etch chemical vapor deposition epitaxy to reduce EPI abnormality
US9356136B2 (en) * 2013-03-07 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Engineered source/drain region for n-Type MOSFET
US9831345B2 (en) * 2013-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with rounded source/drain profile
US8940640B2 (en) 2013-03-13 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure of semiconductor device
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
KR102038486B1 (ko) * 2013-04-09 2019-10-30 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9331176B2 (en) * 2013-04-25 2016-05-03 Samsung Electronics Co., Ltd. Methods of forming field effect transistors, including forming source and drain regions in recesses of semiconductor fins
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9070710B2 (en) * 2013-06-07 2015-06-30 United Microelectronics Corp. Semiconductor process
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
KR20150000546A (ko) * 2013-06-24 2015-01-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR20160029005A (ko) * 2013-06-28 2016-03-14 인텔 코포레이션 III-N 에피택시를 위한 Si (100) 웨이퍼들 상의 Si (111) 평면들을 가진 나노구조들 및 나노피처들
US9209175B2 (en) * 2013-07-17 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices having epitaxy regions with reduced facets
CN104425265B (zh) * 2013-08-20 2017-07-14 中芯国际集成电路制造(上海)有限公司 Pmos晶体管的形成方法及cmos晶体管的形成方法
US20160190319A1 (en) * 2013-09-27 2016-06-30 Intel Corporation Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates
US9246003B2 (en) * 2013-11-19 2016-01-26 Globalfoundries Inc. FINFET structures with fins recessed beneath the gate
US20150137237A1 (en) * 2013-11-21 2015-05-21 Globalfoundries Inc. Undoped epitaxial layer for junction isolation in a fin field effect transistor (finfet) device
CN103681355B (zh) * 2013-12-18 2016-04-06 北京大学 制备准soi源漏场效应晶体管器件的方法
US9711645B2 (en) * 2013-12-26 2017-07-18 International Business Machines Corporation Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
US9054189B1 (en) 2014-01-06 2015-06-09 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9490345B2 (en) * 2014-01-17 2016-11-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9698249B2 (en) * 2014-01-17 2017-07-04 Taiwan Semiconductor Manufacturing Company Ltd. Epitaxy in semiconductor structure and manufacturing method of the same
US10164107B2 (en) 2014-01-24 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with laterally extended portion
US9853154B2 (en) 2014-01-24 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region
KR102155181B1 (ko) 2014-01-28 2020-09-11 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102193493B1 (ko) 2014-02-03 2020-12-21 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9379214B2 (en) * 2014-02-14 2016-06-28 Semi Solutions Llc Reduced variation MOSFET using a drain-extension-last process
US9543410B2 (en) * 2014-02-14 2017-01-10 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
US9543387B2 (en) * 2014-03-10 2017-01-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
KR102017611B1 (ko) 2014-04-04 2019-09-04 삼성전자주식회사 반도체 장치 및 그 제조방법
CN105304481A (zh) * 2014-06-10 2016-02-03 联华电子股份有限公司 半导体元件及其制作方法
US9490365B2 (en) 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
US9502538B2 (en) 2014-06-12 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of fin-like field effect transistor
US9490346B2 (en) 2014-06-12 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of fin-like field effect transistor
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US9391200B2 (en) 2014-06-18 2016-07-12 Stmicroelectronics, Inc. FinFETs having strained channels, and methods of fabricating finFETs having strained channels
US10084063B2 (en) * 2014-06-23 2018-09-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9299803B2 (en) 2014-07-16 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for semiconductor device fabrication
CN105280492B (zh) * 2014-07-21 2018-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9530661B2 (en) * 2014-08-06 2016-12-27 Applied Materials, Inc. Method of modifying epitaxial growth shape on source drain area of transistor
KR102202754B1 (ko) 2014-08-14 2021-01-15 삼성전자주식회사 반도체 장치
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US10263108B2 (en) 2014-08-22 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insensitive epitaxy formation
DE102015100860A1 (de) 2014-08-22 2016-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metallunempfindliche Epitaxiebildung
US9536985B2 (en) * 2014-09-29 2017-01-03 Globalfoundries Inc. Epitaxial growth of material on source/drain regions of FinFET structure
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
US9673277B2 (en) 2014-10-20 2017-06-06 Applied Materials, Inc. Methods and apparatus for forming horizontal gate all around device structures
KR20170070281A (ko) * 2014-10-30 2017-06-21 어플라이드 머티어리얼스, 인코포레이티드 저온에서 얇은 에피택셜 필름들을 성장시키는 방법
CN105633152B (zh) * 2014-11-05 2019-12-10 联华电子股份有限公司 半导体结构及其制作方法
US9406568B2 (en) 2014-11-21 2016-08-02 International Business Machines Corporation Semiconductor structure containing low-resistance source and drain contacts
US10170554B2 (en) * 2014-12-26 2019-01-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9991384B2 (en) * 2015-01-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9406680B1 (en) * 2015-02-13 2016-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9991343B2 (en) * 2015-02-26 2018-06-05 Taiwan Semiconductor Manufacturing Company Ltd. LDD-free semiconductor structure and manufacturing method of the same
US9443957B1 (en) * 2015-03-12 2016-09-13 International Business Machines Corporation Self-aligned source and drain regions for semiconductor devices
KR20160112778A (ko) 2015-03-20 2016-09-28 삼성전자주식회사 핀 액티브 영역들을 갖는 반도체
KR102224849B1 (ko) 2015-03-24 2021-03-08 삼성전자주식회사 스트레서를 갖는 반도체 소자 및 그 제조 방법
WO2016164152A1 (en) 2015-04-10 2016-10-13 Applied Materials, Inc. Method to enhance growth rate for selective epitaxial growth
US9954107B2 (en) 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture
US9530889B2 (en) * 2015-05-21 2016-12-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
EP3311417A4 (de) * 2015-06-19 2019-01-16 Intel Corporation Kohlenstoffbasierten schnittstelle für epitaktisch gewachsene source/drain-transistorregionen
EP3311418A4 (de) * 2015-06-19 2019-01-09 Intel Corporation Widerstandsreduzierung in transistoren mit epitaxial gezüchteten source/drain-regionen
US10164096B2 (en) 2015-08-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10164097B2 (en) * 2015-09-11 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9647122B2 (en) * 2015-09-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US9607838B1 (en) 2015-09-18 2017-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Enhanced channel strain to reduce contact resistance in NMOS FET devices
KR102374321B1 (ko) 2015-10-14 2022-03-14 삼성전자주식회사 반도체 장치 제조 방법
US9722079B2 (en) 2015-10-15 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-type field effect transistor structure and manufacturing method thereof
CN106653751B (zh) * 2015-11-04 2019-12-03 中芯国际集成电路制造(北京)有限公司 半导体器件及其制造方法
KR102422158B1 (ko) 2015-12-23 2022-07-20 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
US9570567B1 (en) 2015-12-30 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Source and drain process for FinFET
US10796924B2 (en) 2016-02-18 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof by forming thin uniform silicide on epitaxial source/drain structure
US10276715B2 (en) * 2016-02-25 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9570556B1 (en) 2016-03-03 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9685554B1 (en) 2016-03-07 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and semiconductor device
US9853129B2 (en) * 2016-05-11 2017-12-26 Applied Materials, Inc. Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth
US10038094B2 (en) * 2016-05-31 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET structure and methods thereof
US10276663B2 (en) * 2016-07-18 2019-04-30 United Microelectronics Corp. Tunneling transistor and method of fabricating the same
CN108010846B (zh) * 2016-10-28 2020-08-07 中芯国际集成电路制造(上海)有限公司 用于改善短沟道效应的方法以及半导体结构
KR101960763B1 (ko) * 2016-11-03 2019-03-21 주식회사 유진테크 저온 에피택셜층 형성방법
KR102443814B1 (ko) * 2016-11-16 2022-09-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US11011634B2 (en) * 2016-11-30 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Elongated source/drain region structure in finFET device
US10170617B2 (en) * 2017-02-03 2019-01-01 Globalfoundries Vertical transport field effect transistors
TWI745365B (zh) * 2017-03-23 2021-11-11 聯華電子股份有限公司 半導體元件及其製作方法
KR102373630B1 (ko) 2017-05-26 2022-03-11 삼성전자주식회사 반도체 장치
US10468529B2 (en) * 2017-07-11 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with etch stop layer
KR102385567B1 (ko) 2017-08-29 2022-04-12 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN109950314B (zh) * 2017-12-21 2023-01-20 中芯国际集成电路制造(上海)有限公司 半导体结构及其制造方法
US11222980B2 (en) * 2019-07-18 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
KR20220041882A (ko) * 2019-08-01 2022-04-01 어플라이드 머티어리얼스, 인코포레이티드 트랜지스터들에 대한 비소 확산 프로파일 엔지니어링
JP7230877B2 (ja) * 2020-04-20 2023-03-01 株式会社Sumco エピタキシャルウェーハの製造システム及びエピタキシャルウェーハの製造方法
US11522049B2 (en) 2020-04-27 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion barrier layer for source and drain structures to increase transistor performance
TWI764399B (zh) * 2020-04-27 2022-05-11 台灣積體電路製造股份有限公司 半導體裝置、積體晶片及其形成方法
US11935793B2 (en) * 2020-05-29 2024-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Dual dopant source/drain regions and methods of forming same
US11482594B2 (en) 2020-08-27 2022-10-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside power rail and method thereof
US11854831B2 (en) * 2020-11-24 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Cleaning process for source/drain epitaxial structures

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080124878A1 (en) * 2006-11-28 2008-05-29 Cook Ted E Multi-component strain-inducing semiconductor regions
US20080242061A1 (en) * 2007-03-28 2008-10-02 Simonelli Danielle M Precursor gas mixture for depositing an epitaxial carbon-doped silicon film
US20090075029A1 (en) * 2007-09-19 2009-03-19 Asm America, Inc. Stressor for engineered strain on channel

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US7473947B2 (en) * 2002-07-12 2009-01-06 Intel Corporation Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby
US7786021B2 (en) 2002-11-14 2010-08-31 Sharp Laboratories Of America, Inc. High-density plasma multilayer gate oxide
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
KR100591157B1 (ko) 2004-06-07 2006-06-19 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7361563B2 (en) 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
US7539732B2 (en) 2004-09-15 2009-05-26 International Business Machines Corporation Client based instant messenger queue limit
US20060108651A1 (en) * 2004-11-22 2006-05-25 International Business Machines Corporation Lowered Source/Drain Transistors
US7195985B2 (en) 2005-01-04 2007-03-27 Intel Corporation CMOS transistor junction regions formed by a CVD etching and deposition sequence
DE102005004411B4 (de) 2005-01-31 2010-09-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren für die Herstellung eines in-situ-gebildeten Halo-Gebietes in einem Transistorelement
US7816236B2 (en) 2005-02-04 2010-10-19 Asm America Inc. Selective deposition of silicon-containing films
US7518196B2 (en) * 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7282415B2 (en) * 2005-03-29 2007-10-16 Freescale Semiconductor, Inc. Method for making a semiconductor device with strain enhancement
JP4984665B2 (ja) * 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7494858B2 (en) 2005-06-30 2009-02-24 Intel Corporation Transistor with improved tip profile and method of manufacture thereof
US7608515B2 (en) * 2006-02-14 2009-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion layer for stressed semiconductor devices
US7598178B2 (en) 2006-03-24 2009-10-06 Applied Materials, Inc. Carbon precursors for use during silicon epitaxial film formation
US20070238236A1 (en) * 2006-03-28 2007-10-11 Cook Ted Jr Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain
DE102006035665B4 (de) * 2006-07-31 2010-12-09 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Feldeffekttransistors und Feldeffekttransistor
US7554110B2 (en) * 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
US8394196B2 (en) 2006-12-12 2013-03-12 Applied Materials, Inc. Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US7960236B2 (en) * 2006-12-12 2011-06-14 Applied Materials, Inc. Phosphorus containing Si epitaxial layers in N-type source/drain junctions
JP2008235568A (ja) 2007-03-20 2008-10-02 Toshiba Corp 半導体装置およびその製造方法
US7732285B2 (en) * 2007-03-28 2010-06-08 Intel Corporation Semiconductor device having self-aligned epitaxial source and drain extensions
US8450165B2 (en) * 2007-05-14 2013-05-28 Intel Corporation Semiconductor device having tipless epitaxial source/drain regions
JP2009147265A (ja) * 2007-12-18 2009-07-02 Panasonic Corp 半導体装置及びその製造方法
US20090166625A1 (en) * 2007-12-28 2009-07-02 United Microelectronics Corp. Mos device structure
US7935589B2 (en) * 2008-04-29 2011-05-03 Chartered Semiconductor Manufacturing, Ltd. Enhanced stress for transistors
US20090302348A1 (en) * 2008-06-10 2009-12-10 International Business Machines Corporation Stress enhanced transistor devices and methods of making
JP4854719B2 (ja) * 2008-09-12 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080124878A1 (en) * 2006-11-28 2008-05-29 Cook Ted E Multi-component strain-inducing semiconductor regions
US20080242061A1 (en) * 2007-03-28 2008-10-02 Simonelli Danielle M Precursor gas mixture for depositing an epitaxial carbon-doped silicon film
US20090075029A1 (en) * 2007-09-19 2009-03-19 Asm America, Inc. Stressor for engineered strain on channel

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MATTHIAS BAUER ET AL: "Tensile Strained Selective Silicon Carbon Alloys for Recessed Source Drain Areas of Devices", ECS TRANSACTIONS, vol. 3, January 2006 (2006-01-01), US, pages 187 - 196, XP055301757, ISSN: 1938-5862, DOI: 10.1149/1.2355808 *
YEE-CHIA YEO: "Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions", SEMICONDUCTOR SCIENCE AND TECHNOLOGY, IOP PUBLISHING LTD, GB, vol. 22, no. 1, January 2007 (2007-01-01), pages S177 - S182, XP020114895, ISSN: 0268-1242, DOI: 10.1088/0268-1242/22/1/S42 *

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US11908934B2 (en) 2024-02-20
US20240145592A1 (en) 2024-05-02
US10957796B2 (en) 2021-03-23
WO2011084262A3 (en) 2011-09-09
US20140084369A1 (en) 2014-03-27
CN102687253B (zh) 2016-10-19
EP3109895B1 (de) 2022-11-16
TW201126614A (en) 2011-08-01
US20210159339A1 (en) 2021-05-27
US20110147828A1 (en) 2011-06-23
EP2517229A4 (de) 2014-05-07
CN107068737B (zh) 2022-07-26
US8598003B2 (en) 2013-12-03
WO2011084262A2 (en) 2011-07-14
CN107068737A (zh) 2017-08-18
TWI564965B (zh) 2017-01-01
CN105470287A (zh) 2016-04-06
HK1176741A1 (zh) 2013-08-02
CN111883591A (zh) 2020-11-03
EP2517229A2 (de) 2012-10-31
JP2013511159A (ja) 2013-03-28
JP5615933B2 (ja) 2014-10-29
EP3109895A2 (de) 2016-12-28
KR101476628B1 (ko) 2014-12-26
CN102687253A (zh) 2012-09-19
EP3208833A1 (de) 2017-08-23
CN105470287B (zh) 2020-07-14
KR20120086369A (ko) 2012-08-02

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