EP1974265A1 - Procédé de définition de matériels - Google Patents

Procédé de définition de matériels

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Publication number
EP1974265A1
EP1974265A1 EP07702834A EP07702834A EP1974265A1 EP 1974265 A1 EP1974265 A1 EP 1974265A1 EP 07702834 A EP07702834 A EP 07702834A EP 07702834 A EP07702834 A EP 07702834A EP 1974265 A1 EP1974265 A1 EP 1974265A1
Authority
EP
European Patent Office
Prior art keywords
hardware
data
registers
paes
pae
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP07702834A
Other languages
German (de)
English (en)
Inventor
Martin Vorbach
Frank May
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT XPP Technologies AG
Original Assignee
PACT XPP Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PACT XPP Technologies AG filed Critical PACT XPP Technologies AG
Priority to EP07702834A priority Critical patent/EP1974265A1/fr
Publication of EP1974265A1 publication Critical patent/EP1974265A1/fr
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Definitions

  • the present invention relates to the preamble and thus deals with a preferably reconfigurable architecture, or a preferably partially reconfigurable architecture, and a method for programming a cell array, wherein the elements of the array can perform a number of different functions, in particular one Variety of features that a general-purpose processor is obtained.
  • a reconfigurable architecture is understood in the broadest sense to mean an architecture in which at least one of elements of networks of data processing, storing and / or forwarding elements or elements itself is changeable;
  • a dynamically reconfigurable architecture is understood to mean the concept of reconfigurable architecture, as long as nothing else results from the respective context of meaning.
  • Dynamic may mean that it can be reconfigured at a rate that allows full and / or partial reconfiguration at run time; the reconfiguration can therefore take place for all cell elements, connecting elements etc. of a field, only for a subgroup of a field and / or for a single element of the field.
  • Reconfiguration may, and for the purpose of disclosure, refer to prior patent documents of the Applicant, all of which are incorporated in their entirety
  • the cell-to-cell direct data connection may alternatively and / or in addition to connecting multiple cells together by connecting to longer areas extending over extended portions of the field and / or with a reconfiguration entity and / or external entities such as data storage , Data sources and / or data receivers.
  • data receivers or sources may be, for example, displays, data interfaces, external (host) processors, co-processors, microcontrollers and / or on-chip sequencer units and the like.
  • Reconfiguration information may e.g. B. also be transmitted together with the data, eg. B. also interleaved in data words of a longer data packet, in any case, the data exchange between the cell elements can be done in a-synchronous manner anyway.
  • the transfer of configuration data from cell to cell can be done by transferring Licher configuration words for configuring a configurable cell element done and / or by transmission of triggers, in particular in trigger vector form, which is selected with these triggers between a plurality of still to be fed and / or already fed configurations for the trigger vector target receiver cell element ,
  • Hierarchical structures which can be constructed with and for processor fields of the present type, be it for configuration data and / or data to be processed, should be noted. It should be mentioned that trigger vectors can also be interposed in a data stream in order to select between a multiplicity of different, in particular previously stored, configurations in the manner of a configuration ID. If possible, consider several configurations on a configurable cell element in a time-mixing manner, as suggested, for example, in PCT / EP 02/02402 (PACT25 / PCTE), all of which are to the present assignee, supra In a preferred manner, it may be possible to also send information to cell elements during the data transmission, which relate to the affiliation of a data packet with a specific task to be processed.
  • a currently considered reconfigurable architecture for which a specific program is to be compiled is a (fully) homogeneous field in which, for example, as in the known XPP Applicant, a plurality of cells is provided with in particular segmented buses therebetween, wherein the cells may be A-LUs, some with extended functionality (EALUs), compare PCT / DE 97/02949 (PACTO2 / PCT) but not mandatory, and wherein on both sides of the ALU with the input and output buses coupled (multi-stage) register units may be provided, cf. B.
  • EALUs extended functionality
  • PACTO2 / PCT compare PCT / DE 97/02949
  • multi-stage register units may be provided, cf. B.
  • the communication of the cell elements is thereby preferably subjected to protocols, as described by the Applicant in connection with the XPP architecture. Mention should be made, in particular, of the RDY / ACK protocol, the RDY / ABLE protocol from PCT / DE 03/00489 (PACT16 / PCTD) and the other protocols described there, such as CREDIT protocols, etc., eg. B. Protocols with Rej ect option. The fact that the applicant has already indicated in previous applications that any received but no longer needed data packets can be discarded, is also mentioned. Mentioned here only by way of example also fully for other purposes, such as for applications with respect to the reconfigurable architecture, for example in connection with hyperthreading, processor coupling, etc. relevant PCT / EP 2004/003603 (PACT50 / PCTE), which are considered to be fully incorporated for purposes of disclosure is.
  • the cell elements may be formed and / or comprise in particular as ALU-PAEs EALU-PAEs, RAM-PAEs, RAM + ALU-PAEs, function-folding PAEs, cf. DE 10 2005 005 766.7, DE 10 2005 010 846.6, DE 10 2005 014 860.3, DE 10 2005 023 785.1, EP 05 005 832.0, EP 05 019 296.2, EP 05 020 297.7, EP 05 020 772.9, (PACT62 ff), graph-folding PAEs, sequencer structures connected via command lines, and PAEs in addition to a configurable or adjustable one Unit such as an ALU, a memory such as ring memory and the like, especially those with multiple pointers, etc., also fixed in their function once defined parts, such as FPGA-type logic circuits that are fixed, FPGA-like, only rarely and preferably without recourse to preferred, in particular faster configuration method reconfigurable groups and / or logic components in their functionality such as
  • the ASIC-like logic circuits that may be included in the cell elements may refer to fixed functions such as ASIC-type programmed DCT algorithms, FIR or IIR filters, VITERBI algorithms, etc., which are useful for various applications such as in General purpose processors, general purpose co-processors, microcontrollers, sequencers, image processing and / or processing such as for HDTV, cameras, base stations, mobile phones, software-definded radio, smart antennas, CODECs and / or parts thereof , may be of importance.
  • FIG. 1 shows a known method of creating and programming a reconfigurable architecture in the sense of the above remarks.
  • a library is provided which includes modules for a larger chip, including, but not limited to, an ALU-PAE definition, a RAMPACE definition, and so forth.
  • modules for a larger chip including, but not limited to, an ALU-PAE definition, a RAMPACE definition, and so forth.
  • a library is provided for a number of programs (software parts) in a language such as NML, this particular language, as mentioned, being known from other publications of the Applicant.
  • a program is written using such library software parts, and, apparently, software parts not included in the library may additionally and / or exclusively be used.
  • the program is then compiled, with compilation here to include placement and routing as required. To do this, the compiler needs information related to the actual target hardware design; the compiler has such information too.
  • the compiler generated configuration (s) will then be run as runtime configuration on the hardware.
  • the object of the present invention is to provide new products for commercial use.
  • FIG. 1 shows a procedure according to the prior art
  • FIG. 2 shows an inventively improved method for creating and / or programming hardware
  • Fig. 2 shows, as will be explained below, essentially parts of the design flow, as they are also known in Fig. 1 of the prior art, supplements and extends or changes this but in an inventive manner.
  • This program can be written in conventional high-level languages such as C ++, JAVA, MATLAB and so on.
  • C ++ C ++
  • JAVA JAVA
  • MATLAB MATLAB
  • a quasi-maximum-free hyperset that is to say a superset of possible hardware objects, which can comprise a plurality of variants of individual objects, wherein these variants are, for example, also preferred Parameter distinguishable manner from each other in one or more properties, as translated per se known translated.
  • a quasi-maximum-free hyperset that is to say a superset of possible hardware objects, which can comprise a plurality of variants of individual objects, wherein these variants are, for example, also preferred Parameter distinguishable manner from each other in one or more properties, as translated per se known translated.
  • the modules in the library may be intended for parameterized or parameterizable elements of the hyperset and, as well as the translation described above as done by the transform compiler, both completely and / or partially manufac tured by machine as well as optionally on request - hurry coding can happen. It should be mentioned that the use of modules in machine and / or manual translation is not mandatory.
  • the parameterization can be carried out interactively by a programmer, in particular by interaction with a placement and route tool, but possibly also fully automatically proposed by the programmer and if necessary only confirmed and / or determined without confirmation.
  • heuristic methods if appropriate also interactively and / or under the control and regulation of a placement and routing tool are possible.
  • an iterative approach can be done using the placement and route or other tool in the programming and hardware definition environment; It should be noted that such iterations can be carried out manually, semi-automatically and / or alternatively and more preferably fully automatically.
  • the heuristic can be used to specify desired sizes which are to be achieved with the iteration, for example by trial and error.
  • the methods of "simulated annealing" are explicitly referred to in this context for disclosure purposes.
  • quasimaximal free means for the hypermenge that the number of restrictions on generally available objects is as small as possible, that is, a maximum of degrees of freedom remain. Restrictions may be due to certain factors such.
  • the quasi-maxi- mum hyperset only has to contain one PAE that can be pam- eterized to a large extent and in many parameters, from which many different PAEs can be derived under parameterization ,
  • the final result is thus a program of a plurality of function blocks, which are indicated in FIG. 2 as f (n) for different n.
  • program parts may and will be configurations or configuration parts or a single configuration for an XPP field or the like from an at least partially reconfigurable set of elements described or to be described in the hyperset, in particular fully parameterizable under parameterization, such as ALU-PAEs, charting PAEs, function PAEs, MAC-PAEs, RAM-PAEs, ROP-PAEs and / or input-output PAEs.
  • Selection of program parts by hand which can be done in particular by inserting suitable text in the program code, such. By inserting control characters; Selection of those program parts which occur particularly frequently in the entire program code and / or have to be executed or are supposed to be executed in a large number of program codes which are to be executed independently on the hardware to be produced, that is to say Execution duration and / or frequency;
  • Modules where it can be seen that they are otherwise difficult or with increased clock frequency compared to other elements executable, that is, program parts that prove to be performance critical; the selection of such program parts may be preferred in order to to be able to execute certain program parts on a specific piece of hardware;
  • the selected program parts are initially on the already known and in the hyperset existing PAEs, which can also include PAEs in addition to the previously listed PAEs, consisting of a combination of the functionalities of the previously listed PAEs, so for example a paramet- rable or parameterized PAE with a configurable amount of parameterizable bit width and parameterizable range of functions, whereby further graph-folding, parameterizable elements may belong to this PAE, as well as function-folding, parameterizable elements which can be parameterized with regard to the bit width and / or in particular configurable memory areas with pointers and / or command control lines from one or more ALUs, or other data-changing parts in the PAE, to implement sequencers or microprocessors, input-output elements, and the like.
  • PAEs in addition to the previously listed PAEs, consisting of a combination of the functionalities of the previously listed PAEs, so for example a paramet- rable or parameterized PAE with a configurable amount of parameter
  • the buses are each k-bit wide, with k again representing a parameter, and n different buses are provided, from which the m different inputs are tapped. Also, n, the total number of buses, sets one In the exemplary embodiment of FIG.
  • a divider with combinatorial network for example, a multiplier, an ALU stage, a Boolean logic, a barrel shift stage (barrel shifter) are represented within the PAE by way of example
  • the above-mentioned units themselves are in turn parameterizable, for example with respect to the operand width, that is to say they may be, for example, 8-bit, 16-bit, 32-bit Bitwise or 64-bit stages or levels also obviously have a different bit width, and moreover the functional scope of, for example, the ALU, the flow point unit, etc. can be defined by parameters; agreed, omitted elements that might also be present in a hyper-PAE, such as sequencer units, function-folding PAEs, cf.
  • PCT / EP 03/09957 can be provided; It should also be noted in this context that reference is made in particular to the prior applications of the present applicant, in which a multiplicity of different logic elements as well as FPGA-type structures, SIMD arithmetic units etc. for PAEs are disclosed; this disclosure is fully incorporated.
  • the parameterizable range of functions it is possible, for example only in the case of the flux point unit, to be a floating-point unit which is capable of at least one, preferably a plurality of the following combinations in the still parameterizable definition: multiplication, addition, subtraction, division, floating-point combination, look-up tables, optionally with interpolation option for certain Functions such as trigonometric (sine, cosine, tangent), sequential calculations as for Taylor series, where special hardware may be provided for certain approximations / interpolations, and preferably further a parameterization of the floating point unit with respect to the data word width in Mantissa and / or exponent can be provided.
  • Functions such as trigonometric (sine, cosine, tangent)
  • Taylor series where special hardware may be provided for certain approximations / interpolations, and preferably further a parameterization of the floating point unit with respect to the data word width in Mantissa and / or exponent can be provided.
  • a parameterizable library for such a hyper-PAE may refer to a procedure using so-called if-def constructs. These lead certain program sections only to a translation (in hardware circuits that are actually to be provided on a chip), provided that corresponding definitions, for example by specifying the parameters, for example the range of functions, are given. That this is also possible for sizes and elements of the hyper-PAE, such as the configuration registers which are also provided at different depths, if appropriate, the protocols that can be implemented on a PAE (compare RDY / ACK, credit protocols, RDY / ABLE, etc.) as well as the parameterization of an output, different multiplexer stages in a PAE etc.
  • hyper-PAEs in the definition of the program parts, which are then used to implement hardware modules, proves surprisingly as not disturbing for the converter to hardware code. This is due to the fact that certain parameterizable properties, such as the bit width of the PAE, are already to be specified when determining the actual program for the transformation compiler, while other properties, such as the actual functional scope, ie the provision of a divider stage , a multiplier stage, an adder stage and / or a subtraction stage in an ALU-PAE need not yet be determined.
  • the quasi-maximum-free hyperset is set to a parameterized and / or Partially reduced Hyperteilmenge reduced, in particular less degrees of freedom are given, so must not be modified.
  • the bus widths to the cells can already be specified;
  • the NML-VERILOG converter or, more generally, the hardware-language description-generating converter are provided with the parameters already defined, for example, during the transformation compilation, which is indicated by corresponding statements in the program parts, for example Form of comment lines and / or by means of separate, • separate from the actual program part data can be done.
  • the transformation compiler is thus designed to generate parameterization information of hardware to be based on it. In contrast to conventional compilers, it also generates hardware-descriptive code that describes degrees of freedom.
  • the removal can not be done in a configuration of required elements in a PAE by the NML2V converter, that is in the isomorphic hardware simplification means, and / or that the selection of hardware elements to be removed is not made by synthesis can be.
  • the configuration register does not necessarily have to contain only a constant value, as is the case for better clarity. B. was shown. Rather, it is particularly when the hardware module waveartige changes or reconfigurations of the operation and / or conditional changes in the operation of a single element, such as depending on above or below data processing levels are required, several possible configurations can be stored in the configuration register.
  • the hardware module can also be defined so that freely definable configurations can still be processed on the defined hardware module, whereby these freely definable configurations then access a reduced set of functions in each individual element and / or limited connectivity between the individual elements of the hardware module defined in this way can be provided, for example, only in the case of neighbor-neighbor connections instead of global bus connections extending over many cells, although a multi-dimensional, that is also possibly significantly above two-dimensional connectivity and / or or a toroidal, also multi-dimensional toroidal connectivity can be implemented.
  • the preferably automatically generated hardware description code of the NMLV2 converter is now optimized in a particularly preferred variant of the invention.
  • the registers, linking units etc. which are not required for the respective functionality, are omitted in a parameterisable PII can be;
  • PCT / EP 03/08080 PACT30 / PCTE
  • PCT / EP 03/08081 PACT33 / PCTE
  • PAE-defintion encapsulated functional parts result. However, this is by no means critical, but on the contrary, with a suitably intelligent design chain, even very beneficial.
  • the proposed design chain according to the invention inherently has the intelligent design, which requires the elaborate encapsulation, which is required in the prior art.
  • for. B. first removes the internal, ie between the cells considered at their transitions to each other lying registers. The removal of the registers, however, does not happen blindly to all registers, but rather takes place more specifically, preferably without further automated selection of registers which are removable or which must remain in the hardware piece.
  • the hardware piece should first contain • constants.
  • registers for pre-loading of values PRELOAD register
  • Additional registers are initially not needed in a given process implementation.
  • bus registers can be readily used, feeding / reading data into RAM-PAEs with sufficient memory depth is possible and / or reading in / out of data in pre-load memory, if any - required, or the provision of input-output registers at the end and at the beginning of the hardware piece, unless the long-known FORWARD BACKWARD Register also for purposes of use by other PAEs should be made available. Constant contents of RAMs are realized in a preferred embodiment by ROMs or mapped to such.
  • the balancing would normally be or could be done by providing register levels between different data processing functionalities in or between the PAEs, etc.
  • the balancing would normally be or could be done by providing register levels between different data processing functionalities in or between the PAEs, etc.
  • the Hyper-PAE even with a given parameterization, will usually still have features that are not needed in the hardware module. For example, it would be conceivable that a hardware module is written for a program part in which no divisions are needed at all. In this case, a divider stage in a PAE would be dispensable. A division now requires a specific delay, ie a runtime via the module. This will be significantly greater than about the duration of an adder stage. The primary data runtime compensation of the parameterized or hyper-PAE will be such that the runtimes of a divider stage are taken into account.
  • a divider stage is no longer needed in a hardware module at a certain point, such an unneeded unit can and will preferably also be removed from the PAE, which then alters the delay of the data run by the unit.
  • the hardware module should also be adapted for re-timing. In principle, it should be noted that this is not absolutely necessary.
  • a certain advantage is already obtained if between the individual stages of a hardware composed of several hyper PAEs. module unused register stages are removed; in the preferred case, however, unnecessary parts are removed from the hyper PAEs, which can happen during the synthesis, such as. For example, the predisposed removal of a divider stage, but other stages such as storage stage elements, multipliers, floating point units, etc., are optionally removable.
  • a synthesis is preferably carried out, with which the timing behavior is analyzed automatically, in order to then automatically insert registers at required points and / or to give indications of where a programmer should insert registers in order to ensure a proper timing behavior.
  • the non-removal can z. This can be caused, for example, by references in the hardware-defining code of the hyper-PAE, which can lead to comments that are not necessary for actual program purposes and into a compiler code of the transformation compiler; alternatively and / or additionally saind variants are conceivable in which only removed and can be subsequently inserted again.
  • an identification of the hyper-PAEs can be made as to whether certain registers are algorithmically required so that they are not automatically removed upon initial removal of the registers; alternatively and / or additionally, in the removal of redundant registers, analyzes may be performed so that registers with a feedback to upstream circuit areas are not removed. In fact, such registers are automatically algorithmically relevant.
  • algorithmically needed registers are removable if the algorithm to which they are to be assigned is not executed; this is the case in the case of a sequential division generally provided in a hyper-PAE, if the division per se is not implemented in the hardware module to be built.
  • feedbacks in the standard PAEs provided by the Applicant are implemented by backward registers. As far as they are actually needed in a given program part, it is advantageous not to remove them or not unchecked and / or not completely.
  • registers are inserted with the re-timer. It should be mentioned that it is possible in principle, the Use registers anywhere in the hardware module as needed. In particular, it is possible to use registers within a (parameterized) hyper-PAE provided in the hardware module, if only performance-efficient care must be taken. It should be noted, however, that a simpler method of register insertion is obtained when the registers or a part of those registers which were first removed are re-inserted at the interfaces between several hyper PAEs in the hardware module to be designed. The reason for this is that optimal insertion is possible at these locations because the entire output definition of the hyper-PAEs is chosen so that insertion is automatically possible at these locations. Reference is made to the corresponding figure.
  • registers are the Hyper-PAEs used in parameterized form of the hardware module description, the input / output protocol registers, eg, the FREG / BREG of Hyper Alternatively, it is possible to provide PAEs without FREG / BREG only with those registers which are used in the direct coupling path of the ALUs and other logic elements for operand linking in the PAE in the connections to the buses as
  • Protocol registers are provided. Reference is made in particular to OREG and RREG from PCT / DE 97/02949 (PACT02 / PCT).
  • the newly inserted registers which ensure the balancing or the desired performance / area-efficient / latency after removal of the hatched registers, are shown by dashed lines in the figure and are referred to as "inserted register” or, for multi-level registers, as "inserted FIFO".
  • the illustrated insertion of registers, FIFOs and the like between the predefined hyper PAEs not only simplifies the structural design, but also facilitates the verification and calculation of the delay times via the circuits provided in the hardware module, since the runtime behavior etc
  • the underlying elements can be assumed to be well-known in the register removal step, which facilitates an optionally iterative approach to the re-timing task.
  • the insertion of registers between the pre-used and underlying (param- eterized) hyper-PAEs is particularly space-efficient, since, for. For example, using general ALUs in the hyper PAEs would require a large number of registers there, although the addition would also be readily possible there, for example to achieve very high frequencies. In addition, there is hardly a positive effect when cutting within an ALU or a PAE core.
  • a hardware module it is readily possible to design a hardware module to run at an operating frequency other than that intended for an XPP field or other reconfigurable unit field.
  • frequencies for example to reduce latencies, reduce the area and / or reduce power consumption. That may be worked to reduce the power consumption with other hardware definitions such as different gate thicknesses of transistors compared to a reconfigurable, also to be provided processor field, is disclosed for the sake of completeness.
  • other hardware definitions such as different gate thicknesses of transistors compared to a reconfigurable, also to be provided processor field
  • the register or FIFO stages to be inserted or newly inserted or to be reloaded not only with regard to z.
  • latencies may be used, but also to restore any balance of data flow paths destroyed, if any, by the initial removal of registers.
  • timing conditions may not be met; that then by the insertion of additional registers, the timing behavior is restored first, but thereby the balancing between individual data paths may be disturbed.
  • the output from the re-timer is an undoubtedly executable hardware code which is frequency-optimized and / or throughput-optimized by the re-timing by recourse to the hyper-PAEs or elements of the quasi-maximum-free hyper-quantity.
  • automatic area optimization results.
  • the resulting definition of new hardware areas as hard modules can now be integrated into the [XPP] library.
  • ways to integrate and / or connect the particular hardware module functionality into an XPP field or, more generally, a field of reconfigurable and / or partially reconfigurable elements For example, one possibility is to provide a complete PAE that does not have an ALU or a single sequencer as the central functionality, but rather the specified hardware functionality of the hardware module.
  • FIG 5a shows on the left a combination of an XPP field or FPGA field with a hardware module of the present invention, wherein the coupling of the hardware module to the field via FIFO memory takes place in the input and / or output path, preferably via FIFOs in FIG both ways.
  • the present invention is already achieved by the provision of a decoupling of a FIFO memory between the or JE the hardware module, which allows a particularly in terms of processing speed "more independent approach and a different timing and so on.
  • the exchanged data packets are provided with identification information in the form of a packet header or additional identification bits on each individual word or the like.
  • identification information in the form of a packet header or additional identification bits on each individual word or the like.
  • control commands or the like instead of a pure identification information and / or in order to select, for example, for slightly modifiable hardware modules, such as an addition or subtraction of successive operands is to execute and the like. In this way it can be achieved that an increased flexibility of the programming up to self-modifying code is achieved.
  • FIG. 5b shows how, for the coupling of a hardware module in the input and / or output path, a plurality of coupling elements which are now formed not as FIFOs but as RAM memory, in particular even as RAM PAEs, can be provided.
  • This allows in particular, both for writing data from the field for the hardware module and when writing from the hardware module for the field, that is, when transferring data from the field to the hardware module on the one hand and in the (here :) return results from the Hardware module to the field on the other hand each dedicated memory areas provide.
  • this facilitates handling with different configurations and, on the other hand, makes it possible, for example, to prioritize and preferably work on a first memory area, ie read and write, and only if data processing has been carried out sufficiently often on the first memory area and / or there There is no data available to other memory areas and therefore other tasks are resorted to.
  • the hardware module can use the XPP-FeId as a flexible data processing element and / or where hybrids are possible, so data ping-pong-like or pushed in a less regular manner for a total processing back and forth.
  • Fig. 6a shows a variant, wherein in turn data on FIFO memory are interchangeable and in particular again present at least either in the input and, preferably or in the output branch FI-FO memory.
  • trigger vectors will now be transmitted. With regard to the meaning and application of trigger vectors, reference is made to WO 98/35299 (PACT08 / PCT). The combination of identification information with programming information and / or trigger information or status information that is exchanged to trigger certain data processing or processes should be explicitly mentioned again.
  • RAMs read Write memories
  • the timestamp, which is transmitted, can be used to select those data packets with which processing is to take place next. It should be noted that in this way a particularly favorable control of the data processing is possible.
  • the actual procedure for transmitting time stamps with a data word or data packet in data flow processing is already described in WO 02/071249 (PACT18 / PCTE, butcher protocol).
  • WO 02/071249 PACTl8 / PCTE
  • WO 02/071248 PACT15 / PCTE
  • WO 02 / 071196 PACT25 / PCTE
  • WO 98/29952 PACT04 / PCT
  • WO 98/35299 PACT08 / PCT
  • WO 02/071196 PACT25 / PCTE
  • XPP or other fields are shown to be contiguous to one field as columns or rows, and, where appropriate, an array of such hardware modules as well or hardware parts would be umbbarbar and / or that individual elements or field groups may be distributed over the field, as shown in Fig. 8 bottom left.
  • a hardware element and / or a group of hardware elements according to the present invention could also be set next to an XPP or other field or, assuming corresponding manufacturing processes, could be placed on or below it.
  • the usability by integration on a single, co-manufactured chip is disclosed as a possibility in the same way as that to separately manufacture and connect the separate elements.
  • the arrangement is preferably connected via internal buses, whereas when arranged next to the field, a connection via I / O ports is preferred.
  • connections can alternatively be made via I / O ports and / or via internal buses.
  • bus lines or other lines can be pulled over via the hardware elements which are set between field elements.
  • hardware elements placed in a field may be connectable by separate lines as required.
  • the arrangement in columns is uniquely preferred, wherein depending on the purpose for which a data processing unit with hardware part of the present invention is to be used, an edge-side or intermediate setting of the column is preferred.
  • the number of hardware modules will be chosen such that, on the one hand, the pending data processing tasks can be solved quickly and efficiently, and, on the other hand, the form factor when inserted into or onto a field is taken into account.
  • the hardware modules of the present invention may additionally have their own I / O connections for communication with external elements such as memories and the like, even when they are tightly coupled to a field.
  • the functional scope of the hard module is typically chosen so that the functional scope at the desired location corresponds in each case to the union of the operand links executed or to be executed with different configurations. It should be noted that, where appropriate, in a multi-configuration hard-module definition, fixed configurations can be provided which are fixedly provided in the hard module, cf. PCT / EP 03/08080 (PACT30 / PCTE).
  • the functional scopes of the individual hard module areas obtained by parameterization that is to say determination of parameters of the hyper PAEs, are selected so that respective arithmetic units are considered individually have a minimal functionality. This may possibly be done by performing the configurations that are shared so that multiplications are always performed in the same PAE, if in each configuration only one multiplication is required, and, if necessary, with a multiplier in another PAE less space required for data return or data line, to be addressed by a particular configuration data lines, especially here as

Abstract

L'invention concerne un procédé de définition de matériels. Selon l'invention, une bibliothèque d'éléments exécutables, paramétrables, est mise en oeuvre, une sélection de paramètres est réalisée, les éléments sont combinés à des paramètres sélectionnés, et la combinaison est simplifiée.
EP07702834A 2006-01-18 2007-01-17 Procédé de définition de matériels Ceased EP1974265A1 (fr)

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EP07702834A EP1974265A1 (fr) 2006-01-18 2007-01-17 Procédé de définition de matériels
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US8250503B2 (en) 2012-08-21
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US20120278772A1 (en) 2012-11-01
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