EP1766648B1 - Fusible pour puce - Google Patents

Fusible pour puce Download PDF

Info

Publication number
EP1766648B1
EP1766648B1 EP05776175A EP05776175A EP1766648B1 EP 1766648 B1 EP1766648 B1 EP 1766648B1 EP 05776175 A EP05776175 A EP 05776175A EP 05776175 A EP05776175 A EP 05776175A EP 1766648 B1 EP1766648 B1 EP 1766648B1
Authority
EP
European Patent Office
Prior art keywords
layer
metallic conductor
fuse
intermediate layer
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP05776175A
Other languages
German (de)
English (en)
Other versions
EP1766648A1 (fr
Inventor
Werner Blum
Reiner Friedrich
Wolfgang Werner
Reimer Hinrichs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay BCcomponents Beyschlag GmbH
Original Assignee
Vishay BCcomponents Beyschlag GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vishay BCcomponents Beyschlag GmbH filed Critical Vishay BCcomponents Beyschlag GmbH
Publication of EP1766648A1 publication Critical patent/EP1766648A1/fr
Application granted granted Critical
Publication of EP1766648B1 publication Critical patent/EP1766648B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/046—Fuses formed as printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H69/00—Apparatus or processes for the manufacture of emergency protective devices
    • H01H69/02—Manufacture of fuses
    • H01H69/022—Manufacture of fuses of printed circuit fuses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/0039—Means for influencing the rupture process of the fusible element
    • H01H85/0047—Heating means
    • H01H85/006—Heat reflective or insulating layer on the casing or on the fuse support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411—Miniature fuses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411—Miniature fuses
    • H01H2085/0414—Surface mounted fuses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49107—Fuse making

Definitions

  • the invention relates to a fuse in chip design, which is applied to a carrier substrate made of an Al 2 O 3 ceramic, with a fusible metallic conductor, which is applied and structured by thin-film technology and which is provided with a cover layer, and an inexpensive method for production the chip backup.
  • Chip fuses are formed on a ceramic base material by means of methods known to those skilled in the art, for example photolithography. Other support materials, such as FR-4-epoxy or polyimide are known. Chip fuses are typically designed for a voltage of up to 63V.
  • the fuse In order to avoid damage to other electronic components by a disturbance in the electrical power supply, which causes an overvoltage or excessive current flow, it is known to provide a fuse in the power supply.
  • the fuse consists essentially of a carrier material and a metallic conductor, which consists for example of copper, aluminum or silver.
  • the geometry and cross section of the conductor determines the maximum possible current that can flow through this conductor without melting it. If this value is exceeded, the electrical conductor is melted due to the heat generated in it by its electrical resistance and thus The power supply is interrupted before downstream electronic components are overloaded or damaged.
  • the substrate underlays used are all-ceramic glazed ceramic substrates with a high Al 2 O 3 antinucleate or low-aluminum oxide ceramic substrates with a low thermal conductivity. Both types of substrate are compared to conventional ceramic substrates, eg. B. from 96% Al 2 O 3 in thick film quality, which are used in the manufacture of passive components, considerably more expensive.
  • a fusible metallic conductor is applied by electrochemical methods or by sputtering.
  • a particularly high precision of the turn-off or melting characteristic is achieved by photolithographic structuring of sputtered layers, wherein a low aluminum oxide substrate with low thermal conductivity serves as a base.
  • the JP 20031173728 A discloses a manufacturing method for a chip fuse in thin-film technology, wherein a fuse 14 and a cover layer 15 are arranged on a substrate 11.
  • the fuse 14 is patterned by photolithography.
  • the substrate 11 has a low thermal conductivity, in order not to dissipate the heat caused by the electric conductor 14 current in the electrical conductor 14 and thereby promote a melting of the electrical conductor 14.
  • the electrical conductor 14 is in direct contact with the substrate 11.
  • the JP 2002/140975 A describes a fuse with a metallic conductor 14 made of silver, which is also disposed directly on a substrate 11 with low thermal conductivity, wherein the metallic conductor 14 is electrodeposited or formed as a thick film.
  • the JP 2003/151425 A discloses a fuse with a glass-ceramic substrate 11 having a low thermal conductivity and a metallic conductor 14 in thick-film technology.
  • the JP 2002/279883 A also describes a fuse for a chip, in which the fusible region 17 of a conductor 15 is produced by a complex laser processing. This requires additional time and cost intensive processing steps.
  • the JP 20031234057 A discloses a fuse resistor having a resistor 30 on a substrate 10, wherein between the resistor 30 and the substrate 10, a further heat-storing layer 42 is provided to store the heat generated in the resistor 30 heat.
  • the fusible region is also produced by laser processing.
  • the JP 08/102244 A describes a fuse 10 in thick film technology with a glass-glaze layer 2 with a low thermal conductivity wherein the glass layer 2 is disposed on a ceramic substrate 1 and on the glass layer 2, a fuse 3 is applied.
  • the JP 10/050198 A discloses a further fuse in thin-film technology with a complex layer structure, in which on the conductor 3 and a glass layer 5, a further elastic silicone layer 6 is formed.
  • the DE 197 04 097 A1 describes an electrical fuse element with a fusible link in thick film technology and a carrier wherein the carrier consists of a poor thermal conductivity material, in particular of a glass ceramic.
  • the DE 695 12 519 T2 discloses a surface mounted fuse device wherein a thin film fusible conductor is disposed on a substrate and the substrate is preferably a FR-4 epoxy or a polyamide.
  • JP 09 063 454 A a chip fuse according to the preamble of claim 1 with a glass glaze layer (over the entire surface) over the carrier substrate.
  • An island-shaped formation of the glass layer is proposed only for the second, above the fusible conductor attached glass layer.
  • the hole conductor layer used is gold (Au) and silver (Ag).
  • the clamping electrodes are made of silver or silver-palladium.
  • the JP 09 429 115 A again describes a chip fuse with a full-surface glass glaze layer over the carrier substrate.
  • Aluminum is proposed as the fuse conductor layer.
  • the clamping electrodes consist of at least 3 silver-based layers.
  • the JP 10 050 198 A also describes a chip fuse with a full-surface glass glaze layer over the carrier substrate and a welterem Structure according to patent D1 with an additional silicone cover.
  • JP 09 153 328 also describes a chip fuse with a full-surface glass glaze over the carrier substrate accordingly JP 09 063 454 A with an aluminum fuse conductor layer and silver contacts.
  • the DE 101 64 240 A1 describes a switching protection device having a laminated copper or copper alloy layer formed around a columnar substrate body.
  • Paragraph [0076] proposes the use of a Cr adhesion layer between the copper layer and the ceramic body. It also describes filling previously patterned grooves in the metallic conductor with organic materials designed to protect the grooves from contamination with foreign materials, the organic fillers having low thermal conductivity. It is therefore a filling of grooves of a current-carrying metallization layer which has been deposited directly on the ceramic carrier substrate.
  • the DE 691 25 307 T2 describes a fuse Tellbauouou with a thin film fuse element and a Glaslsoltechniksbe slaughterung which are covered only a central portion of the substrate and which is provided with terminal attachment cuts and Kunststoffverhüllung.
  • the core idea of the invention is to combine the advantages of a low-cost passive component manufacturing process with the advantages of thin-film technology and precise photolithographic patterning, through the use of a thermally insulating interlayer on Al 2 O 3 ceramics in combination with thin-film technology and photolithographic patterning is realized.
  • the core idea of the invention is thus that between a low-cost ceramic substrate as a carrier with high thermal conductivity and the actual fusible metallic conductor an intermediate layer is provided, which is formed either by a cost-effective method, preferably applied in the island printing process low-melting inorganic glass paste or by an applied in island printing organic layer. Due to the low thermal conductivity of this intermediate layer, the heat arising in the metallic conductor through the current flowing through it is not dissipated downwardly through the carrier substrate with a usually higher thermal conductivity, so that melts in a desired current in the conductor this in the desired manner.
  • This intermediate layer serves as a thermal insulator.
  • a low-melting inorganic glass paste is used as the intermediate layer, which is applied in particular by screen printing on the carrier substrate.
  • the intermediate layer is an organic intermediate layer, which is applied in particular in island printing and subsequently baked or cured in a manner known to those skilled in the art by the action of heat in the carrier substrate.
  • any desired shaping of the intermediate layer can also be obtained by the simple island pressure, and the use of Al 2 O 3 ceramics as carrier material can be used.
  • the advantage of the invention is that a cost-effective standard ceramic, a thermally insulating intermediate layer which can be produced cost-effectively by screen printing can be combined with the advantage of thin-film technology and photolithographic structuring.
  • the carrier substrate used for the fuse an alumina substrate that is available from virtually all manufacturers of such ceramic substrates inexpensively and in any shape and size and z. B. is used in mass production of resistance manufacturers use.
  • Such aluminum oxide ceramic substrates can already be provided by the manufacturer with notches in the form of the chips to be produced later from the substrate.
  • the intermediate layers are applied, for example, in the region of the pre-bites given by the manufacturer, in order to separate the carrier substrate in a known manner without damaging the intermediate layers by breaking processes during a subsequent dicing process of the chips.
  • an inorganic or an organic adhesion promoter layer may be applied directly on the intermediate layer by spraying or by sputtering.
  • the metallic conductor is formed by a low-resistance metal layer in order to be able to set the melting point of the fuse accurately.
  • this metal layer is applied by sputtering to the intermediate layer or the adhesion promoter layer. If the sputtered metal layer were applied to a carrier substrate which had been glazed over the whole area, this would lead to a reduced adhesion, so that delamination of the metal layer in the pre-contact region could occur in a singulation process by means of breaking.
  • the metal layer on a thermally insulating island in the form of an intermediate layer with low thermal conductivity ensures the good adhesion of the metal layer in the contact area on the rougher aluminum oxide, as smooth surfaces are generated by these glass islands in the field of fuse, whereby the photolithographic structuring of the fuse particularly precise can be done because in contrast carrier substrates of thermally poorly conducting ceramics have higher surface roughness, which are unfavorable for a precise photolithographic patterning.
  • a metal layer is deposited over the whole area on the layer arranged thereunder, for example copper, and then the desired structure is photolithographically etched into the layer.
  • a negative lithography process is applied to the underlying layer, i. H. the intermediate layer or the adhesion promoter layer, first a photoresist is deposited, for example sprayed on, and then patterned in the desired manner by photolithography. Subsequently, a metal layer, for example a sputtered copper film, is deposited thereon and the remaining lacquer areas are removed thereon with the metal film.
  • one or more cover layers is applied to cover the metallic conductor or preferably the entire fuse, which may, inter alia, also be formed by an inorganic barrier layer.
  • the organic cover layer is in particular a polyamide, polyimide or an epoxide and can also be configured as a multilayer.
  • the end contacts of the metallic conductor are formed by electrodepositing a metallic barrier layer, typically nickel, and the final solderable or bondable layer, typically of tin or tin alloys.
  • a manufacturing process of a fuse 100 is deposited on a carrier substrate 10 (step a)), preferably an alumina ceramic, a thermally insulating intermediate layer 11 in island form (step b)).
  • An adhesion layer 12 for improving the adhesion of the metallic conductor 13 to the substrate is applied to this intermediate layer 11 and the surrounding carrier substrate 10 (step c)).
  • the metallic conductor 13 is applied to the adhesion layer 12, for example sputtered on a copper layer and photolithographically structured in the desired manner (step d)).
  • the maximum current is predetermined by the thickness and width of the web in the central region of the metallic conductor 13 at the crossing of this bridge melts and thus other electronic components are protected from damage.
  • the heat transfer into the carrier substrate 10 is strongly suppressed by the thermally insulating intermediate layer, so that the melting point of the fuse 100 can be precisely defined.
  • the fuse 100 or the middle region of the metallic conductor 13 is coated with an organic cover layer 14, for example a polyamide or an epoxy, in order to protect the fuse 100 against damage.
  • an organic cover layer 14 for example a polyamide or an epoxy, in order to protect the fuse 100 against damage.
  • For contacting the end contacts 15 of the metallic conductor 13 are galvanized, for example with nickel and tin.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Fuses (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Polysaccharides And Polysaccharide Derivatives (AREA)

Claims (4)

  1. Fusible (100) pour une puce sur un substrat porteur (10) fabriqué dans une céramique qui est une céramique de dioxyde d'aluminium en qualité couche épaisse ou couche fine, comprenant un conducteur (13) métallique fusible, placé et structuré au moyen d'une technique de couche fine et qui est muni d'une couche de protection (14), sachant qu'entre le substrat porteur (10) et le conducteur métallique (13), une couche intermédiaire (11) à faible conductibilité thermique est placée, le substrat porteur (10) étant une céramique Al2O3 à haute conductibilité thermique et le conducteur métallique fusible (13) étant appliqué par un procédé de pulvérisation ou de métallisation sous vide et structuré par une technique de lithographie,
    le conducteur métallique (13) est formé par une couche de métal à faible résistance, à savoir par un alliage Cu, Au, Ag, Sn ou un alliage à faible résistance Cu, Au, Ag, Sn et la couche de métal subit une pulvérisation ou une métallisation sous vide pendant le procédé sous vide,
    le conducteur métallique (13) est structuré avec un procédé de lithographie positif ou négatif,
    sur le conducteur métallique (13), une couche de protection (14) est formée par une couche anorganique respectivement organique, en particulier par un polyamide, un polyimide, un polyamidimide ou un époxy et en particulier est formée de plusieurs couches,
    caractérisé en ce que,
    la couche intermédiaire (11) est une pâte de verre anorganique à point de fusion bas appliquée par un procédé de sérigraphie ou une couche intermédiaire (11) organique appliquée par postlumination,
    des contacts terminaux (15) du fusible (100) sont formés par plongée ou de préférence par séparation galvanique, en particulier de cuivre, de nickel, d'étain ou d'alliages d'étain et
    une couche d'adhérence (12) est disposée sur la couche intermédiaire (11),
    le conducteur métallique (13) est alors placé sur la couche d'adhérence (12).
  2. Fusible selon la revendication 1, caractérisé en ce qu'une couche d'arrêt anorganique est formée entre la couche de protection (14) et le conducteur métallique (13).
  3. Procédé de fabrication d'un fusible (100) pour une puce, se composant d'un substrat porteur (10), d'une couche intermédiaire (11) à faible conductibilité thermique, d'une couche d'adhérence (12) placée sur la couche intermédiaire (11) et d'un conducteur thermique fusible (13) placé et structuré par une technique de couche fine et muni d'une couche de protection (14), sachant que
    - la couche intermédiaire (11) est placée sur le substrat porteur (10) en céramique Al2O3 de qualité de couche épaisse ou couche fine avec une haute conductibilité thermique,
    - la couche intermédiaire (11) est formée par une pâte de verre à point de fusion bas appliquée par un procédé de sérigraphie ou une couche intermédiaire (11) organique appliquée par postlumination,
    - sachant que le conducteur métallique (13) est placé sur la couche intermédiaire (11), sachant que le conducteur métallique (13) est placé sur la couche d'adhérence (12) et
    - la couche de protection (14) est placée sur le conducteur métallique (13),
    - le conducteur métallique (13) étant formé par une couche de métal à faible résistance, sachant que la couche de métal subit une pulvérisation ou une métallisation sous vide pendant le procédé sous vide et la couche de métal est formée par un alliage Cu, Au, Ag, Sn ou un alliage à faible résistance Cu, Au, Ag, Sn,
    - le conducteur métallique (13) est structuré par un procédé de lithographie positif ou négatif,
    - la couche de protection (14) est formée par une couche anorganique respectivement organique, en particulier par un polyamide, un polyimide, un polyamidimide ou un époxy et peut être formée également de plusieurs couches, et
    - des contacts terminaux (15) du fusible (100) sont formés par plongée ou de préférence par séparation galvanique, en particulier de cuivre, de nickel, d'étain ou d'alliages d'étain.
  4. Procédé selon la revendication 3, caractérisé en ce qu'une couche d'arrêt anorganique est formée entre la couche de protection (14) et le conducteur métallique (13).
EP05776175A 2004-07-08 2005-06-27 Fusible pour puce Active EP1766648B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004033251A DE102004033251B3 (de) 2004-07-08 2004-07-08 Schmelzsicherung für einem Chip
PCT/EP2005/006894 WO2006005435A1 (fr) 2004-07-08 2005-06-27 Fusible pour puce

Publications (2)

Publication Number Publication Date
EP1766648A1 EP1766648A1 (fr) 2007-03-28
EP1766648B1 true EP1766648B1 (fr) 2010-03-24

Family

ID=35414553

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05776175A Active EP1766648B1 (fr) 2004-07-08 2005-06-27 Fusible pour puce

Country Status (9)

Country Link
US (2) US9368308B2 (fr)
EP (1) EP1766648B1 (fr)
JP (1) JP2008505466A (fr)
KR (1) KR101128250B1 (fr)
CN (1) CN101010768B (fr)
AT (1) ATE462194T1 (fr)
DE (2) DE102004033251B3 (fr)
TW (1) TWI413146B (fr)
WO (1) WO2006005435A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004033251B3 (de) 2004-07-08 2006-03-09 Vishay Bccomponents Beyschlag Gmbh Schmelzsicherung für einem Chip
TWI323906B (en) * 2007-02-14 2010-04-21 Besdon Technology Corp Chip-type fuse and method of manufacturing the same
DE102007014334A1 (de) * 2007-03-26 2008-10-02 Robert Bosch Gmbh Schmelzlegierungselement, Thermosicherung mit einem Schmelzlegierungselement sowie Verfahren zum Herstellen einer Thermosicherung
US20090009281A1 (en) * 2007-07-06 2009-01-08 Cyntec Company Fuse element and manufacturing method thereof
JP4510858B2 (ja) * 2007-08-08 2010-07-28 釜屋電機株式会社 チップヒューズ及びその製造方法
JP5287154B2 (ja) * 2007-11-08 2013-09-11 パナソニック株式会社 回路保護素子およびその製造方法
US9190235B2 (en) * 2007-12-29 2015-11-17 Cooper Technologies Company Manufacturability of SMD and through-hole fuses using laser process
WO2010048782A1 (fr) * 2008-10-28 2010-05-06 南京萨特科技发展有限公司 Fusible de type puce et son procédé de fabrication
CN102891051B (zh) * 2011-07-22 2017-04-12 阿提瓦公司 并排保险丝组件及具该并排保险丝组件的电池阵列
CN107492473B (zh) * 2017-08-17 2019-01-04 中国振华集团云科电子有限公司 片式熔断器阻挡层的加工方法
US11636993B2 (en) 2019-09-06 2023-04-25 Eaton Intelligent Power Limited Fabrication of printed fuse
EP4415019A1 (fr) * 2023-02-09 2024-08-14 Littelfuse, Inc. Pâte conductrice hybride pour fusibles à faible réseau et à ouverture rapide

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3368919A (en) * 1964-07-29 1968-02-13 Sylvania Electric Prod Composite protective coat for thin film devices
US3887893A (en) * 1973-09-24 1975-06-03 Allen Bradley Co Fusible resistor
CH642772A5 (de) * 1977-05-28 1984-04-30 Knudsen Ak L Elektrische schmelzsicherung und deren herstellungsverfahren.
JPS5915394B2 (ja) * 1978-08-31 1984-04-09 富士通株式会社 厚膜微細パタ−ン生成方法
JPS57138961A (en) * 1981-02-23 1982-08-27 Fujitsu Ltd Crossover formation for thermal head
US4685203A (en) * 1983-09-13 1987-08-11 Mitsubishi Denki Kabushiki Kaisha Hybrid integrated circuit substrate and method of manufacturing the same
US4626818A (en) * 1983-11-28 1986-12-02 Centralab, Inc. Device for programmable thick film networks
US4754371A (en) * 1984-04-27 1988-06-28 Nec Corporation Large scale integrated circuit package
US4873506A (en) * 1988-03-09 1989-10-10 Cooper Industries, Inc. Metallo-organic film fractional ampere fuses and method of making
JP2772001B2 (ja) * 1988-11-28 1998-07-02 株式会社日立製作所 半導体装置
JPH02263445A (ja) * 1988-12-23 1990-10-26 Toshiba Corp 窒化アルミニウム基板およびそれを用いた半導体装置
US5097246A (en) * 1990-04-16 1992-03-17 Cooper Industries, Inc. Low amperage microfuse
US5166656A (en) * 1992-02-28 1992-11-24 Avx Corporation Thin film surface mount fuses
DE4329696C2 (de) * 1993-09-02 1995-07-06 Siemens Ag Auf Leiterplatten oberflächenmontierbares Multichip-Modul mit SMD-fähigen Anschlußelementen
US5363082A (en) * 1993-10-27 1994-11-08 Rapid Development Services, Inc. Flip chip microfuse
US5432378A (en) * 1993-12-15 1995-07-11 Cooper Industries, Inc. Subminiature surface mounted circuit protector
US5453726A (en) * 1993-12-29 1995-09-26 Aem (Holdings), Inc. High reliability thick film surface mount fuse assembly
US5552757A (en) * 1994-05-27 1996-09-03 Littelfuse, Inc. Surface-mounted fuse device
US5712610C1 (en) * 1994-08-19 2002-06-25 Sony Chemicals Corp Protective device
JPH08102244A (ja) * 1994-09-29 1996-04-16 Kyocera Corp チップヒューズ
JP2706625B2 (ja) * 1994-10-03 1998-01-28 エス・オー・シー株式会社 超小型チップヒューズ
US5929741A (en) * 1994-11-30 1999-07-27 Hitachi Chemical Company, Ltd. Current protector
JPH0963454A (ja) 1995-08-29 1997-03-07 Kyocera Corp チップヒューズ
JPH09129115A (ja) * 1995-10-30 1997-05-16 Kyocera Corp チップヒューズ
JPH09153328A (ja) * 1995-11-30 1997-06-10 Kyocera Corp チップヒューズ
US5699032A (en) * 1996-06-07 1997-12-16 Littelfuse, Inc. Surface-mount fuse having a substrate with surfaces and a metal strip attached to the substrate using layer of adhesive material
US5977860A (en) * 1996-06-07 1999-11-02 Littelfuse, Inc. Surface-mount fuse and the manufacture thereof
JPH1050198A (ja) * 1996-07-30 1998-02-20 Kyocera Corp チップヒューズ素子
DE19704097A1 (de) * 1997-02-04 1998-08-06 Wickmann Werke Gmbh Elektrisches Sicherungselement
US5914649A (en) * 1997-03-28 1999-06-22 Hitachi Chemical Company, Ltd. Chip fuse and process for production thereof
DE19738575A1 (de) * 1997-09-04 1999-06-10 Wickmann Werke Gmbh Elektrisches Sicherungselement
US6610440B1 (en) * 1998-03-10 2003-08-26 Bipolar Technologies, Inc Microscopic batteries for MEMS systems
US6002322A (en) * 1998-05-05 1999-12-14 Littelfuse, Inc. Chip protector surface-mounted fuse device
JP4396787B2 (ja) * 1998-06-11 2010-01-13 内橋エステック株式会社 薄型温度ヒュ−ズ及び薄型温度ヒュ−ズの製造方法
US6034589A (en) * 1998-12-17 2000-03-07 Aem, Inc. Multi-layer and multi-element monolithic surface mount fuse and method of making the same
US6078245A (en) * 1998-12-17 2000-06-20 Littelfuse, Inc. Containment of tin diffusion bar
JP3640146B2 (ja) * 1999-03-31 2005-04-20 ソニーケミカル株式会社 保護素子
JP2000306477A (ja) * 1999-04-16 2000-11-02 Sony Chem Corp 保護素子
JP2001052593A (ja) 1999-08-09 2001-02-23 Daito Tsushinki Kk ヒューズおよびその製造方法
JP2001325868A (ja) * 2000-05-17 2001-11-22 Sony Chem Corp 保護素子
JP2001325869A (ja) * 2000-05-17 2001-11-22 Sony Chem Corp 保護素子
JP4666427B2 (ja) * 2000-11-10 2011-04-06 東京エレクトロン株式会社 石英ウインドウ及び熱処理装置
JP2002140975A (ja) * 2000-11-01 2002-05-17 Koa Corp ヒューズ素子及びその製造方法
TW541556B (en) * 2000-12-27 2003-07-11 Matsushita Electric Ind Co Ltd Circuit protector
JP2002279883A (ja) * 2001-03-19 2002-09-27 Koa Corp チップ型ヒューズ抵抗器及びその製造方法
US7489229B2 (en) * 2001-06-11 2009-02-10 Wickmann-Werke Gmbh Fuse component
JP4204029B2 (ja) * 2001-11-30 2009-01-07 ローム株式会社 チップ抵抗器
JP2003173728A (ja) * 2001-12-06 2003-06-20 Koa Corp チップ型電流ヒューズの製造方法
US7436284B2 (en) * 2002-01-10 2008-10-14 Cooper Technologies Company Low resistance polymer matrix fuse apparatus and method
US7385475B2 (en) * 2002-01-10 2008-06-10 Cooper Technologies Company Low resistance polymer matrix fuse apparatus and method
US6891266B2 (en) * 2002-02-14 2005-05-10 Mia-Com RF transition for an area array package
JP4110967B2 (ja) * 2002-12-27 2008-07-02 ソニーケミカル＆インフォメーションデバイス株式会社 保護素子
JP2004214033A (ja) * 2002-12-27 2004-07-29 Sony Chem Corp 保護素子
JP2004265618A (ja) * 2003-02-05 2004-09-24 Sony Chem Corp 保護素子
JP2003234057A (ja) * 2003-03-10 2003-08-22 Koa Corp ヒューズ抵抗器およびその製造方法
US8680443B2 (en) * 2004-01-06 2014-03-25 Watlow Electric Manufacturing Company Combined material layering technologies for electric heaters
DE102004033251B3 (de) 2004-07-08 2006-03-09 Vishay Bccomponents Beyschlag Gmbh Schmelzsicherung für einem Chip
US8976001B2 (en) * 2010-11-08 2015-03-10 Cyntec Co., Ltd. Protective device

Also Published As

Publication number Publication date
US10354826B2 (en) 2019-07-16
DE102004033251B3 (de) 2006-03-09
EP1766648A1 (fr) 2007-03-28
WO2006005435A1 (fr) 2006-01-19
US20160372293A1 (en) 2016-12-22
DE502005009279D1 (de) 2010-05-06
US9368308B2 (en) 2016-06-14
US20080303626A1 (en) 2008-12-11
CN101010768A (zh) 2007-08-01
TW200612453A (en) 2006-04-16
CN101010768B (zh) 2011-03-30
KR20070038143A (ko) 2007-04-09
JP2008505466A (ja) 2008-02-21
TWI413146B (zh) 2013-10-21
ATE462194T1 (de) 2010-04-15
KR101128250B1 (ko) 2012-03-23

Similar Documents

Publication Publication Date Title
EP1766648B1 (fr) Fusible pour puce
DE3725438C2 (de) Sicherung
DE68923339T2 (de) Mikroschmelzsicherheiten mit metall-organichem film sowie herstellungsverfahren.
DE112006002516B4 (de) Chip-Widertand und Befestigungsstruktur für einen Chip-Widerstand
DE69005785T2 (de) Elektrischer Widerstand in Chip-Bauweise für Oberflächenbestückung und Verfahren zu seiner Herstellung.
DE69512519T2 (de) Oberflächenmontierte sicherungsvorrichtung
DE69523991T2 (de) Löt-Anschlusskontakt und Verfahren zu seiner Herstellung
EP0844459B1 (fr) Capteur magnétique de position du type passif
EP1756537B1 (fr) Capteur de temperature et son procede de production
EP3371565B1 (fr) Élément capteur et procédé de fabrication d'un élément capteur
DE69500388T2 (de) Filmschaltungs-Metallsystem zur Verwendung in IC-Bauteilen mit Kontakthöckern
EP0538280B1 (fr) Assemblage d'un commutateur a rheostat incorpore
EP0841668B1 (fr) Résistance électrique et son procédé de fabrication
EP0850489B1 (fr) Support de depot de metal d'apport de brasage
DE3722576A1 (de) Elektrischer schichtwiderstand und verfahren zu dessen herstellung
EP0234487B1 (fr) Circuit à couche mince et procédé pour sa fabrication
DE112020002188T5 (de) Oberflächenmontierte Dünnschichtsicherung mit nachgiebigen Endteilen
EP2067390B1 (fr) Procédé de fabrication d'un agencement de composants optoélectroniques et agencement de composants optoélectroniques
EP0069903B1 (fr) Pièce de liaison électrique pour composants semiconducteurs
JP3118509B2 (ja) チップ抵抗器
DE3616185A1 (de) Halbleiterbauelement
DE102011054485A1 (de) Niedrigstrom-Sicherung
EP3961170A1 (fr) Capteur de température et procédé de fabrication d'un tel capteur de température
WO1987007080A1 (fr) Composant a semiconducteur
DE10357673A1 (de) Montage- und Klebeschicht für Halbleiterbauelement

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20061227

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

17Q First examination report despatched

Effective date: 20070503

DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 502005009279

Country of ref document: DE

Date of ref document: 20100506

Kind code of ref document: P

REG Reference to a national code

Ref country code: RO

Ref legal event code: EPE

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20100324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

LTIE Lt: invalidation of european patent or patent extension

Effective date: 20100324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100625

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100705

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

REG Reference to a national code

Ref country code: HU

Ref legal event code: AG4A

Ref document number: E008286

Country of ref document: HU

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100724

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100624

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

BERE Be: lapsed

Owner name: VISHAY BCCOMPONENTS BEYSCHLAG G.M.B.H.

Effective date: 20100630

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100726

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100630

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20100627

26N No opposition filed

Effective date: 20101228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100630

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100627

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100627

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: HU

Payment date: 20110623

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: RO

Payment date: 20110620

Year of fee payment: 7

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20100627

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100324

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RO

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120627

Ref country code: HU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120628

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 12

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 13

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CZ

Payment date: 20240617

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240617

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240828

Year of fee payment: 20