EP1766648B1 - Safety fuse for a chip - Google Patents

Safety fuse for a chip Download PDF

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Publication number
EP1766648B1
EP1766648B1 EP05776175A EP05776175A EP1766648B1 EP 1766648 B1 EP1766648 B1 EP 1766648B1 EP 05776175 A EP05776175 A EP 05776175A EP 05776175 A EP05776175 A EP 05776175A EP 1766648 B1 EP1766648 B1 EP 1766648B1
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EP
European Patent Office
Prior art keywords
layer
metallic conductor
fuse
intermediate layer
low
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EP05776175A
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German (de)
French (fr)
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EP1766648A1 (en
Inventor
Werner Blum
Reiner Friedrich
Wolfgang Werner
Reimer Hinrichs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay BCcomponents Beyschlag GmbH
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Vishay BCcomponents Beyschlag GmbH
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02Details
    • H01H85/04Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/046Fuses formed as printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H69/00Apparatus or processes for the manufacture of emergency protective devices
    • H01H69/02Manufacture of fuses
    • H01H69/022Manufacture of fuses of printed circuit fuses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/0039Means for influencing the rupture process of the fusible element
    • H01H85/0047Heating means
    • H01H85/006Heat reflective or insulating layer on the casing or on the fuse support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02Details
    • H01H85/04Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411Miniature fuses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02Details
    • H01H85/04Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/0411Miniature fuses
    • H01H2085/0414Surface mounted fuses
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49107Fuse making

Definitions

  • the invention relates to a fuse in chip design, which is applied to a carrier substrate made of an Al 2 O 3 ceramic, with a fusible metallic conductor, which is applied and structured by thin-film technology and which is provided with a cover layer, and an inexpensive method for production the chip backup.
  • Chip fuses are formed on a ceramic base material by means of methods known to those skilled in the art, for example photolithography. Other support materials, such as FR-4-epoxy or polyimide are known. Chip fuses are typically designed for a voltage of up to 63V.
  • the fuse In order to avoid damage to other electronic components by a disturbance in the electrical power supply, which causes an overvoltage or excessive current flow, it is known to provide a fuse in the power supply.
  • the fuse consists essentially of a carrier material and a metallic conductor, which consists for example of copper, aluminum or silver.
  • the geometry and cross section of the conductor determines the maximum possible current that can flow through this conductor without melting it. If this value is exceeded, the electrical conductor is melted due to the heat generated in it by its electrical resistance and thus The power supply is interrupted before downstream electronic components are overloaded or damaged.
  • the substrate underlays used are all-ceramic glazed ceramic substrates with a high Al 2 O 3 antinucleate or low-aluminum oxide ceramic substrates with a low thermal conductivity. Both types of substrate are compared to conventional ceramic substrates, eg. B. from 96% Al 2 O 3 in thick film quality, which are used in the manufacture of passive components, considerably more expensive.
  • a fusible metallic conductor is applied by electrochemical methods or by sputtering.
  • a particularly high precision of the turn-off or melting characteristic is achieved by photolithographic structuring of sputtered layers, wherein a low aluminum oxide substrate with low thermal conductivity serves as a base.
  • the JP 20031173728 A discloses a manufacturing method for a chip fuse in thin-film technology, wherein a fuse 14 and a cover layer 15 are arranged on a substrate 11.
  • the fuse 14 is patterned by photolithography.
  • the substrate 11 has a low thermal conductivity, in order not to dissipate the heat caused by the electric conductor 14 current in the electrical conductor 14 and thereby promote a melting of the electrical conductor 14.
  • the electrical conductor 14 is in direct contact with the substrate 11.
  • the JP 2002/140975 A describes a fuse with a metallic conductor 14 made of silver, which is also disposed directly on a substrate 11 with low thermal conductivity, wherein the metallic conductor 14 is electrodeposited or formed as a thick film.
  • the JP 2003/151425 A discloses a fuse with a glass-ceramic substrate 11 having a low thermal conductivity and a metallic conductor 14 in thick-film technology.
  • the JP 2002/279883 A also describes a fuse for a chip, in which the fusible region 17 of a conductor 15 is produced by a complex laser processing. This requires additional time and cost intensive processing steps.
  • the JP 20031234057 A discloses a fuse resistor having a resistor 30 on a substrate 10, wherein between the resistor 30 and the substrate 10, a further heat-storing layer 42 is provided to store the heat generated in the resistor 30 heat.
  • the fusible region is also produced by laser processing.
  • the JP 08/102244 A describes a fuse 10 in thick film technology with a glass-glaze layer 2 with a low thermal conductivity wherein the glass layer 2 is disposed on a ceramic substrate 1 and on the glass layer 2, a fuse 3 is applied.
  • the JP 10/050198 A discloses a further fuse in thin-film technology with a complex layer structure, in which on the conductor 3 and a glass layer 5, a further elastic silicone layer 6 is formed.
  • the DE 197 04 097 A1 describes an electrical fuse element with a fusible link in thick film technology and a carrier wherein the carrier consists of a poor thermal conductivity material, in particular of a glass ceramic.
  • the DE 695 12 519 T2 discloses a surface mounted fuse device wherein a thin film fusible conductor is disposed on a substrate and the substrate is preferably a FR-4 epoxy or a polyamide.
  • JP 09 063 454 A a chip fuse according to the preamble of claim 1 with a glass glaze layer (over the entire surface) over the carrier substrate.
  • An island-shaped formation of the glass layer is proposed only for the second, above the fusible conductor attached glass layer.
  • the hole conductor layer used is gold (Au) and silver (Ag).
  • the clamping electrodes are made of silver or silver-palladium.
  • the JP 09 429 115 A again describes a chip fuse with a full-surface glass glaze layer over the carrier substrate.
  • Aluminum is proposed as the fuse conductor layer.
  • the clamping electrodes consist of at least 3 silver-based layers.
  • the JP 10 050 198 A also describes a chip fuse with a full-surface glass glaze layer over the carrier substrate and a welterem Structure according to patent D1 with an additional silicone cover.
  • JP 09 153 328 also describes a chip fuse with a full-surface glass glaze over the carrier substrate accordingly JP 09 063 454 A with an aluminum fuse conductor layer and silver contacts.
  • the DE 101 64 240 A1 describes a switching protection device having a laminated copper or copper alloy layer formed around a columnar substrate body.
  • Paragraph [0076] proposes the use of a Cr adhesion layer between the copper layer and the ceramic body. It also describes filling previously patterned grooves in the metallic conductor with organic materials designed to protect the grooves from contamination with foreign materials, the organic fillers having low thermal conductivity. It is therefore a filling of grooves of a current-carrying metallization layer which has been deposited directly on the ceramic carrier substrate.
  • the DE 691 25 307 T2 describes a fuse Tellbauouou with a thin film fuse element and a Glaslsoltechniksbe slaughterung which are covered only a central portion of the substrate and which is provided with terminal attachment cuts and Kunststoffverhüllung.
  • the core idea of the invention is to combine the advantages of a low-cost passive component manufacturing process with the advantages of thin-film technology and precise photolithographic patterning, through the use of a thermally insulating interlayer on Al 2 O 3 ceramics in combination with thin-film technology and photolithographic patterning is realized.
  • the core idea of the invention is thus that between a low-cost ceramic substrate as a carrier with high thermal conductivity and the actual fusible metallic conductor an intermediate layer is provided, which is formed either by a cost-effective method, preferably applied in the island printing process low-melting inorganic glass paste or by an applied in island printing organic layer. Due to the low thermal conductivity of this intermediate layer, the heat arising in the metallic conductor through the current flowing through it is not dissipated downwardly through the carrier substrate with a usually higher thermal conductivity, so that melts in a desired current in the conductor this in the desired manner.
  • This intermediate layer serves as a thermal insulator.
  • a low-melting inorganic glass paste is used as the intermediate layer, which is applied in particular by screen printing on the carrier substrate.
  • the intermediate layer is an organic intermediate layer, which is applied in particular in island printing and subsequently baked or cured in a manner known to those skilled in the art by the action of heat in the carrier substrate.
  • any desired shaping of the intermediate layer can also be obtained by the simple island pressure, and the use of Al 2 O 3 ceramics as carrier material can be used.
  • the advantage of the invention is that a cost-effective standard ceramic, a thermally insulating intermediate layer which can be produced cost-effectively by screen printing can be combined with the advantage of thin-film technology and photolithographic structuring.
  • the carrier substrate used for the fuse an alumina substrate that is available from virtually all manufacturers of such ceramic substrates inexpensively and in any shape and size and z. B. is used in mass production of resistance manufacturers use.
  • Such aluminum oxide ceramic substrates can already be provided by the manufacturer with notches in the form of the chips to be produced later from the substrate.
  • the intermediate layers are applied, for example, in the region of the pre-bites given by the manufacturer, in order to separate the carrier substrate in a known manner without damaging the intermediate layers by breaking processes during a subsequent dicing process of the chips.
  • an inorganic or an organic adhesion promoter layer may be applied directly on the intermediate layer by spraying or by sputtering.
  • the metallic conductor is formed by a low-resistance metal layer in order to be able to set the melting point of the fuse accurately.
  • this metal layer is applied by sputtering to the intermediate layer or the adhesion promoter layer. If the sputtered metal layer were applied to a carrier substrate which had been glazed over the whole area, this would lead to a reduced adhesion, so that delamination of the metal layer in the pre-contact region could occur in a singulation process by means of breaking.
  • the metal layer on a thermally insulating island in the form of an intermediate layer with low thermal conductivity ensures the good adhesion of the metal layer in the contact area on the rougher aluminum oxide, as smooth surfaces are generated by these glass islands in the field of fuse, whereby the photolithographic structuring of the fuse particularly precise can be done because in contrast carrier substrates of thermally poorly conducting ceramics have higher surface roughness, which are unfavorable for a precise photolithographic patterning.
  • a metal layer is deposited over the whole area on the layer arranged thereunder, for example copper, and then the desired structure is photolithographically etched into the layer.
  • a negative lithography process is applied to the underlying layer, i. H. the intermediate layer or the adhesion promoter layer, first a photoresist is deposited, for example sprayed on, and then patterned in the desired manner by photolithography. Subsequently, a metal layer, for example a sputtered copper film, is deposited thereon and the remaining lacquer areas are removed thereon with the metal film.
  • one or more cover layers is applied to cover the metallic conductor or preferably the entire fuse, which may, inter alia, also be formed by an inorganic barrier layer.
  • the organic cover layer is in particular a polyamide, polyimide or an epoxide and can also be configured as a multilayer.
  • the end contacts of the metallic conductor are formed by electrodepositing a metallic barrier layer, typically nickel, and the final solderable or bondable layer, typically of tin or tin alloys.
  • a manufacturing process of a fuse 100 is deposited on a carrier substrate 10 (step a)), preferably an alumina ceramic, a thermally insulating intermediate layer 11 in island form (step b)).
  • An adhesion layer 12 for improving the adhesion of the metallic conductor 13 to the substrate is applied to this intermediate layer 11 and the surrounding carrier substrate 10 (step c)).
  • the metallic conductor 13 is applied to the adhesion layer 12, for example sputtered on a copper layer and photolithographically structured in the desired manner (step d)).
  • the maximum current is predetermined by the thickness and width of the web in the central region of the metallic conductor 13 at the crossing of this bridge melts and thus other electronic components are protected from damage.
  • the heat transfer into the carrier substrate 10 is strongly suppressed by the thermally insulating intermediate layer, so that the melting point of the fuse 100 can be precisely defined.
  • the fuse 100 or the middle region of the metallic conductor 13 is coated with an organic cover layer 14, for example a polyamide or an epoxy, in order to protect the fuse 100 against damage.
  • an organic cover layer 14 for example a polyamide or an epoxy, in order to protect the fuse 100 against damage.
  • For contacting the end contacts 15 of the metallic conductor 13 are galvanized, for example with nickel and tin.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Fuses (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Polysaccharides And Polysaccharide Derivatives (AREA)

Abstract

To produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al2O3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.

Description

Technisches GebietTechnical area

Die Erfindung betrifft eine Schmelzsicherung in Chipbauform, die auf einem Trägersubstrat aus einer Al2O3-Keramik aufgebracht ist, mit einem aufschmelzbaren metallischen Leiter, der mittels Dünnschichttechnik aufgebracht und strukturiert ist und der mit einer Deckschicht versehen ist, sowie ein kostengünstiges Verfahren zur Herstellung der Chipsicherung.The invention relates to a fuse in chip design, which is applied to a carrier substrate made of an Al 2 O 3 ceramic, with a fusible metallic conductor, which is applied and structured by thin-film technology and which is provided with a cover layer, and an inexpensive method for production the chip backup.

Stand der TechnikState of the art

Chipsicherungen werden auf einem keramischen Grundmaterial mit Hilfe dem Fachmann bekannter Verfahren beispielsweise der Photolithographie ausgebildet. Auch andere Trägermaterialen, wie FR-4-Epoxid oder Polyimid sind bekannt. Chipsicherungen werden üblicherweise für eine Spannung bis zu 63 V ausgelegt.Chip fuses are formed on a ceramic base material by means of methods known to those skilled in the art, for example photolithography. Other support materials, such as FR-4-epoxy or polyimide are known. Chip fuses are typically designed for a voltage of up to 63V.

Um eine Beschädigung anderer elektronischer Komponenten durch eine Störung in der elektrischen Stromversorgung, die eine Überspannung oder einen zu großen Stromfluss herbeiführt, zu vermeiden ist es bekannt, in der Stromversorgung eine Schmelzsicherung vorzusehen. Die Schmelzsicherung besteht im Wesentlichen aus einem Trägermaterial und einem metallischem Leiter, der beispielsweise aus Kupfer, Aluminium oder Silber besteht. Durch die Geometrie und den Querschnitt des Leiters wird die maximal mögliche Stromstärke, die durch diesen Leiter fließen kann ohne ihn aufzuschmelzen bestimmt. Wird dieser Wert überschritten so wird der elektrische Leiter aufgrund der in ihm durch seinen elektrischen Widerstand anfallenden Wärme aufgeschmolzen und somit die Stromversorgung unterbrochen bevor nachgeschaltete elektronische Komponenten überlastet oder beschädigt werden.In order to avoid damage to other electronic components by a disturbance in the electrical power supply, which causes an overvoltage or excessive current flow, it is known to provide a fuse in the power supply. The fuse consists essentially of a carrier material and a metallic conductor, which consists for example of copper, aluminum or silver. The geometry and cross section of the conductor determines the maximum possible current that can flow through this conductor without melting it. If this value is exceeded, the electrical conductor is melted due to the heat generated in it by its electrical resistance and thus The power supply is interrupted before downstream electronic components are overloaded or damaged.

Bei den Verfahren zur Herstellung von Chipsicherungen in Dickschichttechnik, bei denen die Schmelzelemente und Kontaktschichten als Pasten mittels Siebdruck auf eine Substratunterlage mit niedriger thermischer Leitfähigkeit aufgebracht werden sind ausreichende Präzisionen der Geometrie der Schmelzelementschichten durch das Siebdruckverfahren prozessbedingt nur unzureichend realisierbar. Für höherwertige Dickschichtsicherungen ist es daher notwendig, durch zusätzliche Laserschnittverfahren das Schmelzelement bzw. den aufschmelzbaren metallischen Leiter zu bearbeiten.In the methods for the production of chip fuses in thick film technology, in which the fuses and contact layers are applied as pastes by screen printing on a substrate substrate with low thermal conductivity sufficient precision of the geometry of the fusible element layers by the screen printing process due to the process only insufficiently feasible. For higher-quality thick-film fuses, it is therefore necessary to process the fusible element or the fusible metallic conductor by additional laser cutting methods.

Üblicherweise werden als Substratunteriage ganzflächig glasierte Keramiksubstrate mit hohem Al2O3-Antell oder aluminiumoxidarme Keramiksubstrate mit niedriger thermischer Leitfähigkeit gewählt. Beide Substratarten sind im Vergleich zu herkömmlichen Keramiksubstraten, z. B. aus 96% Al2O3 in Dickschichtqualität, die in der Herstellung passiver Bauelemente Verwendung finden, erheblich teurer.Conventionally, the substrate underlays used are all-ceramic glazed ceramic substrates with a high Al 2 O 3 antinucleate or low-aluminum oxide ceramic substrates with a low thermal conductivity. Both types of substrate are compared to conventional ceramic substrates, eg. B. from 96% Al 2 O 3 in thick film quality, which are used in the manufacture of passive components, considerably more expensive.

Bei einem Verfahren zur Herstellung einer Schmelzsicherung in Dünnschichttechnik wird ein aufschmelzbarer metallischer Leiter durch elektrochemische Verfahren oder durch Sputtern aufgebracht. Eine besonders hohe Präzision der Abschalt- bzw. Schmelzcharakteristik wird dabei durch photolithographische Strukturierung von gesputterten Schichten erreicht, wobei als Unterlage ein aluminiumoxidarmes Substrat mit niedriger thermischer Leitfähigkeit dient.In a method for producing a fuse in thin-film technology, a fusible metallic conductor is applied by electrochemical methods or by sputtering. A particularly high precision of the turn-off or melting characteristic is achieved by photolithographic structuring of sputtered layers, wherein a low aluminum oxide substrate with low thermal conductivity serves as a base.

Die JP 20031173728 A offenbart ein Herstellungsverfahren für eine Chip-Schmelzsicherung in Dünnschichttechnologie, wobei auf einem Substrat 11 eine Schmelzsicherung 14 sowie eine Deckschicht 15 angeordnet wird. Die Schmelzsicherung 14 wird mittels Photolithographie strukturiert. Das Substrat 11 weist eine geringe Wärmeleitfähigkeit auf, um die durch den elektrischen Leiter 14 fließenden Strom verursachte Wärme im elektrischen Leiter 14 nicht abzuführen und dadurch ein Aufschmelzen des elektrischen Leiters 14 zu begünstigen. Der elektrische Leiter 14 steht in unmittelbaren Kontakt mit dem Substrat 11.The JP 20031173728 A discloses a manufacturing method for a chip fuse in thin-film technology, wherein a fuse 14 and a cover layer 15 are arranged on a substrate 11. The fuse 14 is patterned by photolithography. The substrate 11 has a low thermal conductivity, in order not to dissipate the heat caused by the electric conductor 14 current in the electrical conductor 14 and thereby promote a melting of the electrical conductor 14. The electrical conductor 14 is in direct contact with the substrate 11.

Die JP 2002/140975 A beschreibt eine Schmelzsicherung mit einem metallischen Leiter 14 aus Silber, der ebenfalls unmittelbar auf einem Substrat 11 mit geringer thermischer Leitfähigkeit angeordnet ist, wobei der metallische Leiter 14 galvanisch abgeschieden wird oder als Dickschicht ausgebildet ist.The JP 2002/140975 A describes a fuse with a metallic conductor 14 made of silver, which is also disposed directly on a substrate 11 with low thermal conductivity, wherein the metallic conductor 14 is electrodeposited or formed as a thick film.

Die JP 2003/151425 A offenbart eine Schmelzsicherung mit einem Glaskeramik-Substrat 11 mit einer geringen thermischen Leitfähigkeit und einem metallischen Leiter 14 in Dickschichttechnologie.The JP 2003/151425 A discloses a fuse with a glass-ceramic substrate 11 having a low thermal conductivity and a metallic conductor 14 in thick-film technology.

Die JP 2002/279883 A beschreibt ebenfalls eine Schmelzsicherung für einen Chip, bei der der aufschmelzbare Bereich 17 eines Leiters 15 durch eine aufwändige Laserbearbeitung hergestellt ist. Dies erfordert zusätzliche zeit- und kostenintensive Bearbeitungsschritte.The JP 2002/279883 A also describes a fuse for a chip, in which the fusible region 17 of a conductor 15 is produced by a complex laser processing. This requires additional time and cost intensive processing steps.

Die JP 20031234057 A offenbart einen Sicherungswiderstand mit einem Widerstand 30 auf einem Substrat 10 wobei zwischen dem Widerstand 30 und dem Substrat 10 eine weitere wärmespeichernde Schicht 42 vorgesehen ist, um die im Widerstand 30 anfallende Wärme zu speichern. Der aufschmelzbare Bereich wird ebenfalls durch Laserbearbeitung hergestellt.The JP 20031234057 A discloses a fuse resistor having a resistor 30 on a substrate 10, wherein between the resistor 30 and the substrate 10, a further heat-storing layer 42 is provided to store the heat generated in the resistor 30 heat. The fusible region is also produced by laser processing.

Die JP 08/102244 A beschreibt eine Schmelzsicherung 10 in Dickschichttechnologie mit einer Glas-Glasurschicht 2 mit einer niedrigen thermischen Leitfähigkeit wobei die Glasschicht 2 auf einem Keramiksubstrat 1 angeordnet ist und auf der Glasschicht 2 eine Schmelzsicherung 3 aufgebracht wird.The JP 08/102244 A describes a fuse 10 in thick film technology with a glass-glaze layer 2 with a low thermal conductivity wherein the glass layer 2 is disposed on a ceramic substrate 1 and on the glass layer 2, a fuse 3 is applied.

Die JP 10/050198 A offenbart eine weitere Schmelzsicherung in Dünnschichttechnologie mit einem aufwändigen Schichtaufbau, bei dem auf dem Leiter 3 und einer Glasschicht 5 eine weitere elastische Silikonschicht 6 ausgebildet ist.The JP 10/050198 A discloses a further fuse in thin-film technology with a complex layer structure, in which on the conductor 3 and a glass layer 5, a further elastic silicone layer 6 is formed.

Die DE 197 04 097 A1 beschreibt ein elektrisches Sicherungselement mit einem Schmelzleiter in Dickschichttechnologie und einem Träger wobei der Träger aus einem schlecht wärmeleitenden Material besteht, insbesondere aus einer Glaskeramik.The DE 197 04 097 A1 describes an electrical fuse element with a fusible link in thick film technology and a carrier wherein the carrier consists of a poor thermal conductivity material, in particular of a glass ceramic.

Die DE 695 12 519 T2 offenbart eine oberflächenmontierte Sicherungsvorrichtung, wobei ein Dünnschicht-Schmelzleiter auf einem Substrat angeordnet ist und das Substrat vorzugsweise ein FR-4-Epoxid oder ein Polyamid ist.The DE 695 12 519 T2 discloses a surface mounted fuse device wherein a thin film fusible conductor is disposed on a substrate and the substrate is preferably a FR-4 epoxy or a polyamide.

Bekannt sind also zum einen Verfahren zur Herstellung von Chipsicherungen in Dickschichttechnologie unter Verwendung von Spezialkeramiken oder auch Al2O3 Keramiken und einer thermisch isolierenden Zwischenschicht, zum anderen Chipsicherungen in Dünnschichttechnologie unter Verwendung von Spezialkeramiken oder anderer spezieller Trägermaterialien.Known are therefore on the one hand a method for the production of chip fuses in thick film technology using special ceramics or Al 2 O 3 ceramics and a thermally insulating intermediate layer, on the other hand, chip fuses in thin-film technology using special ceramics or other special support materials.

So beschreibt die JP 09 063 454 A eine Chip-Sicherung gemäß dem Oberbegriff des Anspruchs 1 mit einer Glasglasurschicht (ganzflächig) über dem Trägersubstrat. Eine inselförmige Ausbildung der Glasschicht wird nur für die zweite, über dem Schmelzleiter angebrachte Glasschicht vorgeschlagen. Als Slcherungsleiterschicht werden Gold (Au) und Silber (Ag) verwendet. Die Klemmelektroden bestehen aus Silber oder Silber-Palladium.That's how it describes JP 09 063 454 A a chip fuse according to the preamble of claim 1 with a glass glaze layer (over the entire surface) over the carrier substrate. An island-shaped formation of the glass layer is proposed only for the second, above the fusible conductor attached glass layer. The hole conductor layer used is gold (Au) and silver (Ag). The clamping electrodes are made of silver or silver-palladium.

Die JP 09 429 115 A beschreibt wiederum eine Chip Sicherung mit einer ganzflächigen Glasglasurschicht über dem Trägersubstrat. Als Sicherungsleiterschicht wird Aluminium vorgeschlagen. Die Klemmelektroden bestehen aus mindestens 3 Schichten auf Silberbasis.The JP 09 429 115 A again describes a chip fuse with a full-surface glass glaze layer over the carrier substrate. Aluminum is proposed as the fuse conductor layer. The clamping electrodes consist of at least 3 silver-based layers.

Die JP 10 050 198 A beschreibt ebenso eine Chip Sicherung mit einer ganzflächigen Glasglasurschicht über dem Trägersubstrat und einem welterem Aufbau entsprechend Patent D1 mit einer zusätzlichen Siliconabdeckung.The JP 10 050 198 A also describes a chip fuse with a full-surface glass glaze layer over the carrier substrate and a welterem Structure according to patent D1 with an additional silicone cover.

Die JP 09 153 328 beschreibt ebenso eine Chip Sicherung mit einer ganzflächigen Glasglasurschicht über dem Trägersubstrat entsprechend JP 09 063 454 A mit einer Aluminium Sicherungsleiterschicht und Silberkontakten.The JP 09 153 328 also describes a chip fuse with a full-surface glass glaze over the carrier substrate accordingly JP 09 063 454 A with an aluminum fuse conductor layer and silver contacts.

Die DE 101 64 240 A1 beschreibt eine Schaltschutzvorrichtung mit einer laminierten Kupfer oder Kupferiegierungsschicht, die um einen säulenförmigen Substratkörper herum ausgebildet ist. Im Absatz [0076] wird die Verwendung einer Cr-Haftschicht zwischen der Kupferschicht und des Keramikkörpers vorgeschlagen. Außerdem wird das Ausfüllen von zuvor strukturierten Rillen im metallischen Leiter mit organischen Materialien beschrieben, die die Rillen vor Kontaminationen mit Fremdmaterialien schützen sollen, wobei die organischen Füllstoffe eine niedrige thermische Leitfähigkeit aufweisen. Es handelt sich also um eine Ausfüllung von Rillen einer stromtragenden Metallisierungsschicht die direkt auf dem keramischen Trägesubstrat abgeschieden wurde.The DE 101 64 240 A1 describes a switching protection device having a laminated copper or copper alloy layer formed around a columnar substrate body. Paragraph [0076] proposes the use of a Cr adhesion layer between the copper layer and the ceramic body. It also describes filling previously patterned grooves in the metallic conductor with organic materials designed to protect the grooves from contamination with foreign materials, the organic fillers having low thermal conductivity. It is therefore a filling of grooves of a current-carrying metallization layer which has been deposited directly on the ceramic carrier substrate.

Die DE 691 25 307 T2 beschreibt eine Sicherungs-Tellbaugruppe mit einem Dünnschicht-Sicherungselement und einer Glaslsolierungsbeschichtung, die nur ein Mittelabschnitt des Substrates bedeckt sind und die mit Anschlussstellen-Anbringungsschnitten und Kunststoffverhüllung versehen ist.The DE 691 25 307 T2 describes a fuse Tellbaugruppe with a thin film fuse element and a Glaslsolierungsbeschichtung which are covered only a central portion of the substrate and which is provided with terminal attachment cuts and Kunststoffverhüllung.

Darstellung der Erfindung: Aufgabe, Lösung, VorteileDESCRIPTION OF THE INVENTION: Problem, Solution, Advantages

Es ist daher Aufgabe der Erfindung, eine gattungsgemäße Schmelzsicherung anzugeben, die kostengünstig und mit ausreichender Präzision herstellbar ist wobei ihre Schmelzcharakteristik genau definierbar sein soll. Des Weiteren soll ein Verfahren zur Herstellung der Schmelzsicherung angegeben werden.It is therefore an object of the invention to provide a generic fuse, which is inexpensive and can be produced with sufficient precision and their melting characteristics should be precisely defined. Furthermore, a method for producing the fuse is to be specified.

Diese Aufgaben werden durch die Merkmale der Ansprüche 1 bzw. 3 gelöstThese objects are achieved by the features of claims 1 and 3, respectively

Kerngedanke der Erfindung ist es, die Vorteile eines kostengünstigen Herstellungsprozesses für passive Bauelemente mit den Vorteilen einer Dünnschichttechnologie und der präzisen photolithographischen Strukturierung zu kombinieren, was durch die Verwendung einer thermisch isolierenden Zwischenschicht auf Al2O3 Keramik in Kombination mit der Dünnschichttechnologie und der photolithographischen Strukturierung realisiert wird.The core idea of the invention is to combine the advantages of a low-cost passive component manufacturing process with the advantages of thin-film technology and precise photolithographic patterning, through the use of a thermally insulating interlayer on Al 2 O 3 ceramics in combination with thin-film technology and photolithographic patterning is realized.

Der Kerngedanke der Erfindung besteht also darin, dass zwischen einem kostengünstigen Keramiksubstrat als Träger mit hoher thermischer Leitfähigkeit und dem eigentlichen aufschmelzbaren metallischen Leiter eine Zwischenschicht vorgesehen ist, die entweder durch ein kostengünstiges Verfahren, vorzugsweise im Inseldruckverfahren aufgebrachte niedrigschmelzende anorganische Glaspaste oder durch eine im Inseldruck aufgebrachte organische Schicht gebildet ist. Aufgrund der niedrigen thermischen Leitfähigkeit dieser Zwischenschicht wird die im metallischen Leiter durch den durch diesen hindurchfließenden Strom entstehende Wärme nicht nach unten hin durch das Trägersubstrat mit einer üblicherweise höheren thermischen Leitfähigkeit abgeführt, so dass bei einer definierten Stromstärke im Leiter dieser in gewünschter Weise aufschmilzt. Diese Zwischenschicht dient als thermischer Isolator. In bevorzugter Weise wird als Zwischenschicht eine niedrig schmelzende anorganische Glaspaste verwendet, die insbesondere im Siebdruckverfahren auf das Trägersubstrat aufgebracht wird. Dies bietet gegenüber anderen Substraten mit niedriger thermischer Leitfähigkeit einen wesentlichen Vorteil, da letztere praktisch nur als Sonderanfertigungen lieferbar bzw. herstellbar sind, wohingegen durch das Aufbringen von Glasinseln als thermisch isolierende Zwischenschicht jetzt preisgünstige Standardkeramiken genutzt werden können, wobei auch solche mit nur mäßiger Oberflächenbeschaffenheit (Dickschichtqualität) zum Einsatz kommen können. In einer alternativen Ausgestaltung ist die Zwischenschicht eine organische Zwischenschicht, die insbesondere im Inseldruck aufgebracht und nachfolgend in dem Fachmann bekannter Weise durch Wärmeeinwirkung in das Trägersubstrat eingebrannt bzw. ausgehärtet wird. Hierbei kann durch den einfach durchzuführenden Inseldruck ebenfalls eine beliebige Formgebung der Zwischenschicht erhalten, sowie die Verwendung von Al2O3 Keramiken als Trägermaterial genutzt werden.The core idea of the invention is thus that between a low-cost ceramic substrate as a carrier with high thermal conductivity and the actual fusible metallic conductor an intermediate layer is provided, which is formed either by a cost-effective method, preferably applied in the island printing process low-melting inorganic glass paste or by an applied in island printing organic layer. Due to the low thermal conductivity of this intermediate layer, the heat arising in the metallic conductor through the current flowing through it is not dissipated downwardly through the carrier substrate with a usually higher thermal conductivity, so that melts in a desired current in the conductor this in the desired manner. This intermediate layer serves as a thermal insulator. Preferably, a low-melting inorganic glass paste is used as the intermediate layer, which is applied in particular by screen printing on the carrier substrate. This offers a significant advantage over other substrates with low thermal conductivity, since the latter are practically only available as custom-made or produced, whereas by applying glass islands as a thermally insulating intermediate layer now inexpensive standard ceramics can be used, even those with only moderate surface finish ( Thick film quality) can be used. In an alternative embodiment, the intermediate layer is an organic intermediate layer, which is applied in particular in island printing and subsequently baked or cured in a manner known to those skilled in the art by the action of heat in the carrier substrate. In this case, any desired shaping of the intermediate layer can also be obtained by the simple island pressure, and the use of Al 2 O 3 ceramics as carrier material can be used.

Der Vorteil der Erfindung besteht darin, dass eine kostengünstige Standardkeramik, eine kostengünstig im Siebdruckverfahren herstellbare thermisch isolierende Zwischenschicht mit dem Vorteil der Dünnschichttechnik und der Photolithographischen Strukturierung kombiniert werden kann.The advantage of the invention is that a cost-effective standard ceramic, a thermally insulating intermediate layer which can be produced cost-effectively by screen printing can be combined with the advantage of thin-film technology and photolithographic structuring.

Hierdurch können hochpräzise und kostengünstige Schmelzsicherungen in miniaturisierter Ausführung zur Absicherung elektronischer Baugruppen vor Fehlströmen hergestellt werden.As a result, highly precise and cost-effective fuses in miniaturized version for securing electronic assemblies against fault currents can be produced.

In vorteilhafter Weise wird als Trägersubstrat für die Schmelzsicherung ein Aluminiumoxidsubstrat verwendet, das von praktisch allen Herstellern derartiger Keramiksubstrate preisgünstig und in beliebiger Form und Größe verfügbar ist und z. B. in der Massenproduktion der Widerstandshersteller Verwendung findet. Derartige Aluminiumoxid-Keramiksubstrate können bereits mit Vorkerbungen in Form der später aus dem Substrat herzustellenden Chips herstellerseitig versehen sein. Bei beiden vorstehend beschriebenen Ausgestaltungen werden die Zwischenschichten beispielsweise im Bereich der herstellerseitig vorgegebenen Vorkerbungen aufgebracht, um bei einem späteren Vereinzelungsprozess der Chips das Trägersubstrat in bekannter Weise ohne Beschädigung der Zwischenschichten durch Brechprozesse zu trennen.Advantageously, the carrier substrate used for the fuse an alumina substrate that is available from virtually all manufacturers of such ceramic substrates inexpensively and in any shape and size and z. B. is used in mass production of resistance manufacturers use. Such aluminum oxide ceramic substrates can already be provided by the manufacturer with notches in the form of the chips to be produced later from the substrate. In the case of both embodiments described above, the intermediate layers are applied, for example, in the region of the pre-bites given by the manufacturer, in order to separate the carrier substrate in a known manner without damaging the intermediate layers by breaking processes during a subsequent dicing process of the chips.

Um die Haftung des metallischen Leiters auf der Zwischenschicht zu verbessern kann unmittelbar auf der Zwischenschicht eine anorganische oder eine organische Haftvermittlerschicht im Sprühverfahren oder durch Sputtern aufgebracht sein.In order to improve the adhesion of the metallic conductor to the intermediate layer, an inorganic or an organic adhesion promoter layer may be applied directly on the intermediate layer by spraying or by sputtering.

Vorteilhafterweise ist der metallische Leiter durch eine niedrigohmige Metallschicht gebildet, um den Schmelzpunkt der Schmelzsicherung genau einstellen zu können.Advantageously, the metallic conductor is formed by a low-resistance metal layer in order to be able to set the melting point of the fuse accurately.

Erfindungsgemäß wird diese Metallschicht durch Sputtern auf die Zwischenschicht bzw. die Haftvermittlerschicht aufgebracht. Würde die gesputterte Metallschicht auf ein ganzflächig glasiertes Trägersubstrat aufgebracht, würde dies zu einer verminderten Haftung führen, so dass bei einem Vereinzelungsprozess mittels Brechen eine Delamination der Metallschicht im Vorkontaktbereich auftreten könnte. Durch das Aufbringen der Metallschicht auf eine thermisch isolierende Insel in Form einer Zwischenschicht mit niedriger thermischer Leitfähigkeit ist die gute Haftung der Metallschicht im Kontaktbereich auf der rauheren Aluminiumoxidkeramik gewährleistet, da durch diese Glasinseln im Bereich der Schmelzsicherung glatte Oberflächen erzeugt werden, wodurch die photolithographische Strukturierung der Schmelzsicherung besonders präzise erfolgen kann, da im Gegensatz hierzu Trägersubstrate aus thermisch schlecht leitenden Keramiken höhere Oberflächenrauhigkeiten aufweisen, die für eine präzise photolithographische Strukturierung ungünstig sind.According to the invention, this metal layer is applied by sputtering to the intermediate layer or the adhesion promoter layer. If the sputtered metal layer were applied to a carrier substrate which had been glazed over the whole area, this would lead to a reduced adhesion, so that delamination of the metal layer in the pre-contact region could occur in a singulation process by means of breaking. By applying the metal layer on a thermally insulating island in the form of an intermediate layer with low thermal conductivity ensures the good adhesion of the metal layer in the contact area on the rougher aluminum oxide, as smooth surfaces are generated by these glass islands in the field of fuse, whereby the photolithographic structuring of the fuse particularly precise can be done because in contrast carrier substrates of thermally poorly conducting ceramics have higher surface roughness, which are unfavorable for a precise photolithographic patterning.

Zur Strukturierung des metallischen Leiters in Form der gewünschten Schmelzsicherung ist vorgeschlagen, dass dies durch positive oder negative Lithographie erfolgt. Bei einem positiven Lithographieprozess wird beispielsweise ganzflächig eine Metallschicht auf der darunter angeordneten Schicht abgeschieden, beispielsweise Kupfer, und anschließend die gewünschte Struktur photolithographisch in die Schicht geätzt. Bei einem negativen Lithographieprozess wird auf die darunter liegende Schicht, d. h. die Zwischenschicht oder die Haftvermittlerschicht, zuerst ein Photolack abgeschieden, beispielsweise aufgesprüht, und anschließend in gewünschter Weise photollthographisch strukturiert. Anschließend wird eine Metallschicht, beispielsweise ein gesputterter Kupferfilm, darauf abgeschieden und die verbleibenden Lackbereiche mit dem Metallfilm darauf abgelöst.For structuring the metallic conductor in the form of the desired fuse, it is proposed that this be done by positive or negative lithography. In a positive lithography process, for example, a metal layer is deposited over the whole area on the layer arranged thereunder, for example copper, and then the desired structure is photolithographically etched into the layer. In a negative lithography process is applied to the underlying layer, i. H. the intermediate layer or the adhesion promoter layer, first a photoresist is deposited, for example sprayed on, and then patterned in the desired manner by photolithography. Subsequently, a metal layer, for example a sputtered copper film, is deposited thereon and the remaining lacquer areas are removed thereon with the metal film.

Zum Schutz der Schmelzsicherung wird auf den metallischen Leiter oder vorzugsweise die gesamte Schmelzsicherung überdeckend eine oder mehrere Deckschichten aufgebracht, die u. a. auch durch eine anorganische Sperrschicht gebildet sein kann. Die organische Deckschicht ist insbesondere ein Polyamid, Polyimid oder ein Epoxid und kann auch mehrschichtig ausgeführt sein.In order to protect the fuse, one or more cover layers is applied to cover the metallic conductor or preferably the entire fuse, which may, inter alia, also be formed by an inorganic barrier layer. The organic cover layer is in particular a polyamide, polyimide or an epoxide and can also be configured as a multilayer.

Zur Kontaktierung der Schmelzsicherung werden die Endkontakte des metallischen Leiters durch galvanisches Abscheiden einer metallischen Barriereschicht, typischerweise aus Nickel, und der abschließenden lötfähigen oder bondfähigen Schicht, typischerweise aus Zinn oder Zinnlegierungen, erzeugt.For contacting the fuse, the end contacts of the metallic conductor are formed by electrodepositing a metallic barrier layer, typically nickel, and the final solderable or bondable layer, typically of tin or tin alloys.

Vorteilhafte Ausgestaltungen der Erfindung sind jeweils in den Unteransprüchen gekennzeichnet.Advantageous embodiments of the invention are each characterized in the subclaims.

Kurze Beschreibung der ZeichnungShort description of the drawing

Nachstehend wird die Erfindung anhand einer Zeichnung näher erläutert. Es zeigt:

  • Fig. 1: den Herstellungsprozess einer Schmelzsicherung in sechs Schritten.
The invention will be explained in more detail with reference to a drawing. It shows:
  • Fig. 1 : the manufacturing process of a fuse in six steps.

Bei dem in Figur 1 dargestellten Herstellungsprozess einer Schmelzsicherung 100 wird zuerst auf einem Trägersubstrat 10 (Schritt a)), vorzugsweise einer Aluminiumoxidkeramik, eine thermisch isolierende Zwischenschicht 11 in Inselform abgeschieden (Schritt b)). Auf diese Zwischenschicht 11 sowie das umgebende Trägersubstrat 10 wird eine Haftschicht 12 zur Verbesserung der Haftung des metallischen Leiters 13 auf dem Untergrund aufgebracht (Schritt c)). Anschließend wird der metallische Leiter 13 auf die Haftschicht 12 aufgebracht, beispielsweise eine Kupferschicht aufgesputtert und in gewünschter Weise photolithographisch strukturiert (Schritt d)).At the in FIG. 1 First, a manufacturing process of a fuse 100 is deposited on a carrier substrate 10 (step a)), preferably an alumina ceramic, a thermally insulating intermediate layer 11 in island form (step b)). An adhesion layer 12 for improving the adhesion of the metallic conductor 13 to the substrate is applied to this intermediate layer 11 and the surrounding carrier substrate 10 (step c)). Subsequently, the metallic conductor 13 is applied to the adhesion layer 12, for example sputtered on a copper layer and photolithographically structured in the desired manner (step d)).

Hierbei wird durch die Dicke und Breite des Stegs im mittleren Bereich des metallischen Leiters 13 die maximale Stromstärke vorgegeben bei deren Überschreiten dieser Steg aufschmilzt und somit andere elektronische Bauteile vor einer Beschädigung geschützt werden. Durch die thermisch isolierende Zwischenschicht wird der Wärmeübertrag in das Trägersubstrat 10 stark unterdrückt, so dass der Schmelzpunkt der Schmelzsicherung 100 präzise definierbar ist.Here, the maximum current is predetermined by the thickness and width of the web in the central region of the metallic conductor 13 at the crossing of this bridge melts and thus other electronic components are protected from damage. The heat transfer into the carrier substrate 10 is strongly suppressed by the thermally insulating intermediate layer, so that the melting point of the fuse 100 can be precisely defined.

Nachfolgend wird die Schmelzsicherung 100 bzw. der mittlere Bereich des metallischen Leiters 13 mit einer organischen Deckschicht 14, beispielsweise einem Polyamid oder einem Epoxid überzogen, um die Schmelzsicherung 100 gegen Beschädigungen zu schützen. Zur Kontaktierung werden die Endkontakte 15 des metallischen Leiters 13 galvanisiert, beispielsweise mit Nickel und Zinn.Subsequently, the fuse 100 or the middle region of the metallic conductor 13 is coated with an organic cover layer 14, for example a polyamide or an epoxy, in order to protect the fuse 100 against damage. For contacting the end contacts 15 of the metallic conductor 13 are galvanized, for example with nickel and tin.

BEZUGSZEICHENLISTELIST OF REFERENCE NUMBERS

100100
Schmelzsicherungfuse
1010
Trägersubstratcarrier substrate
1111
Zwischenschichtinterlayer
1212
Haftschichtadhesive layer
1313
metallischer Leitermetallic conductor
1414
Deckschichttopcoat
1515
Endkontaktend contact

Claims (4)

  1. A fuse (100) in chip design, which is on a carrier substrate (10) made of a ceramic, which is an aluminium oxide ceramic in thick-film quality or in thin-film quality, with a fusible metallic conductor (13) which is applied and structured by means of thin-film technology and which is provided with a cover layer (14), wherein between carrier substrate (10) and metallic conductor (13) an intermediate layer (11) having low thermal conductivity is arranged, the carrier substrate (10) is an Al2O3 ceramic with high thermal conductivity, and the fusible metallic conductor (13) is applied by sputteriing or vapour deposition methods and is structured by means of lithography technology,
    the metallic conductor (13) is formed by a low-resistance metal layer, namely by Cu, Au, Ag, Sn alloy or a low-resistance Cu, Au, Ag, Sn alloy, and the metal layer is sputtered on by the vacuum method or is vapour-deposited,
    the metallic conductor (13) is structured with a positive or negative lithography method,
    a cover layer (14) is formed on the metallic conductor (13) by an inorganic or organic layer, in particular by a polyamide, polyimide, polyamide imide or an epoxide and in particular is constructed having several layers,
    characterized in that
    the intermediate layer (11) is a low-melting-point inorganic glass paste, applied by the screen printing method, or is an organic intermediate layer (11) applied by island printing,
    end contacts (15) of the fuse (100) are formed by immersion or preferably by galvanic deposition, in particular of copper, nickel, tin and tin alloys, and an adhesive layer (12) is arranged on the intermediate layer (11),
    the metallic conductor (13) is applied onto the adhesive layer (12).
  2. The fuse according to Claim 1, characterized in that an inorganic barrier layer is formed between the cover layer (4) and the metallic conductor (13).
  3. A method for the production of a fuse (100) in chip design, consisting of a carrier substrate (10), an intermediate layer (11) with low thermal conductivity, an adhesive layer (12) which is arranged on the intermediate layer (11), and a fusible metallic conductor (13), which is applied and structured by means of thin-film technology and which is provided with a cover layer (14), wherein
    - the intermediate layer (11) is applied on the carrier substrate (10) of an Al2O3 ceramic in thick-film quality or thin-film quality with a high thermal conductivity,
    - the intermediate layer (11) is formed by a low-melting-point inorganic glass paste applied by the screen printing method or an organic intermediate layer (11) applied by island printing,
    - the metallic conductor (13) is applied onto the intermediate layer (11), wherein the metallic conductor (13) is applied onto the adhesive layer (12) and
    - the cover layer (14) is applied onto the metallic conductor (13),
    - the metallic conductor (13) is formed by a low-resistance metal layer, wherein the metal layer is sputtered on by the vacuum method or is vapour-deposited, and the metal layer is formed by Cu, Au, Ag, Sn alloy or a low-resistance Cu, Au, Ag, Sn alloy,
    - the metallic conductor (13) is structured by a positive or negative lithography process,
    - the cover layer (14) is formed by an inorganic or organic layer, in particular by a polyamide, polyimide, polyamide imide or an epoxide and may also be constructed having several layers, and
    - end contacts (15) of the fuse (100) are formed by immersion or preferably by galvanic deposition, in particular of copper, nickel, tin or tin alloys.
  4. The method according to Claim 3, characterized in that an inorganic barrier layer is formed between the cover layer (14) and the metallic conductor (13).
EP05776175A 2004-07-08 2005-06-27 Safety fuse for a chip Active EP1766648B1 (en)

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DE102004033251A DE102004033251B3 (en) 2004-07-08 2004-07-08 Fuse for a chip
PCT/EP2005/006894 WO2006005435A1 (en) 2004-07-08 2005-06-27 Safety fuse for a chip

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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004033251B3 (en) 2004-07-08 2006-03-09 Vishay Bccomponents Beyschlag Gmbh Fuse for a chip
TWI323906B (en) * 2007-02-14 2010-04-21 Besdon Technology Corp Chip-type fuse and method of manufacturing the same
DE102007014334A1 (en) * 2007-03-26 2008-10-02 Robert Bosch Gmbh Fusible alloy element, thermal fuse with a fusible alloy element and method for producing a thermal fuse
US20090009281A1 (en) * 2007-07-06 2009-01-08 Cyntec Company Fuse element and manufacturing method thereof
JP4510858B2 (en) * 2007-08-08 2010-07-28 釜屋電機株式会社 Chip fuse and manufacturing method thereof
JP5287154B2 (en) * 2007-11-08 2013-09-11 パナソニック株式会社 Circuit protection element and manufacturing method thereof
US9190235B2 (en) * 2007-12-29 2015-11-17 Cooper Technologies Company Manufacturability of SMD and through-hole fuses using laser process
WO2010048782A1 (en) * 2008-10-28 2010-05-06 南京萨特科技发展有限公司 Chip type fuse and its manufacturing method
CN102891051B (en) * 2011-07-22 2017-04-12 阿提瓦公司 Side-by-side fuse component and battery array with same
CN107492473B (en) * 2017-08-17 2019-01-04 中国振华集团云科电子有限公司 The processing method on chip fuse barrier layer
US11636993B2 (en) 2019-09-06 2023-04-25 Eaton Intelligent Power Limited Fabrication of printed fuse

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3368919A (en) * 1964-07-29 1968-02-13 Sylvania Electric Prod Composite protective coat for thin film devices
US3887893A (en) * 1973-09-24 1975-06-03 Allen Bradley Co Fusible resistor
US4246563A (en) * 1977-05-28 1981-01-20 Aktieselkabet Laur. Knudsen Nordisk Electricitets Electric safety fuse
JPS5915394B2 (en) * 1978-08-31 1984-04-09 富士通株式会社 Thick film fine pattern generation method
JPS57138961A (en) * 1981-02-23 1982-08-27 Fujitsu Ltd Crossover formation for thermal head
US4685203A (en) * 1983-09-13 1987-08-11 Mitsubishi Denki Kabushiki Kaisha Hybrid integrated circuit substrate and method of manufacturing the same
US4626818A (en) * 1983-11-28 1986-12-02 Centralab, Inc. Device for programmable thick film networks
US4754371A (en) * 1984-04-27 1988-06-28 Nec Corporation Large scale integrated circuit package
US4873506A (en) * 1988-03-09 1989-10-10 Cooper Industries, Inc. Metallo-organic film fractional ampere fuses and method of making
JP2772001B2 (en) * 1988-11-28 1998-07-02 株式会社日立製作所 Semiconductor device
JPH02263445A (en) * 1988-12-23 1990-10-26 Toshiba Corp Aluminum nitride substrate and semiconductor using same
US5097246A (en) 1990-04-16 1992-03-17 Cooper Industries, Inc. Low amperage microfuse
US5166656A (en) * 1992-02-28 1992-11-24 Avx Corporation Thin film surface mount fuses
DE4329696C2 (en) * 1993-09-02 1995-07-06 Siemens Ag Multichip module with SMD-compatible connection elements that can be surface-mounted on printed circuit boards
US5363082A (en) * 1993-10-27 1994-11-08 Rapid Development Services, Inc. Flip chip microfuse
US5432378A (en) * 1993-12-15 1995-07-11 Cooper Industries, Inc. Subminiature surface mounted circuit protector
US5453726A (en) * 1993-12-29 1995-09-26 Aem (Holdings), Inc. High reliability thick film surface mount fuse assembly
US5552757A (en) * 1994-05-27 1996-09-03 Littelfuse, Inc. Surface-mounted fuse device
US5712610C1 (en) * 1994-08-19 2002-06-25 Sony Chemicals Corp Protective device
JPH08102244A (en) * 1994-09-29 1996-04-16 Kyocera Corp Chip fuse
JP2706625B2 (en) * 1994-10-03 1998-01-28 エス・オー・シー株式会社 Micro chip fuse
US5929741A (en) * 1994-11-30 1999-07-27 Hitachi Chemical Company, Ltd. Current protector
JPH0963454A (en) * 1995-08-29 1997-03-07 Kyocera Corp Chip fuse
JPH09129115A (en) * 1995-10-30 1997-05-16 Kyocera Corp Chip fuse
JPH09153328A (en) 1995-11-30 1997-06-10 Kyocera Corp Chip fuse
US5699032A (en) * 1996-06-07 1997-12-16 Littelfuse, Inc. Surface-mount fuse having a substrate with surfaces and a metal strip attached to the substrate using layer of adhesive material
US5977860A (en) * 1996-06-07 1999-11-02 Littelfuse, Inc. Surface-mount fuse and the manufacture thereof
JPH1050198A (en) * 1996-07-30 1998-02-20 Kyocera Corp Chip fuse element
DE19704097A1 (en) * 1997-02-04 1998-08-06 Wickmann Werke Gmbh Electrical fuse element
US5914649A (en) * 1997-03-28 1999-06-22 Hitachi Chemical Company, Ltd. Chip fuse and process for production thereof
DE19738575A1 (en) * 1997-09-04 1999-06-10 Wickmann Werke Gmbh Electrical fuse element
US6610440B1 (en) * 1998-03-10 2003-08-26 Bipolar Technologies, Inc Microscopic batteries for MEMS systems
US6002322A (en) * 1998-05-05 1999-12-14 Littelfuse, Inc. Chip protector surface-mounted fuse device
JP4396787B2 (en) * 1998-06-11 2010-01-13 内橋エステック株式会社 Thin temperature fuse and method of manufacturing thin temperature fuse
US6034589A (en) * 1998-12-17 2000-03-07 Aem, Inc. Multi-layer and multi-element monolithic surface mount fuse and method of making the same
US6078245A (en) * 1998-12-17 2000-06-20 Littelfuse, Inc. Containment of tin diffusion bar
JP3640146B2 (en) * 1999-03-31 2005-04-20 ソニーケミカル株式会社 Protective element
JP2000306477A (en) * 1999-04-16 2000-11-02 Sony Chem Corp Protective element
JP2001052593A (en) * 1999-08-09 2001-02-23 Daito Tsushinki Kk Fuse and its manufacture
JP2001325868A (en) * 2000-05-17 2001-11-22 Sony Chem Corp Protective element
JP2001325869A (en) * 2000-05-17 2001-11-22 Sony Chem Corp Protective element
JP4666427B2 (en) * 2000-11-10 2011-04-06 東京エレクトロン株式会社 Quartz window and heat treatment equipment
JP2002140975A (en) * 2000-11-01 2002-05-17 Koa Corp Fuse element and its manufacturing method
TW541556B (en) * 2000-12-27 2003-07-11 Matsushita Electric Ind Co Ltd Circuit protector
JP2002279883A (en) * 2001-03-19 2002-09-27 Koa Corp Chip type fuse resistor and manufacturing method of same
US7489229B2 (en) * 2001-06-11 2009-02-10 Wickmann-Werke Gmbh Fuse component
JP4204029B2 (en) * 2001-11-30 2009-01-07 ローム株式会社 Chip resistor
JP2003173728A (en) * 2001-12-06 2003-06-20 Koa Corp Manufacturing method of chip current fuse
US7436284B2 (en) * 2002-01-10 2008-10-14 Cooper Technologies Company Low resistance polymer matrix fuse apparatus and method
US7385475B2 (en) * 2002-01-10 2008-06-10 Cooper Technologies Company Low resistance polymer matrix fuse apparatus and method
US6891266B2 (en) * 2002-02-14 2005-05-10 Mia-Com RF transition for an area array package
JP4110967B2 (en) * 2002-12-27 2008-07-02 ソニーケミカル&インフォメーションデバイス株式会社 Protective element
JP2004214033A (en) * 2002-12-27 2004-07-29 Sony Chem Corp Protection element
JP2004265618A (en) * 2003-02-05 2004-09-24 Sony Chem Corp Protection element
JP2003234057A (en) * 2003-03-10 2003-08-22 Koa Corp Fuse resistor and its manufacturing method
US8680443B2 (en) * 2004-01-06 2014-03-25 Watlow Electric Manufacturing Company Combined material layering technologies for electric heaters
DE102004033251B3 (en) 2004-07-08 2006-03-09 Vishay Bccomponents Beyschlag Gmbh Fuse for a chip
US8976001B2 (en) * 2010-11-08 2015-03-10 Cyntec Co., Ltd. Protective device

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JP2008505466A (en) 2008-02-21
KR20070038143A (en) 2007-04-09
WO2006005435A1 (en) 2006-01-19
US20160372293A1 (en) 2016-12-22
US20080303626A1 (en) 2008-12-11
CN101010768B (en) 2011-03-30
ATE462194T1 (en) 2010-04-15
TWI413146B (en) 2013-10-21
DE502005009279D1 (en) 2010-05-06
KR101128250B1 (en) 2012-03-23
US10354826B2 (en) 2019-07-16
US9368308B2 (en) 2016-06-14
DE102004033251B3 (en) 2006-03-09
TW200612453A (en) 2006-04-16
EP1766648A1 (en) 2007-03-28
CN101010768A (en) 2007-08-01

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