EP1759393B1 - Concurrent programming of non-volatile memory - Google Patents

Concurrent programming of non-volatile memory Download PDF

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Publication number
EP1759393B1
EP1759393B1 EP05755315A EP05755315A EP1759393B1 EP 1759393 B1 EP1759393 B1 EP 1759393B1 EP 05755315 A EP05755315 A EP 05755315A EP 05755315 A EP05755315 A EP 05755315A EP 1759393 B1 EP1759393 B1 EP 1759393B1
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Prior art keywords
volatile storage
storage element
programming
voltage
condition
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German (de)
English (en)
French (fr)
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EP1759393A1 (en
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Daniel C. Guterman
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SanDisk Corp
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SanDisk Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Definitions

  • the present invention relates to technology for programming non-volatile memory.
  • Non-volatile semiconductor memory devices have become more popular for use in various electronic devices.
  • non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices.
  • Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
  • Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate.
  • the floating gate is positioned between source and drain regions.
  • a control gate is provided over and insulated from the floating gate.
  • the threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
  • Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state).
  • an EEPROM or flash memory device such as a NAND flash memory device
  • typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. More information about programming can be found in U.S.
  • Patent Application 10/379,608 ( US 6,859,397 ), titled “Self Boosting Technique, " filed on March 5, 2003; and in U.S. Patent Application 10/629, 068 ( US 6,917,542 ), titled “Detecting Over Programmed Memory,” filed on July 29, 2003.
  • a multi-state flash memory, cell is implemented by identifying multiple, distinct allowed programmed threshold voltage ranges separated by forbidden voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits.
  • the program voltage applied to the control gate is applied as a series of pulses.
  • the magnitude of the pulses is increased with each successive pulse by a predetermined step size (e.g. 0.2v, 0.4v, or other).
  • verify operations are carried out.
  • the number of programmable states increase, the number of verify operations increases and more time is needed.
  • One means for reducing the time burden of verifying is to use a more efficient verify process, such as the process that is disclosed in U.S. Patent Application Serial No. 10/314,055 ( US 7,073,103 ), "Smart Verify for Multi-State Memories," filed December 5, 2002.
  • U.S. Patent Application Serial No. 10/314,055 US 7,073,103
  • Smart Verify for Multi-State Memories filed December 5, 2002.
  • US 6,529,410 describes a method of programming in which memory cells of a NAND array structure are programmed simultaneously.
  • the present invention pertains to technology for-reducing the time needed to program non-volatile memory.
  • the first program condition can be different than the second program condition.
  • the first non-volatile storage element and the second non-volatile storage element are part of a group of non-volatile storage elements associated with a common source/drain control line.
  • the first non-volatile storage element is programmed using the first program condition and the second non-volatile storage element is programmed using said second program condition.
  • One example implementation includes applying a first value to a bit line, boosting word lines associated with the bit line to create a first condition based on the first value and cutting off a boundary non-volatile storage element associated with the bit line to maintain the first condition for a particular non-volatile storage element associated with the bit line.
  • a second value is applied to the bit line and at least a subset of the word lines associated with the bit line are boosted to create a second condition for a different non-volatile storage element.
  • the first condition and the second condition exist during overlapping times. Both non-volatile storage elements are programmed based on the associated conditions.
  • Various embodiments of the present invention include programming two or more non-volatile storage elements.
  • the present invention can be used to program an array of flash memory devices (or other types of non-volatile storage elements).
  • One embodiment utilizes NAND flash memory.
  • the programming of the two or more non-volatile storage elements is performed by or at the direction of a control circuit.
  • the components of the control circuit may differ based on the particular application.
  • a control circuit may include any one of the following components or any combination of two or more of the following components: controller, command circuits, state machine, row control, column control, source control, p-well or n-well control, or other circuits that perform similar functionality.
  • Figure 1 is a top view of a NAND string.
  • Figure 2 is an equivalent circuit diagram of the NAND string.
  • Figure 3 is a cross sectional view of the NAND string.
  • Figure 4 is a block diagram of one embodiment of a non-volatile memory system in which the various aspects of the present invention are implemented.
  • Figure 5 illustrates an example of an organization of a memory array.
  • Figure 6 shows threshold voltage distributions for a multi-state non-volatile memory device.
  • Figure 7 depicts a programming voltage signal, which includes a series of programming pulses with magnitudes increasing over time.
  • Figure 8 depicts three of the programming pulses from the signal of Figure 7 , and the verification pulses between the programming pulses.
  • Figure 9 depicts a NAND string.
  • Figure 10 is a flow chart describing one embodiment of a process for programming flash memory.
  • Figure 11 is a flow chart describing one embodiment of a process for establishing program conditions.
  • Figure 12 is a timing diagram describing the behavior of various signals during the program process.
  • Figure 13 is a flow chart describing one embodiment of a process for establishing program conditions.
  • Figure 14 is a flow chart describing one embodiment of a process for verifying.
  • NAND flash memory structure which includes arranging multiple transistors in series between two select gates.
  • the transistors in series and the select gates are referred to as a NAND string.
  • Figure 1 is a top view showing one NAND string.
  • Figure 2 is an equivalent circuit thereof.
  • the NAND string depicted in Figures 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122.
  • Select gate 120 connects the NAND string to bit line 126.
  • Each of the channels for the transistors on the NAND string are effected by the bit line 126.
  • Select gate 122 connects the NAND string to source line 128.
  • Select gate 120 is controlled by the applying appropriate voltages to control gate 120CG.
  • Select gate 122 is controlled by applying the appropriate voltages to control gate 122CG.
  • Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate.
  • Transistor 100 has control gate 100CG and floating gate 100FG.
  • Transistor 102 includes control gate 102CG and floating gate 102FG.
  • Transistor 104 includes control gate 104CG and floating gate 104FG.
  • Transistor 106 includes a control gate 106CG and floating gate 106FG.
  • Control gate 100CG is connected to word line WL3
  • control gate 102CG is connected to word line WL2
  • control gate 104CG is connected to word line WL1
  • control gate 106CG is connected to word line WL0.
  • transistors 100, 102, 104 and 106 are each memory cells. In other embodiments, the memory cells may include multiple transistors or may be different than that depicted in Figs 1 and 2 .
  • Select gate 120 is connected to select line SGD.
  • Select gate 128 is connected to select line SGS.
  • FIG. 3 provides a cross-sectional view of the NAND string described above.
  • the transistors of the NAND string are formed in p-well region 140.
  • Each transistor includes a stacked gate structure that consists of the control gate (100CG, 102CG, 104CG and 106CG) and a floating gate (100FG, 102FG, 104FG and 106FG).
  • the floating gates are formed on the surface of the p-well on top of an oxide or other dielectric film.
  • the control gate is above the floating gate, with an inter-polysilicon dielectric layer separating the control gate and floating gate.
  • the control gates of the memory cells (100, 102, 104, 106) form the word lines.
  • N+ doped layers 130, 132, 134, 136 and 138 are shared between neighboring cells, whereby the cells are connected to one another in series to form a NAND string. These N+ doped layers form the source and drain of each of the cells.
  • N+ doped layer 130 serves as the drain of transistor 122 and the source for transistor of 106
  • N+ doped layer 132 serves as the drain for transistor 106 and the source for transistor 104
  • N+ doped region 134 serves as the drain for transistor 104 and the source for transistor 102
  • N+ doped region 136 serves as the drain for transistor 102 and the source for transistor 100
  • N+ doped layer 138 serves as the drain for transistor 100 and the source for transistor 120.
  • N+ doped layer 126 connects to the bit line for the NAND string
  • N+ doped layer 128 connects to a common source line for multiple NAND strings.
  • Figures 1-3 show four memory cells in the NAND string, the use of four transistors is only provided as an example.
  • a NAND string can have less than four memory cells or more than four memory cells.
  • some NAND strings will include 8 memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
  • Each memory cell can store data represented in analog or digital form.
  • the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data "1" and "0.”
  • the voltage threshold is negative after the memory cell is erased, and defined as logic "1.”
  • the threshold voltage after a program operation is positive and defined as logic "0.”
  • the memory cell will turn on to indicate logic one is being stored.
  • the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on, which indicates that logic zero is stored.
  • a memory cell can also store multiple states, for example, thereby storing multiple bits of digital data.
  • the range of possible threshold voltages is divided into the number of states. For example, if four states are used, there will be four threshold voltage ranges assigned to the data values "11", “10", “01”, and "00.” In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as "11". Positive threshold voltages are used for the states of "10", “01” ", and "00.”
  • Fig. 4 is a block diagram of one embodiment of a flash memory system that can be used to implement the present invention.
  • Memory cell array 302 is controlled by column control circuit 304, row control circuit 306, c-source control circuit 310 and p-well control circuit 308.
  • Column control circuit 304 is connected to the bit lines of memory cell array 302 for reading data stored in the memory cells, for determining a state of the memory cells during a program operation, and for controlling potential levels of the bit lines to promote the programming or to inhibit the programming.
  • Row control circuit 306 is connected to the word lines to select one of the word lines, to apply read voltages, to apply program voltages and to apply an erase voltage.
  • C-source control circuit 310 controls a common source line (labeled as "C-source” in Fig. 5 ) connected to the memory cells.
  • P-well control circuit 308 controls the p-well voltage.
  • the data stored in the memory cells are read out by the column control circuit 304 and are output to external I/O lines via data input/output buffer 312.
  • Program data to be stored in the memory cells are input to the data input/output buffer 312 via the external I/O lines, and transferred to the column control circuit 304.
  • the external I/O lines are connected to controller 318.
  • Command data for controlling the flash memory device is input to controller 318.
  • the command data informs the flash memory of what operation is requested.
  • the input command is transferred to state machine 316, which controls column control circuit 304, row control circuit 306, c-source control 310, p-well control circuit 308 and data input/output buffer 312.
  • State machine 316 can also output status data of the flash memory such as READY/BUSY or PASS/FAIL.
  • Controller 318 is connected or connectable with a host system such as a personal computer, a digital camera, personal digital assistant, etc. Controller 318 communicates with the host in order to receive commands from the host, receive data from the host, provide data to the host and provide status information to the host. Controller 318 converts commands from the host into command signals that can be interpreted and executed by command circuits 314, which is in communication with state machine 316. Controller 318 typically contains buffer memory for the user data being written to or read from the memory array.
  • One exemplar memory system comprises one integrated circuit that includes controller 318, and one or more integrated circuit chips that each contain a memory array and associated control, input/output and state machine circuits.
  • the trend is to integrate the memory arrays and controller circuits of a system together on one or more integrated circuit chips.
  • the memory system may be embedded as part of the host system, or may be included in a memory card (or other package) that is removably inserted into the host systems.
  • a removable card may include the entire memory system (e.g. including the controller) or just the memory array(s) and associated peripheral circuits (with the Controller or control function being embedded in the host).
  • the controller can be embedded in the host or included within a removable memory system.
  • some of the components of Figure 4 can be combined. In various designs, one or more of the components of Fig 4 , other than memory cell array 302, can be thought of as a control circuit.
  • FIG. 5 an example structure of memory cell array 302 is described.
  • a NAND flash EEPROM is described that is partitioned into 1,024 blocks.
  • the data stored in each block is simultaneously erased.
  • the block is the minimum unit of cells that are simultaneously erased.
  • the bit lines are also divided into even bit lines (BLe) and odd bit lines (BLo).
  • Figure 5 shows four memory cells connected in series to form a NAND string. Although four cells are shown to be included in each NAND string, more or less than four memory cells can be used.
  • One terminal of the NAND string is connected to corresponding bit line via a first select transistor SGD, and another terminal is connected to c-source via a second select transistor SGS.
  • 4,256 memory cells are simultaneously selected.
  • the memory cells selected have the same word line and the same kind of bit line (e.g. even bit lines or odd bit lines). Therefore, 532 bytes of data can be read or programmed simultaneously. These 532 bytes of data that are simultaneously read or programmed form a logical page. Therefore, one block can store at least eight logical pages (four word lines, each with odd and even pages). When each memory cell stores two bits of data (e.g. a multi-level cell), one block stores 16 logical pages. Other sized blocks and pages can also be used with the present invention. Additionally, architectures other than that of Figs. 4 and 5 can also be used to implement the present invention.
  • Memory cells are erased in one embodiment by raising the p-well to an erase voltage (e.g. 20 volts) and grounding the word lines of a selected block while the source and bit lines are floating. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and c-source are also raised to 20V. A strong electric field is thus applied to the tunnel oxide layers of selected memory cells and the data of the selected memory cells are erased as electrons of the floating gates are emitted to the substrate side. As electrons are transferred from the floating gate to the p-well region, the threshold voltage of a selected cell becomes negative. Erasing can be performed on the entire memory array, separate blocks, or another unit of cells.
  • an erase voltage e.g. 20 volts
  • the select gates (SGD and SGS) of a selected block are raised to one or more select voltages and the unselected word lines (e.g., WL0, WL1 and WL3) of the selected block are raised to a read pass voltage (e.g. 4.5 volts) to make the transistors operate as pass gates.
  • the selected word line of the selected block (e.g. WL2) is connected to a reference voltage, a level of which is specified for each read and verify operation in order to determine whether a threshold voltage of the concerned memory cell has reached such level. For example, in a read operation for a two level memory cell, the selected word line WL2 may be grounded, so that it is detected whether the threshold voltage is higher than 0v.
  • the selected word line WL2 is connected to 2.4v, for example, so that as the programming progresses it is verified whether the threshold voltage has reached at least 2.4v.
  • the source and p-well are at zero volts during verify.
  • the selected bit lines (BLe) are precharged to a level of, for example, 0.7v. If the threshold voltage is higher than the read or verify level on the word line, the potential level of the concerned bit line (BLe) maintains the high level because of the non-conductive memory cell. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the concerned bit line (BLe) decreases to a low level, for example less than 0.5V, because of the conductive memory cell. The state of the memory cell is detected by a sense amplifier that is connected to the bit line.
  • Figure 6 illustrates threshold voltage distributions for memory cells storing two bits of data (e.g., four data states).
  • distribution 460 represents a distribution of threshold voltages of cells that are in the erased state (e.g., storing "11"), having negative threshold voltage levels.
  • Distribution 462 represents a distribution of threshold voltages of cells that are storing "10.”
  • Distribution 464 represents a distribution of threshold voltages of memory cells storing "00.”
  • Distribution 466 represents a distribution of threshold voltages of cells that are storing "01.”
  • each of the distributions can correspond to different data states than described above. In some implementations, these data values (e.g.
  • a memory cell in the erased state can be programmed to any of the program states (distributions 462, 464 or 466).
  • memory cells in the erased state are programmed according to a two-step methodology. In this two-step methodology, each of the bits stored in a data state correspond to different logical pages. That is, each bit stored in a memory cell has a different logical page address, pertaining to a lower logical page and an upper logical page. For example, in state "10,” the "0" is stored for the lower logical page and the "1" is stored for the upper logical page.
  • the cell's threshold voltage level is set according to the bit to be programmed into the lower logical page. If that bit is a logic "1,” the threshold voltage is not changed since it is in the appropriate state (e.g. distribution 460) as a result of having been earlier erased. However, if the bit is to be programmed to a logic "0,” the threshold level of the cell is increased to be within the threshold voltage distribution 462.
  • the memory cell's threshold voltage level is set according to the bit being programmed into the upper logical page. If the upper logical page bit is to be logic "1,” then no further programming occurs since the cell is in one of the states corresponding to the threshold voltage distribution 460 or 462, both of which carry an upper page bit of "1.” If the upper logical page bit is to be logic "0" and the first step resulted in the cell remaining in the erased state corresponding to threshold 460, then the second step of the programming process includes raising the threshold voltage to be within threshold distribution 466.
  • the second step of the programming process includes raising the threshold voltage to be within threshold voltage distribution 464.
  • the two step process is just one example of a methodology for programming multi-state memory. Many other methodologies, including a one step process or more than two steps can be used.
  • Fig. 6 shows four states (two bits), the present invention can also be used with other multi-state structures including those that include eight states, sixteen states, thirty-two states, and others.
  • memory cells that use an erased state and only one programmed state would only use two threshold voltage distributions.
  • threshold voltage distribution 460 could be used to represent the erased state and threshold voltage distribution 462 could be used to represent the programmed state.
  • Other state assignments can also be used with the present invention.
  • a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised to one of the threshold voltage distribution described above.
  • the program voltage applied to the control gate is applied as a series of pulses. In one embodiment, the magnitude of the pulses is increased with each successive pulse by a predetermined step size (e.g. 0.4v, 0.2v, or others).
  • Figure 7 shows a program voltage signal Vpgm applied to the control gates of flash memory cells.
  • verify operations are carried out. That is, the programming level of each cell of a group of cells being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which it is being programmed.
  • the memory cells will perform a verification step for each state to determine which state the memory cell is within.
  • a multi-state memory cell capable of storing data in four states may need to perform verify operations for three compare points.
  • Figure 8 shows three programming pulses 10a, 10b and 10c (each of which are also depicted in Fig. 7 ). Between the programming pulses are three verify pulses in order to perform three verify operations. Based on the three verify operations, the system can determine whether or not the threshold compare point of the data state associated with each memory cell of the population of memory cells being concurrently programmed has been reached.. Note that one of the verify pulses is at 0 volts.
  • the present invention relates to technology for reducing the overall time needed to program a given amount of data into a non-volatile memory.
  • One embodiment provides for faster overall programming by concurrently programming multiple pages within a single erasable block, thereby increasing write performance without increasing erase block size.
  • multiple memory cells on the same NAND string can be programmed concurrently.
  • various data conditional channel programming potentials are established in spaced apart memory cells within the NAND string, using intervening memory cells (referred to as boundary memory cells) as isolation there-between. Setting up the various internal potentials can be accomplished by a sequential data load process followed by an isolation (voltage trapping) operation.
  • the data load process essentially includes causing channels of addressed memory cells selected for programming to be at voltage potentials appropriate for programming and causing channels of memory cells not selected for programming to be at a voltage potential appropriate for inhibiting programming.
  • all the selected control gates e.g., the control gates for the addressed memory cells to be data conditionally programmed
  • their programming voltage e.g., a pulse that can have a magnitude up to -20v, in one embodiment
  • the magnitude of this programming and resulting threshold voltage shift depends both on the channel potential and on the relative storage strength (i.e. relative capacitance) of the underlying channel and source/drain reservoir.
  • the underlying channel and source/drain reservoir is used to hold the boosting voltage for memory cells to be inhibited.
  • the underlying channel and source/drain reservoir is also used to absorb the voltage applied to word lines so that the channel remains at or near 0 volts (or other target potential) for memory cells being programmed. If the underlying channel and source/drain reservoir is too small (e.g. limited cathode programming charge scenario), then very little programming will occur, requiring many repetitions to get useful programming. Use of substantially higher voltages may help a bit, but is unattractive, putting more burden on the process and circuitry to support such higher voltage, increasing vulnerability to programming disturbs as well as degrading overall reliability.
  • every eight or every sixteenth memory cell can be concurrently programmed, with one of the intervening memory cells serving as isolation and the other intervening memory cells providing additional cathode reservoir capacitance for data conditional programming.
  • the number of memory cells programmed concurrently depends on the number of intervening memory cells providing additional cathode reservoir capacitance.
  • the number of intervening memory cells required in order to provide the necessary additional cathode reservoir capacitance depends on the device physics of the transistors and neighboring source/drain junctions. What is important is that there are enough intervening memory cells to provide the necessary additional cathode reservoir capacitance.
  • Figure 9 depicts a NAND string with thirty two memory cells: 502-564.
  • the NAND string also includes a source side select gate 500 and a drain side select gate 566. Connected to the control gate for the source side select gate 500 is a select signal SGS. Connected to the control gate for the drain side select gate 566 is a select signal SGD.
  • Each memory cell of Fig. 9 is connected to a word line.
  • Memory cell 502 is connected to word line WL0.
  • Memory cell 504 is connected to word line WL1.
  • Memory cell 506 is connected to word line WL2.
  • Memory cell 508 is connected to word line WL3.
  • Memory cell 510 is connected to word line WL4.
  • Memory cell 512 is connected to word line WL5.
  • Memory cell 514 is connected to word line WL6.
  • Memory cell 516 is connected to word line WL7. Memory cell 518 is connected to word line WL8. Memory cell 520 is connected to word line WL9. Memory cell 522 is connected to word line WL10. Memory cell 524 is connected to word line WL11. Memory cell 526 is connected to word line WL12. Memory cell 528 is connected to word line WL13. Memory cell 530 is connected to word line WL14. Memory cell 532 is connected to word line WL15. Memory cell 534 is connected to word line WL16. Memory cell 536 is connected to word line WL17. Memory cell 538 is connected to word line WL18. Memory cell 540 is connected to word line WL19. Memory cell 542 is connected to word line WL20. Memory cell 544 is connected to word line WL21.
  • Memory cell 546 is connected to word line WL22.
  • Memory cell 548 is connected to word line WL23.
  • Memory cell 550 is connected to word line WL24.
  • Memory cell 552 is connected to word line WL25.
  • Memory cell 554 is connected to word line WL26.
  • Memory cell 556 is connected to word line WL27.
  • Memory cell 558 is connected to word line WL28.
  • Memory cell 560 is connected to word line WL29.
  • Memory cell 562 is connected to word line WL30.
  • Memory cell 564 is connected to word line WL31.
  • the NAND string of Figure 9 will be used to explain the present invention. However, it is noted that the present invention may be used with other types of non-volatile storage.
  • the NAND string is divided into two regions.
  • a bottom region includes memory cells 502-532 and a top region includes memory cells 534-564.
  • one memory cell from the top region will be programmed concurrently with one memory cell from the bottom region.
  • the memory cell from the top region is 16 memory cells (total cells on NAND string divided by number of groups) away from the memory cell of the bottom regions. This means that memory cell 518 would be concurrently programmed with memory cell 550, memory cell 520 would be concurrently programmed with memory cell 552, etc.
  • Figure 10 is a flow chart describing one embodiment of a process for programming using the above described technology.
  • the portion of the memory to be programmed is selected. In one implementation, this can be one or more write units appropriate to the memory structure.
  • a write unit is referred to as a page. In other embodiments, other units and/or structures can also be used.
  • a pre-programming process is sometimes used wherein the addressed memory cells are given non-data dependent programming to level out storage element wear and provide a more uniform starting point for the subsequent erase.
  • an erase process is performed, as appropriate for the type of storage element being used.
  • a suitable smart erase process is described in U.S. Patent No. 5,095,344 .
  • Step 608 includes an optional soft programming process designed to put the threshold voltages of erased memory cells into a more uniform starting range for the actual write phase. In one embodiment, if any of the memory cells fail to verify during erase (or during soft programming), they can be mapped out of the logical address space. At this point the memory is ready for the data conditional programming phase.
  • step 610 the program voltage (Vpgm) is set to an initial value.
  • the waveform of Fig. 7 is used and step 610 includes setting the initial pulse.
  • a program counter (PC) is initialized to zero.
  • step 618 the various programming conditions are established.
  • a first programming condition for the bottom group and a second programming condition for the top group.
  • a programming condition is set up for each group.
  • the programming conditions are set up sequentially, starting with the group closest to the source line.
  • step 620 program pulses are concurrently applied. If two memory cells are being programmed concurrently, then two program pulses are applied: one program pulse is applied to the first memory cell being programmed and a second program pulse is concurrently applied to the second memory cell being programmed. If four memory cells are being programmed concurrently, then four program pulses are applied.
  • step 622 a verification process is performed to the memory cells being concurrently programmed.
  • a memory cell being programmed has attained its target threshold voltage condition, then it is inhibited from further programming during the remained of the data programming session.
  • Two memory cells that are being programmed concurrently may reach their target threshold voltage conditions at different times causing the memory cells to being inhibited at different times. As such, there may be a time when one of the memory cells is being programmed while the other memory cell is inhibited. Although such a situation can occur, the programming processes for the memory cells still overlap in time.
  • PC program counter
  • Figure 11 is a flow chart describing more details of one embodiment of the process for establishing program conditions (step 618 of Fig. 10 ).
  • the steps of Fig. 11 implement an example that divides a NAND string into two groups, as discussed above.
  • memory cells 518 and 550 of Fig. 9 are to be programmed concurrently. Note that although much of the examples pertain to the NAND string of Fig. 9 , in many implementations there will be many NAND strings being programmed simultaneously (e.g., as described above all even or all odd bit lines for a block may be programmed simultaneously).
  • bit lines connected to NAND strings of bottom group memory cells that are not to receive programming may receive an inhibit voltage, such as Vdd (e.g. ⁇ 2.5volts), and bit lines connected to NAND strings that are to receive programming may receive a voltage that enables programming (e.g., ⁇ 0 volts).
  • the bit line may receive an intermediate voltage (e.g., 1.5v or other values) that allows partial or reduced speed programming.
  • the intermediate voltage may be used to retard programming as part of a coarse/fine programming methodology.
  • the data applied to the bit lines in step 702 is for the memory cell in the bottom group.
  • the data is for memory cell 518.
  • one or more boosting voltages are applied to the word lines connected to the NAND string.
  • Those NAND strings receiving 0 volts at the bit line will dissipate the boosting voltage so that the channel region(s) for those NAND strings (including the bottom group) will be at or near 0 volts.
  • Those NAND strings receiving 2.5 volts at the bit line will have channel regions boosted, for example, to approximately 7.5 volts in the case of a 9 volt boosting voltage applied to the word lines.
  • V G is the voltage applied to the gate
  • V S is the voltage at the source
  • V TH is threshold voltage of the transistor.
  • the NAND transistor is symmetrical in that either side could be the source or the drain. The side with the lower voltage is typically referred to as the source. Thus, as voltages change, which side is the source and which side is the drain may also change. If V G is less than V TH than the transistor is cut off (no conduction between source and drain). If both V S and V D are increased relative to a given V G , so that V G -V S ⁇ V TH (remember that V D > Vs), then the device is also cut-off.
  • the to be inhibited bit lines are raised to Vdd (e.g., -2.5 volts).
  • Vdd e.g., -2.5 volts
  • the control gate of the drain side select gate is also at Vdd, causing the select gate to conduct.
  • the NAND strings on the unselected bit lines are then boosted by the boosting voltages applied to the word lines, which raises the voltage in the NAND string.
  • V G -V TH of the select gate
  • the select gate will cut-off, which isolates the NAND string from the bit line so that the voltage on the NAND string will not be dissipated into the bit line.
  • the voltage on the NAND string will then continue to increase so that it is higher then V G , but because the bit line potential is greater than V G -V TH , the select gate will remain cut-off and the voltage in the NAND string will continue to increase in concert with the increasing boosting voltage, for example, to about 7.5 volts.
  • the voltage in the channel is at this boosted potential (e.g., 7.5 volts)
  • the differential across the tunnel dielectric is not sufficient to allow for tunneling of electrons into the floating gate during the time of programming which could cause data state failure.
  • the boundary cells between the bottom group and the top group will be cut off for each for the NAND strings.
  • the boundary cells are the memory cells that are at the borders between the groups.
  • the boundary cell between the bottom group and the top group could be memory cell 532 or memory cell 534.
  • the boundary cell can be the memory cell that is midway between the two memory cells being programmed.
  • the boundary cell could be some other memory cell between the two memory cells being programmed.
  • the boundary cell is cut-off by apppling a voltage to its control gate that is less than the threshold voltage for that boundary cell. In one example, it may be possible for an erased memory cell to have a negative threshold voltage; therefore, negative voltage (e.g., -4 volts) is applied to the control gate of the boundary cells in order to insure cut-off the boundary cells.
  • the boundary cells are memory cells that also may need to be programmed. When it is time to program a memory cell that is a boundary cell, a different memory cell will become the boundary cell. For example, an adjacent memory cell or memory cell two or more away in the NAND string, and separating the memory cells being programmed, can become the new boundary cell.
  • step 708 the word lines for the top group are reset (e.g., to 0 volts).
  • step 710 data is applied to the bit lines for the top group.
  • step 712 one or more boosting voltages are applied to the word lines for the top group, while leaving the voltages already applied to those of the bottom group unchanged.
  • Those NAND strings receiving 0 volts at the bit line in step 710 will dissipate the boosting voltage applied to the top group in step 712 so that the channel region(s) are at or near 0 volts.
  • Those NAND strings receiving 2.5 volts at the bit line in step 710 will have channels (for the top group) boosted, for example, to approximately 7.5 volts for a 9 volt boosting voltage applied to the word lines.
  • the drain side select gate is optionally cut-off (e.g., by lowering its control gate voltage to 0 volts).
  • Figure 12 is a timing diagram that explains the behavior of seven signals (V BL , V SGD , V TUWL , V BUWL , V WLS , V WL24 and V WL15 ) operating according to the process of Figure 11 .
  • the signals of Fig. 12 implement both steps 618 and 620 of Fig. 10 .
  • Fig. 12 plots voltage versus time for various signals. To improve the explanation, numbers are assigned to the time units. In one example implementation, the time units may correspond to ⁇ sec. However, the invention is in no way limited to any particular timing and the time units are chosen for example purposes only.
  • the graph for the bit line voltage V BL shows four possible bit line voltage signals: A, B, C and D.
  • Signal A at approximately 0 volts until 14 time units, is applied to a bit line to allow a memory cell of the bottom group to be programmed.
  • Signal B at approximately 2.5 volts until 14 time units, is applied to a bit line to inhibit a memory cell of the bottom group.
  • Signal C at approximately 2.5 volts starting from 18 time units until optionally 33 time units, is applied to a bit line to inhibit a memory cell of the top group.
  • Signal D at approximately 0 volts starting from 18 time units and optionally held there until 33 time units, is applied to a bit line to allow a memory cell of the top group to be programmed.
  • bit line voltage V BL there are four possible forms of bit line voltage V BL : (1) signal A followed by signal C for programming the memory cell in the bottom group while inhibiting the memory cell in the top group, (2) signal A followed by signal D for programming the memory cell in the bottom group and programming the memory cell in the top group, (3) signal B followed by signal C for inhibiting the memory cell in the bottom group and inhibiting the memory cell in the top group, and (4) signal B followed by signal D for inhibiting the memory cell in the bottom group and programming the memory cell in the top group. Which of the four waveforms is applied to the bit line depends on the data to be stored and the current threshold voltage of the memory cells.
  • V SGD applied to the drain side select gate is raised to approximately 5 volts at time 0, as part of step 700.
  • V SGD is lowered to 2.5 volts.
  • time 20 it is raised to 5 volts, and then subsequently lowered to 2.5 volts at time 25.
  • V SGD is optionally lowered to 0 volts as per step 714 of Figure 11 .
  • V SGD can be left at the selected voltage level of 2.5 volts for the duration of that programming step (e.g., until time 58) and shut-off thereafter. In that case, the bit line voltage conditions V BL of signals C and D should also be maintained for the duration (e.g., to approximately time 58).
  • the period when V SGD is at 5 volts is used to pre-charge the bit line before each boosting phase.
  • the signal V TUWL is the voltage on the unselected word lines associated with the memory cells in the top group (Top Unselected Word Lines).
  • the signal V BUWL is the voltage on the unselected word lines connected to the memory cells in the bottom group (Bottom Unselected Word Lines).
  • the signal V WL8 is the voltage on the selected word line WL8 connected to the memory cell 518 of Fig. 9 selected for programming in the bottom group.
  • the signal V WL24 is the voltage on the selected word line WL24 connected to the memory cell 550 selected for programming in the top group.
  • the signal V WL15 is the voltage on the word line WL15, connected to the boundary memory cell 532.
  • V TUWL , V BUWL , V WL8 , V WL24 and V WL15 are raised to approximately 1.5 volts during the initial period when V SGD is at 5 volts in order to pre-charge the bit line/NAND string.
  • signals V TUWL , V BUWL , V WL8 , V WL24 and V WL15 are raised to approximately 9.5 volts (could also be 9 volts or other levels), as per step 704 of Fig. 11 , to provide a boosting voltage.
  • Those NAND strings receiving signal B on the bit line will be boosted and those NAND strings receiving signal A on the bit line will remain at or near 0 volts.
  • the boundary cell will be cut off (as per step 706), by lowering V WL15 to approximately - 4 volts.
  • the word lines for the top group are reset in step 708 by lowering signals V TUWL and V WL24 to 0 volts at time 15.
  • V BUWL remains at 9.5 volts until time 55.
  • V WL8 remains at 9.5 volts until the start of the programming, at time 35.
  • the channel of bottom group transistors will be at or near 0 volts for programming or at or near 7.5 volts for inhibiting programming.
  • Either signal C or signal D will be asserted on V BL as part of step 710.
  • the signals V TUWL and V WL24 are raised to approximately 1.5v at time 20 to allow NAND string pre-charging, and to approximately 9.5 volts at time 25 to provide boosting for the top group in step 712, and remain at 9.5 volts until time 55.
  • the control gate voltage V SGD for the drain side select transistor is optionally lowered to 0 volts at time 30 in order to cutoff the select transistor, as per step 714.
  • a second programming condition has established and is maintained for the top group of memory cells.
  • the channel of top group transistors will be at or near 0 volts for programming or at or near 7.5 volts for inhibiting programming.
  • the pre-charge condition associated with raising V SGD to 5v at time intervals 0 to 5 and 20 to 25, described in this example waveform, is optional. In other embodiments, no such pre-charge operation is used and V SGD is maintained at the 2.5v level during those time intervals.
  • the program pulses are applied to V WL8 and V WL24 .
  • the magnitude of the pulses can vary between 12 and 20 volts.
  • both V WL8 and V WL24 are raised at time 35 to the magnitude of the desired program pulse voltage and both memory cells 518 and 550 are concurrently programmed as dictated by the just described bit line related data programming setup.
  • the program pulse lasts until time 55, at which time V TUWL , V BUWL , V WL85 V WL24 and V WL15 (and optionally V BL and V SGD ) are all brought to 0 volts.
  • Figure 13 is a flow chart describing more details of another embodiment of the process for establishing program conditions (step 618 of Fig. 10 ).
  • the steps of Fig. 13 implement an example that divides a NAND string into four groups so that four memory cells on a common NAND string are concurrently programmed.
  • the first group corresponds to memory cells 502-516
  • the second group corresponds to memory cells 518-532
  • the third group corresponds to memory cells 534-548
  • the fourth group corresponds to memory cells 550-564.
  • One example set of the boundary cells includes memory cells 516, 532 and 548. Other memory cells can also serve as boundary cells.
  • step 750 of Figure 13 the drain side select gate 556 is turned on.
  • Vdd can be applied to the signal SGD.
  • step 702 data is applied to the bit lines.
  • the data applied to the bit lines in step 752 is for the memory cell in the first group that is being programmed.
  • the data is for memory cell 508.
  • step 754 one or more boosting voltages are applied to the word lines connected to the NAND string.
  • step 756 the boundary cells between the first group and the second group will be cut off.
  • step 758 the word lines for the groups not cut off (e.g., groups 2-4) are reset. Group one word lines remain at the boosting voltage.
  • step 760 data for the second group is applied to the bit lines.
  • one or more boosting voltages are applied to the word lines for the groups not cut-off (groups 2-4).
  • step 764 the boundary cell between the second group and the third group is cut-off.
  • step 766 the word lines for the groups not cut-off (e.g., groups 3-4) are reset. Word lines for group one and two remain at the boosting voltage.
  • step 768 data for the third group is applied to the bit lines.
  • step 770 one or more boosting voltages are applied to the word lines for the groups not cut-off (groups 3-4).
  • step 772 the boundary cell between the third group and the fourth group is cut-off.
  • step 774 the word lines for the groups not cut-off (e.g., group 4) are reset. Group one, two and three word lines remain at the boosting voltage.
  • step 776 data for the fourth group is applied to the bit lines.
  • step 778 one or more boosting voltages are applied to the word lines for the group not cut-off (group 4).
  • step 780 the drain side select gate is optionally cut-off. The considerations for this optional select gate cutoff are analogous to those described earlier for the two group case. Note that, in one embodiment, the process of Fig. 13 is performed simultaneously for many NAND strings.
  • the process of Figure 13 describes the use of four groups so that four memory cells on a NAND string can be simultaneously programmed.
  • the process of Figure 13 can be adapted to be used with more than four groups so that more than four memory cells on a NAND string can be simultaneously programmed. For example, steps 758-764 (with the iteration of step 760 applying the appropriate data and step 764 cutting-off the appropriate boundary cell) can be repeatedly performed for each additional group.
  • Figure 14 is a flow chart describing one embodiment of a process for verifying.
  • the process of Figure 14 is performed as part of step 622 of Figure 10 for a NAND string divided into two groups. Note that although multiple memory cells are programmed simultaneously, in one embodiment the verification process is performed sequentially.
  • step 820 pass voltages are applied to the unselected word lines in regard to the bottom group. That is the word lines for all of the memory cells, except the memory cell selected for programming in the bottom group, receive a pass voltage.
  • the pass voltage (e.g. 4.5 volts) is designed to make sure that each of the unselected memory cells is sufficiently turned on.
  • step 822 one or more verify pulses (appropriate to the type of data being programmed) are applied to the word line associated with the memory cell selected for programming in the bottom group.
  • Step 822 may also include pre-charging the bit line, as discussed above.
  • the data is sensed for each of the verify pulses.
  • One verify pulse is used for binary memory storage, and multiple verify pulses (e.g, total number of states -1, as per Fig. 8 ) are used for multi-state memory storage.
  • step 824 the system determines whether the memory cell has reached its target threshold voltage condition. If a memory cell has reached its target threshold voltage condition, then that memory cell is locked out from further programming in step 826 (e.g., by raising its bit line voltage to Vdd), thereby terminating programming to that memory cell for the duration of that programming session.
  • step 828 pass voltages are applied to the unselected word lines in regard to the top group. That is, the word lines for all of the memory cells, except the memory cell selected for programming in the top group, receives a pass voltage.
  • the pass voltage e.g. 4.5 volts
  • the pass voltage is designed to make sure that each of the unselected memory cells are sufficiently turned on.
  • one or more verify pulses are applied to the word line associated with the memory cell selected for programming in the top group. Step 830 may also include pre-charging the bit line, as discussed above. The data is sensed for each of the verify pulses.
  • step 832 the system determines whether the memory cell has reached its target threshold voltage.
  • a memory cell If a memory cell has reached its target threshold voltage, then that memory cell is locked out from further programming (e.g., by raising its bit line voltage to Vdd) in step 834 (analogous to step 826).
  • the process of Fig. 14 is performed on multiple NAND strings simultaneously. Furthermore, the process of Fig. 14 can be adapted to be used for more than two groups by repeating step 820-826 for each of the additional groups.

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TWI287228B (en) 2007-09-21
CN101057299B (zh) 2010-06-16
US7821835B2 (en) 2010-10-26
US20080055994A1 (en) 2008-03-06
KR20070069126A (ko) 2007-07-02
US20050276108A1 (en) 2005-12-15
TW200623136A (en) 2006-07-01
DE602005024394D1 (de) 2010-12-09
US7570518B2 (en) 2009-08-04
US7307884B2 (en) 2007-12-11
US20080056002A1 (en) 2008-03-06
KR100868570B1 (ko) 2008-11-13
WO2006001979A1 (en) 2006-01-05
CN101057299A (zh) 2007-10-17
US20080056003A1 (en) 2008-03-06
JP4647656B2 (ja) 2011-03-09
EP1759393A1 (en) 2007-03-07
US7796444B2 (en) 2010-09-14
JP2008503025A (ja) 2008-01-31
ATE486349T1 (de) 2010-11-15

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