EP1741141A1 - Systeme de transistor a effet de champ a ailettes et procede de production d'un systeme de transistor a effet de champ a ailettes - Google Patents

Systeme de transistor a effet de champ a ailettes et procede de production d'un systeme de transistor a effet de champ a ailettes

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Publication number
EP1741141A1
EP1741141A1 EP05748159A EP05748159A EP1741141A1 EP 1741141 A1 EP1741141 A1 EP 1741141A1 EP 05748159 A EP05748159 A EP 05748159A EP 05748159 A EP05748159 A EP 05748159A EP 1741141 A1 EP1741141 A1 EP 1741141A1
Authority
EP
European Patent Office
Prior art keywords
fin
field effect
effect transistor
fin field
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05748159A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Erhard Landgraf
Richard Johannes Luyken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1741141A1 publication Critical patent/EP1741141A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device

Definitions

  • the invention relates to a fin field effect transistor arrangement and a method for producing a fin field effect transistor arrangement.
  • CMOS technology integrated circuits are formed on a substrate, which have n-channel field effect transistors and p-channel field effect transistors. With the same dimensioning of the transistors of different conductivity types, it happens that an n-channel transistor of a CMOS circuit has a different current driver capability than a p-channel transistor of the circuit.
  • p-MOS Transistors with a different transistor width than n-MOS transistors are provided.
  • a p-channel transistor with a larger (e.g. two to three times) the width is often provided than the corresponding n-channel transistor.
  • n-MOS field-effect transistor 100 and a p-MOS field-effect transistor 110 of a CMOS circuit according to the prior art are described below with reference to FIGS. 1A, 1B.
  • the n-MOS field effect transistor 100 from FIG. 1A contains a first source / drain region 101 and a second source Z drain region 102, between which a channel region 103 is formed.
  • the electrical conductivity of the channel region 103 can be controlled by applying an electrical voltage to a gate region 104.
  • the transistor width of the n-MOS field-effect transistor 100 is denoted by d x in FIG. 1A.
  • FIG. 1B shows a p-MOS field-effect transistor 110 which is said to have the same current driving capability as the n-MOS field-effect transistor 100.
  • the p-MOS field-effect transistor 110 likewise has a first source / drain region 111 and a second source - / Drain region 112, between which a channel region 113 is formed.
  • the electrical conductivity of the channel region 113 can be controlled by applying an electrical signal to a gate region 114.
  • the transistor width d 2 of the p-MOS field-effect transistor 110 is substantially larger than the transistor width di of the n-MOS field-effect transistor 100.
  • the different transistor widths di, d 2 are required in order to be the same in a CMOS arrangement in which the n-MOS field-effect transistor 100 and the p-MOS field-effect transistor 110 are integrated To achieve current driving capabilities of the transistors.
  • the p-MOS field effect transistor 110 requires approximately three times the area as the n-MOS field effect transistor 100 in order to achieve the same current driving capability in both transistors 100, 110. This is disadvantageous because it increases the chip area required to form transistors 100, 110.
  • a new type of field effect transistor is the so-called fin field effect transistor or fin field effect transistor.
  • a thin fin i.e. formed in a thin semiconductor web with a width of, for example, 50 nm and less, two end sections as source / drain regions, between the two
  • a channel region is formed in the source / drain regions in the fin.
  • the channel area is covered by a gate insulating layer.
  • a gate electrode is formed above the fin, which enables lateral control of the electrical conductivity of the fin.
  • a fin field effect transistor arrangement is known from [2], in which the fins of an n-MOS fin field effect transistor and the fins of a p-MOS fin field effect transistor are divided into a plurality of semiconductor partial fins formed next to one another, with a different number the partial fins in the n-MOS fin field effect transistor and in the p-MOS fin field effect transistor the current driving capability of the two
  • Transistors can be matched.
  • this concept has the disadvantage that by dividing the fin into several sub-fins, the space requirement of the transistor arrangement is increased, which counteracts the attempt to increase the integration density.
  • n-MOS fin field effect transistor 120 is described below with reference to FIG. IC and a p-MOS fin field effect transistor 130 according to the prior art is described with reference to FIG. ID, in which similar
  • the n-MOS fin field effect transistor 120 contains two silicon partial fins 125, 126.
  • An end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 arranged in parallel forms a first source ZDrain region 121, and another end section of the mutually parallel silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 forms a second source ZDrain region 122.
  • a channel region 123 is formed, the conductivity of which is determined by a gate Area 124 is controllable, which is formed on the silicon partial fins 125, 126.
  • a gate insulating layer (not shown) is arranged between the gate region 124 and the silicon partial fins.
  • the p-MOS fin field effect transistor 130 contains six silicon partial fins 135.
  • One end section of the parallel silicon partial fins 135 of the p-MOS fin field effect transistor 130 forms a first source ZDrain region 131, and another end section of the one another Silicon partial fins 135 of the n-MOS fin field effect transistor 130 arranged in parallel form a second source ZDrain region 132.
  • a channel region 133 is formed between the first source ZDrain region 131 and the second source ZDrain region 132 whose electrical conductivity can be controlled by a gate region 134 which is formed on the silicon partial fins 135.
  • a gate insulating layer (not shown) is arranged between the gate region 134 and the silicon partial fins 135.
  • a fin field effect transistor device is described in [3], wherein, according to an embodiment described there, a plurality of field effect transistors stacked one above the other, each insulated by a dielectric layer, are provided. Furthermore, it is described for this stack of transistors that the ratio of the widths of the NMOS field-effect transistors and PMOS field effect transistors can be adjusted by adjusting the thickness of the semiconductor layers.
  • a method for producing a gate oxide layer with two regions of different layer thickness is known from [4].
  • [5] describes an MIS field-effect transistor, the channel area of which is significantly smaller than twice the maximum spread of the depletion area, which can form in the channel area.
  • the invention is based in particular on the problem of providing a fin field effect transistor arrangement in which the current driver capability of different fin field effect transistors can be coordinated with one another with a moderate amount of space.
  • the fin field effect transistor arrangement according to the invention contains a substrate and a first fin field effect transistor on andZ or in the substrate, the one
  • Has fin in which the channel region is formed between the first and the second source ZDrain region, and over which the gate region is formed. Furthermore, the fin field effect transistor arrangement contains one, for example laterally next to the first fin
  • Field effect transistor arranged, second fin field effect transistor on andZ or in the substrate, which has a fin in which the channel region between the first and the second source ZDrain region is formed, and over which the gate region is formed.
  • the height of the fin of the first fin field effect transistor is greater than the height of the fin of the second fin field effect transistor.
  • a first fin field effect transistor is formed on and Z or in a substrate and is formed with a fin in which the channel region between the first and the second source Z drain region is formed , and over which the channel area is formed. Furthermore, a second fin field effect transistor is formed on and Z or in the substrate and is formed with a fin in which the channel region is formed between the first and second source Z drain regions and over which the gate region is formed. The height of the fin of the first fin field effect transistor is provided to be greater than the height of the fin of the second fin field effect transistor.
  • a basic idea of the invention is to be seen in the fact that it has been recognized and exploited that in the case of fin field effect transistors the current flows on the side walls of the fin, and therefore by adjusting the height of the fins of different fin field effect transistors of a fin field effect transistor arrangement different current driver capability or generally different transistor properties of different fin field effect transistors can be compensated.
  • the height of a fin can be used as a parameter that is easily accessible in terms of process technology, in order to set the electrical properties of a fin field effect transistor with little outlay on process technology or to match these to the electrical properties of another fin field effect transistor.
  • the fin is preferably made of semiconductor material (e.g. silicon), but can also be made of metallic material.
  • the setting of the current driver capability in the fin field effect transistor according to the invention Arrangement by adjusting the height of the fins does not result in an increase in the chip area, since this increase has an effect only in one dimension perpendicular to the chip surface, but not in the surface plane of the substrate.
  • the fin field effect transistor arrangement according to the invention is therefore well suited for continued scaling. Furthermore, it is unnecessary according to the invention to increase the current driver capability of a p-channel fin field effect transistor by increasing the number of fins per transistor, which in turn would increase the required chip surface area.
  • the fin height of different fin field effect transistors of a fin field effect transistor arrangement is used according to the invention as parameters to adjust the transistor properties (threshold voltages, current driving capability, etc.) and to adapt them to the requirements of a desired application.
  • the height of the fins of the n-channel fin field effect transistors and the p-channel fin field effect transistors can be set differently, so that both transistor types have the same current driver capability.
  • the same current driver capability can be established for the p-channel fin field effect transistor as for an n-channel fin field effect transistor.
  • the fin of the first fin field effect transistor can dopant material of the p
  • Doping atoms of the opposite conductivity type is doped or undoped.
  • the fin of the first fin field-effect transistor can either have doping material of the p-conductivity type or be free of doping material and the fin of the second fin Have field effect transistor dopant of the n-type.
  • the two fin field effect transistors can have different line types, the resulting different transistor properties (especially current driver capabilities) being able to be compensated for by setting different fin heights.
  • the fin field effect transistor arrangement of the invention can be set up as a CMOS arrangement, i.e. as an arrangement of n-channel fin field effect transistors and p-channel fin field effect transistors, the current driver capabilities and other transistor properties being able to be matched to one another by adjusting the height of the fin of the two transistor types.
  • the height of the fin field-effect transistor of the p-conduction type is generally chosen to be higher than that of the n-fin field-effect transistor.
  • the height of the fin of the first fin field effect transistor and the height of the fin of the second fin field effect transistor can be adjusted such that the current driving ability of the first fin field effect transistor is substantially equal to the current driving ability of the second fin field effect transistor.
  • the substrate can be a SOI (silicone-on-insulator) substrate.
  • the fins can be formed in the upper silicon layer of such an SOI substrate. Since the fin height in this case is determined by the thickness of the SOI Substrate, in particular the upper silicon layer of an SOI substrate, an SOI substrate is advantageous which has different top silicon thicknesses.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are preferably formed at least in part on or in the upper silicon layer of the SOI substrate.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can be divided into a plurality of semiconductor sub-fins formed side by side.
  • the current driving ability of the transistor can be adjusted by combining two measures, namely by dividing different fin heights and by providing the fin as an arrangement of several semiconductor sub-fins.
  • the realization of a fin as several sub-fins is described in [2].
  • the plurality of semiconductor partial fins can be provided between two common source ZDrain connections of the fin field effect transistor and can be arranged essentially parallel to one another.
  • a desired current driving capability of a transistor can thus be set by balancing the number of sub-fins (the fewer, the smaller the area requirement) and the height of the sub-fins (the lower, the less the topology) suitable for an application.
  • the height of the fin of the first fin field effect transistor and the height of the fin of the second fin Field effect transistor and the number of sub-fins of the first fin field-effect transistor and the number of sub-fins of the second fin field-effect transistor can be adjusted such that the current driver capability of the first fin field-effect transistor is substantially equal to that
  • the method according to the invention for producing a fin field effect transistor arrangement is described below. Refinements of the fin field effect transistor arrangement also apply to the method for producing a fin field effect transistor arrangement and vice versa.
  • configurations are described in particular such as how fins of different heights of the fin field effect transistors can be realized.
  • an electrically insulating layer can be formed for this purpose between the substrate and the fin of the second fin field effect transistor.
  • the thickness of the electrically insulating layer can e.g. be provided such that the thickness together with the height of the fin of the second fin field effect transistor is substantially equal to the height of the fin of the first fin field effect transistor.
  • an electrically insulating layer can be formed on the fin of the second fin field effect transistor.
  • the fin of the second fin field effect transistor is e.g. formed directly on the substrate and an electrically insulating layer deposited over it. This makes it possible to use the electrically insulating layer as a spacer or as
  • Height compensation structure to compensate for the different heights of the fin of the first and the second field effect transistors, and thereby to obtain a layer arrangement with a more uniform topology.
  • the thickness of the electrically insulating layer can be adjusted in accordance with the described embodiments such that the electrically insulating layer together with the fin of the second fin field effect transistor has a height which is substantially equal to the height of the fin of the first fin field effect transistor.
  • the fin of the first fin field effect transistor and the fin of the second fin field effect transistor can be formed by forming and structuring a common semiconductor layer on the substrate, so that a first one laterally forming the fin of the first fin field effect transistor limited layer is formed and a second laterally limited layer is formed.
  • the fin of the second fin field effect transistor can then be formed by
  • Material of the second laterally delimited layer is removed.
  • semiconductor material is used to form the fin of the second fin field effect transistor second laterally delimited layer (for example removed by etching, in which case the fin of the first fin field effect transistor should be protected from etching by covering with an auxiliary structure), as a result of which the height of the fin of the second fin field effect transistor compared to the height of the fin of the first Fin field effect transistor is reduced.
  • the fin of the first fin field effect transistor and the fin of the second fin field effect transistor are formed from a surface semiconductor layer of a planar substrate, which surface semiconductor layer has a greater thickness in the region of the first fin field effect transistor than in the region of the second fin field effect transistor.
  • the layer sequence known from [1], in particular from FIG. 6 of [1] can be used as the starting substrate. Accordingly, an insulator layer with a stepped surface is provided, a semiconductor layer with different thicknesses being provided on the stepped surface.
  • the first fin field effect transistor (the one with the higher fin) in a semiconductor region of the substrate according to [1], in which the semiconductor layer has a greater thickness
  • the fin of the second fin field effect transistor (the one with the lower Fin) is formed in a region of the substrate [1] in which the semiconductor layer has a smaller thickness
  • An SOI substrate (silicone-on-insulator) can be used as the substrate, in particular partially or completely may be depleted of carriers and may be Z or a thin film SOI substrate.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can or can be at least partially formed from the upper silicon layer of the SOI substrate.
  • the doping material can in particular be introduced using the plasma immersion ion implantation method, the rapid vapor phase doping method or the solid phase diffusion method. These methods are particularly suitable as doping methods for doping fins, in particular fins of great height.
  • FIG. 3 shows a cross-sectional view of a fin field effect transistor arrangement according to an exemplary embodiment of the invention
  • FIG. 4 shows a cross-sectional view of a fin field effect transistor arrangement according to another exemplary embodiment of the invention
  • FIG. 2B an n-MOS
  • Fin field effect transistor 200 and a p-MOS fin field effect transistor 210 are described, which are integrated in a fin field effect transistor arrangement according to the invention and in a common substrate.
  • 2A, 2B which contains the n-MOS fin field effect transistor 200 and the p-MOS fin field effect transistor 210, has a silicon substrate 220 on which a silicon oxide Layer 221 is formed.
  • transistors 200, 210 are shown separately in FIGS. 2A, 2B, both fin field effect transistors 200, 210 are monolithically integrated in the same substrate 220.
  • the p-MOS fin field effect transistor 210 shown in FIG. 2B contains a silicon fin of height h 2 .
  • a first source ZDrain region 211 and a second source ZDrain region 212 are formed as implanted regions of the fin, between the source ZDrain regions 211, 212 a channel region 213 is arranged.
  • the electrical conductivity of the channel region 213 can be controlled by applying an electrical signal to a gate region 214 which is electrically insulated from the channel region by means of a gate insulating layer (not shown).
  • the current driving capabilities of the transistors 200, 210 are identical.
  • the adaptation of the current driver capabilities of the transistors 200, 210 does not lead to an increase in the space requirement of the transistors 200, 210 on the silicon substrate 220, since different dimensions of the components (namely the silicon fins) are required only in one dimension perpendicular to the substrate surface. An optimization of the required layout area is thus achieved in the inventive CMOS fin field effect transistor arrangement from FIGS. 2A, 2B.
  • a fin field effect transistor arrangement 300 according to an exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 300 is in one
  • Integrated silicon substrate 301 on which a silicon oxide layer 302 is formed.
  • a first silicon fin of a height h x which is less than the height h 2 of a second silicon, is formed on a first surface region of the fin field effect transistor arrangement 300, namely in an n-MOS fin field effect transistor region 305.
  • the fin field effect transistor arrangement 300 is formed on or in an SOI substrate (silicon-on-insulator).
  • the gate region, the gate insulating layer and the source Zdrain regions of the fin field effect transistors of the fin field effect transistor arrangement 300 are not shown in FIG. 3.
  • the second laterally delimited layer sequence is subsequently subjected to an etching process, as a result of which the second laterally delimited layer sequence is etched back in such a way that the first silicon fin 303 is formed with a lower height hi than the silicon fin 304 (height h 2 ). In other words, a lower silicon height is achieved by etching back silicon.
  • a fin field effect transistor arrangement 400 according to another exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 400 shown in FIG. 4 differs from the fin field effect transistor arrangement 300 shown in FIG. 3 in that a silicon oxide structure 401 is additionally applied to the first silicon fin 303.
  • This additional silicon oxide structure 401 which alternatively also consists of silicon nitride material has the effect that the same topology (ie the same surface structure) is achieved in the p-MOS fin field effect transistor region 305 as in the p-MOS fin field effect transistor region 306. This brings about advantages in subsequent lithography and planarization steps.
  • a fin field effect transistor arrangement 500 according to yet another exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 500 shown in FIG. 5 differs from the fin field effect transistor arrangements 300, 400 shown in FIGS. 3 and 4 in that the fin field effect transistor arrangement 500 is formed starting from a substrate, as described for example in Fig. 6 of [1]. There is described a substrate with a carrier layer and an insulator layer with a stepped surface with different surface areas on the carrier layer, a semiconductor layer having a different semiconductor thickness in different surface areas being formed on the stepped surface of the insulator layer that as a result a substrate with a planar surface is formed.
  • the silicon substrate 301 serves as the carrier layer in the fin field effect transistor arrangement 500.
  • the substrate shown contains a semiconductor layer which terminates with a planar surface. This semiconductor layer can only be seen in FIG. 5 in the form of the first silicon fin 303 and the second silicon fin 304.
  • the semiconductor layer thickness which is different in different areas of the substrate is structured such that the first silicon fin 303 and the second silicon fin 304 are formed thereby, which have different heights h x ⁇ h 2 , but whose upper end sections are arranged at the same height.
  • a fin field effect transistor arrangement 500 is thus provided, in which the n-MOS fin field effect transistor and the p-MOS fin field effect transistor have essentially the same height.
  • n-MOS field effect transistor 101 first source ZDrain region 102 second source ZDrain region 103 channel region 104 gate region 110 p-MOS field effect transistor 111 first source ZDrain region 112 second source ZDrain region 113 channel Region 114 gate region 120 n-MOS fin field effect transistor 121 first source ZDrain region 122 second source ZDrain region 123 channel region 124 gate region 125 first silicon partial fin 126 first silicon partial fin 130 p-MOS -Fin field effect transistor 131 first source ZDrain region 132 second source ZDrain region 133 channel region 134 gate region 135 silicon partial fins 200 n-MOS fin field effect transistor 201 first source ZDrain region 202 second source ZDrain Region 203 channel region 204 gate region 210 p-MOS fin field effect transistor 211 first source ZDrain region 212 second source ZDrain region 213 channel region 214 gate region 220 silicon substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un système de transistor à effet de champ à ailette, comportant un substrat, un premier transistor à effet de champ à ailette, situé sur et/ou dans le substrat, qui présente une ailette dans laquelle la zone de canal est formée entre la première et la seconde zone de source/drain et au-dessus de laquelle est formée une zone de grille. Ledit système comprend également un second transistor à effet de champ à ailette, situé sur et/ou dans le substrat, qui présente une ailette dans laquelle la zone de canal est formée entre la première et la seconde zone de source/drain et au-dessus de laquelle est formée la zone de grille. La hauteur de l'ailette du premier transistor à effet de champ à ailette est supérieure à celle de l'ailette du second transistor à effet de champ à ailette.
EP05748159A 2004-04-27 2005-04-22 Systeme de transistor a effet de champ a ailettes et procede de production d'un systeme de transistor a effet de champ a ailettes Withdrawn EP1741141A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004020593A DE102004020593A1 (de) 2004-04-27 2004-04-27 Fin-Feldeffekttransistor-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffektransistor-Anordnung
PCT/DE2005/000746 WO2005104238A1 (fr) 2004-04-27 2005-04-22 Systeme de transistor a effet de champ a ailettes et procede de production d'un systeme de transistor a effet de champ a ailettes

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US20070096196A1 (en) 2007-05-03
DE102004020593A1 (de) 2005-11-24
JP2007535153A (ja) 2007-11-29
WO2005104238A1 (fr) 2005-11-03
US7719059B2 (en) 2010-05-18

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