EP1741141A1 - Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement - Google Patents

Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement

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Publication number
EP1741141A1
EP1741141A1 EP05748159A EP05748159A EP1741141A1 EP 1741141 A1 EP1741141 A1 EP 1741141A1 EP 05748159 A EP05748159 A EP 05748159A EP 05748159 A EP05748159 A EP 05748159A EP 1741141 A1 EP1741141 A1 EP 1741141A1
Authority
EP
European Patent Office
Prior art keywords
fin
field effect
effect transistor
fin field
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05748159A
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German (de)
French (fr)
Inventor
Franz Hofmann
Erhard Landgraf
Richard Johannes Luyken
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1741141A1 publication Critical patent/EP1741141A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device

Definitions

  • the invention relates to a fin field effect transistor arrangement and a method for producing a fin field effect transistor arrangement.
  • CMOS technology integrated circuits are formed on a substrate, which have n-channel field effect transistors and p-channel field effect transistors. With the same dimensioning of the transistors of different conductivity types, it happens that an n-channel transistor of a CMOS circuit has a different current driver capability than a p-channel transistor of the circuit.
  • p-MOS Transistors with a different transistor width than n-MOS transistors are provided.
  • a p-channel transistor with a larger (e.g. two to three times) the width is often provided than the corresponding n-channel transistor.
  • n-MOS field-effect transistor 100 and a p-MOS field-effect transistor 110 of a CMOS circuit according to the prior art are described below with reference to FIGS. 1A, 1B.
  • the n-MOS field effect transistor 100 from FIG. 1A contains a first source / drain region 101 and a second source Z drain region 102, between which a channel region 103 is formed.
  • the electrical conductivity of the channel region 103 can be controlled by applying an electrical voltage to a gate region 104.
  • the transistor width of the n-MOS field-effect transistor 100 is denoted by d x in FIG. 1A.
  • FIG. 1B shows a p-MOS field-effect transistor 110 which is said to have the same current driving capability as the n-MOS field-effect transistor 100.
  • the p-MOS field-effect transistor 110 likewise has a first source / drain region 111 and a second source - / Drain region 112, between which a channel region 113 is formed.
  • the electrical conductivity of the channel region 113 can be controlled by applying an electrical signal to a gate region 114.
  • the transistor width d 2 of the p-MOS field-effect transistor 110 is substantially larger than the transistor width di of the n-MOS field-effect transistor 100.
  • the different transistor widths di, d 2 are required in order to be the same in a CMOS arrangement in which the n-MOS field-effect transistor 100 and the p-MOS field-effect transistor 110 are integrated To achieve current driving capabilities of the transistors.
  • the p-MOS field effect transistor 110 requires approximately three times the area as the n-MOS field effect transistor 100 in order to achieve the same current driving capability in both transistors 100, 110. This is disadvantageous because it increases the chip area required to form transistors 100, 110.
  • a new type of field effect transistor is the so-called fin field effect transistor or fin field effect transistor.
  • a thin fin i.e. formed in a thin semiconductor web with a width of, for example, 50 nm and less, two end sections as source / drain regions, between the two
  • a channel region is formed in the source / drain regions in the fin.
  • the channel area is covered by a gate insulating layer.
  • a gate electrode is formed above the fin, which enables lateral control of the electrical conductivity of the fin.
  • a fin field effect transistor arrangement is known from [2], in which the fins of an n-MOS fin field effect transistor and the fins of a p-MOS fin field effect transistor are divided into a plurality of semiconductor partial fins formed next to one another, with a different number the partial fins in the n-MOS fin field effect transistor and in the p-MOS fin field effect transistor the current driving capability of the two
  • Transistors can be matched.
  • this concept has the disadvantage that by dividing the fin into several sub-fins, the space requirement of the transistor arrangement is increased, which counteracts the attempt to increase the integration density.
  • n-MOS fin field effect transistor 120 is described below with reference to FIG. IC and a p-MOS fin field effect transistor 130 according to the prior art is described with reference to FIG. ID, in which similar
  • the n-MOS fin field effect transistor 120 contains two silicon partial fins 125, 126.
  • An end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 arranged in parallel forms a first source ZDrain region 121, and another end section of the mutually parallel silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 forms a second source ZDrain region 122.
  • a channel region 123 is formed, the conductivity of which is determined by a gate Area 124 is controllable, which is formed on the silicon partial fins 125, 126.
  • a gate insulating layer (not shown) is arranged between the gate region 124 and the silicon partial fins.
  • the p-MOS fin field effect transistor 130 contains six silicon partial fins 135.
  • One end section of the parallel silicon partial fins 135 of the p-MOS fin field effect transistor 130 forms a first source ZDrain region 131, and another end section of the one another Silicon partial fins 135 of the n-MOS fin field effect transistor 130 arranged in parallel form a second source ZDrain region 132.
  • a channel region 133 is formed between the first source ZDrain region 131 and the second source ZDrain region 132 whose electrical conductivity can be controlled by a gate region 134 which is formed on the silicon partial fins 135.
  • a gate insulating layer (not shown) is arranged between the gate region 134 and the silicon partial fins 135.
  • a fin field effect transistor device is described in [3], wherein, according to an embodiment described there, a plurality of field effect transistors stacked one above the other, each insulated by a dielectric layer, are provided. Furthermore, it is described for this stack of transistors that the ratio of the widths of the NMOS field-effect transistors and PMOS field effect transistors can be adjusted by adjusting the thickness of the semiconductor layers.
  • a method for producing a gate oxide layer with two regions of different layer thickness is known from [4].
  • [5] describes an MIS field-effect transistor, the channel area of which is significantly smaller than twice the maximum spread of the depletion area, which can form in the channel area.
  • the invention is based in particular on the problem of providing a fin field effect transistor arrangement in which the current driver capability of different fin field effect transistors can be coordinated with one another with a moderate amount of space.
  • the fin field effect transistor arrangement according to the invention contains a substrate and a first fin field effect transistor on andZ or in the substrate, the one
  • Has fin in which the channel region is formed between the first and the second source ZDrain region, and over which the gate region is formed. Furthermore, the fin field effect transistor arrangement contains one, for example laterally next to the first fin
  • Field effect transistor arranged, second fin field effect transistor on andZ or in the substrate, which has a fin in which the channel region between the first and the second source ZDrain region is formed, and over which the gate region is formed.
  • the height of the fin of the first fin field effect transistor is greater than the height of the fin of the second fin field effect transistor.
  • a first fin field effect transistor is formed on and Z or in a substrate and is formed with a fin in which the channel region between the first and the second source Z drain region is formed , and over which the channel area is formed. Furthermore, a second fin field effect transistor is formed on and Z or in the substrate and is formed with a fin in which the channel region is formed between the first and second source Z drain regions and over which the gate region is formed. The height of the fin of the first fin field effect transistor is provided to be greater than the height of the fin of the second fin field effect transistor.
  • a basic idea of the invention is to be seen in the fact that it has been recognized and exploited that in the case of fin field effect transistors the current flows on the side walls of the fin, and therefore by adjusting the height of the fins of different fin field effect transistors of a fin field effect transistor arrangement different current driver capability or generally different transistor properties of different fin field effect transistors can be compensated.
  • the height of a fin can be used as a parameter that is easily accessible in terms of process technology, in order to set the electrical properties of a fin field effect transistor with little outlay on process technology or to match these to the electrical properties of another fin field effect transistor.
  • the fin is preferably made of semiconductor material (e.g. silicon), but can also be made of metallic material.
  • the setting of the current driver capability in the fin field effect transistor according to the invention Arrangement by adjusting the height of the fins does not result in an increase in the chip area, since this increase has an effect only in one dimension perpendicular to the chip surface, but not in the surface plane of the substrate.
  • the fin field effect transistor arrangement according to the invention is therefore well suited for continued scaling. Furthermore, it is unnecessary according to the invention to increase the current driver capability of a p-channel fin field effect transistor by increasing the number of fins per transistor, which in turn would increase the required chip surface area.
  • the fin height of different fin field effect transistors of a fin field effect transistor arrangement is used according to the invention as parameters to adjust the transistor properties (threshold voltages, current driving capability, etc.) and to adapt them to the requirements of a desired application.
  • the height of the fins of the n-channel fin field effect transistors and the p-channel fin field effect transistors can be set differently, so that both transistor types have the same current driver capability.
  • the same current driver capability can be established for the p-channel fin field effect transistor as for an n-channel fin field effect transistor.
  • the fin of the first fin field effect transistor can dopant material of the p
  • Doping atoms of the opposite conductivity type is doped or undoped.
  • the fin of the first fin field-effect transistor can either have doping material of the p-conductivity type or be free of doping material and the fin of the second fin Have field effect transistor dopant of the n-type.
  • the two fin field effect transistors can have different line types, the resulting different transistor properties (especially current driver capabilities) being able to be compensated for by setting different fin heights.
  • the fin field effect transistor arrangement of the invention can be set up as a CMOS arrangement, i.e. as an arrangement of n-channel fin field effect transistors and p-channel fin field effect transistors, the current driver capabilities and other transistor properties being able to be matched to one another by adjusting the height of the fin of the two transistor types.
  • the height of the fin field-effect transistor of the p-conduction type is generally chosen to be higher than that of the n-fin field-effect transistor.
  • the height of the fin of the first fin field effect transistor and the height of the fin of the second fin field effect transistor can be adjusted such that the current driving ability of the first fin field effect transistor is substantially equal to the current driving ability of the second fin field effect transistor.
  • the substrate can be a SOI (silicone-on-insulator) substrate.
  • the fins can be formed in the upper silicon layer of such an SOI substrate. Since the fin height in this case is determined by the thickness of the SOI Substrate, in particular the upper silicon layer of an SOI substrate, an SOI substrate is advantageous which has different top silicon thicknesses.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are preferably formed at least in part on or in the upper silicon layer of the SOI substrate.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can be divided into a plurality of semiconductor sub-fins formed side by side.
  • the current driving ability of the transistor can be adjusted by combining two measures, namely by dividing different fin heights and by providing the fin as an arrangement of several semiconductor sub-fins.
  • the realization of a fin as several sub-fins is described in [2].
  • the plurality of semiconductor partial fins can be provided between two common source ZDrain connections of the fin field effect transistor and can be arranged essentially parallel to one another.
  • a desired current driving capability of a transistor can thus be set by balancing the number of sub-fins (the fewer, the smaller the area requirement) and the height of the sub-fins (the lower, the less the topology) suitable for an application.
  • the height of the fin of the first fin field effect transistor and the height of the fin of the second fin Field effect transistor and the number of sub-fins of the first fin field-effect transistor and the number of sub-fins of the second fin field-effect transistor can be adjusted such that the current driver capability of the first fin field-effect transistor is substantially equal to that
  • the method according to the invention for producing a fin field effect transistor arrangement is described below. Refinements of the fin field effect transistor arrangement also apply to the method for producing a fin field effect transistor arrangement and vice versa.
  • configurations are described in particular such as how fins of different heights of the fin field effect transistors can be realized.
  • an electrically insulating layer can be formed for this purpose between the substrate and the fin of the second fin field effect transistor.
  • the thickness of the electrically insulating layer can e.g. be provided such that the thickness together with the height of the fin of the second fin field effect transistor is substantially equal to the height of the fin of the first fin field effect transistor.
  • an electrically insulating layer can be formed on the fin of the second fin field effect transistor.
  • the fin of the second fin field effect transistor is e.g. formed directly on the substrate and an electrically insulating layer deposited over it. This makes it possible to use the electrically insulating layer as a spacer or as
  • Height compensation structure to compensate for the different heights of the fin of the first and the second field effect transistors, and thereby to obtain a layer arrangement with a more uniform topology.
  • the thickness of the electrically insulating layer can be adjusted in accordance with the described embodiments such that the electrically insulating layer together with the fin of the second fin field effect transistor has a height which is substantially equal to the height of the fin of the first fin field effect transistor.
  • the fin of the first fin field effect transistor and the fin of the second fin field effect transistor can be formed by forming and structuring a common semiconductor layer on the substrate, so that a first one laterally forming the fin of the first fin field effect transistor limited layer is formed and a second laterally limited layer is formed.
  • the fin of the second fin field effect transistor can then be formed by
  • Material of the second laterally delimited layer is removed.
  • semiconductor material is used to form the fin of the second fin field effect transistor second laterally delimited layer (for example removed by etching, in which case the fin of the first fin field effect transistor should be protected from etching by covering with an auxiliary structure), as a result of which the height of the fin of the second fin field effect transistor compared to the height of the fin of the first Fin field effect transistor is reduced.
  • the fin of the first fin field effect transistor and the fin of the second fin field effect transistor are formed from a surface semiconductor layer of a planar substrate, which surface semiconductor layer has a greater thickness in the region of the first fin field effect transistor than in the region of the second fin field effect transistor.
  • the layer sequence known from [1], in particular from FIG. 6 of [1] can be used as the starting substrate. Accordingly, an insulator layer with a stepped surface is provided, a semiconductor layer with different thicknesses being provided on the stepped surface.
  • the first fin field effect transistor (the one with the higher fin) in a semiconductor region of the substrate according to [1], in which the semiconductor layer has a greater thickness
  • the fin of the second fin field effect transistor (the one with the lower Fin) is formed in a region of the substrate [1] in which the semiconductor layer has a smaller thickness
  • An SOI substrate (silicone-on-insulator) can be used as the substrate, in particular partially or completely may be depleted of carriers and may be Z or a thin film SOI substrate.
  • the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can or can be at least partially formed from the upper silicon layer of the SOI substrate.
  • the doping material can in particular be introduced using the plasma immersion ion implantation method, the rapid vapor phase doping method or the solid phase diffusion method. These methods are particularly suitable as doping methods for doping fins, in particular fins of great height.
  • FIG. 3 shows a cross-sectional view of a fin field effect transistor arrangement according to an exemplary embodiment of the invention
  • FIG. 4 shows a cross-sectional view of a fin field effect transistor arrangement according to another exemplary embodiment of the invention
  • FIG. 2B an n-MOS
  • Fin field effect transistor 200 and a p-MOS fin field effect transistor 210 are described, which are integrated in a fin field effect transistor arrangement according to the invention and in a common substrate.
  • 2A, 2B which contains the n-MOS fin field effect transistor 200 and the p-MOS fin field effect transistor 210, has a silicon substrate 220 on which a silicon oxide Layer 221 is formed.
  • transistors 200, 210 are shown separately in FIGS. 2A, 2B, both fin field effect transistors 200, 210 are monolithically integrated in the same substrate 220.
  • the p-MOS fin field effect transistor 210 shown in FIG. 2B contains a silicon fin of height h 2 .
  • a first source ZDrain region 211 and a second source ZDrain region 212 are formed as implanted regions of the fin, between the source ZDrain regions 211, 212 a channel region 213 is arranged.
  • the electrical conductivity of the channel region 213 can be controlled by applying an electrical signal to a gate region 214 which is electrically insulated from the channel region by means of a gate insulating layer (not shown).
  • the current driving capabilities of the transistors 200, 210 are identical.
  • the adaptation of the current driver capabilities of the transistors 200, 210 does not lead to an increase in the space requirement of the transistors 200, 210 on the silicon substrate 220, since different dimensions of the components (namely the silicon fins) are required only in one dimension perpendicular to the substrate surface. An optimization of the required layout area is thus achieved in the inventive CMOS fin field effect transistor arrangement from FIGS. 2A, 2B.
  • a fin field effect transistor arrangement 300 according to an exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 300 is in one
  • Integrated silicon substrate 301 on which a silicon oxide layer 302 is formed.
  • a first silicon fin of a height h x which is less than the height h 2 of a second silicon, is formed on a first surface region of the fin field effect transistor arrangement 300, namely in an n-MOS fin field effect transistor region 305.
  • the fin field effect transistor arrangement 300 is formed on or in an SOI substrate (silicon-on-insulator).
  • the gate region, the gate insulating layer and the source Zdrain regions of the fin field effect transistors of the fin field effect transistor arrangement 300 are not shown in FIG. 3.
  • the second laterally delimited layer sequence is subsequently subjected to an etching process, as a result of which the second laterally delimited layer sequence is etched back in such a way that the first silicon fin 303 is formed with a lower height hi than the silicon fin 304 (height h 2 ). In other words, a lower silicon height is achieved by etching back silicon.
  • a fin field effect transistor arrangement 400 according to another exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 400 shown in FIG. 4 differs from the fin field effect transistor arrangement 300 shown in FIG. 3 in that a silicon oxide structure 401 is additionally applied to the first silicon fin 303.
  • This additional silicon oxide structure 401 which alternatively also consists of silicon nitride material has the effect that the same topology (ie the same surface structure) is achieved in the p-MOS fin field effect transistor region 305 as in the p-MOS fin field effect transistor region 306. This brings about advantages in subsequent lithography and planarization steps.
  • a fin field effect transistor arrangement 500 according to yet another exemplary embodiment of the invention is described below with reference to FIG.
  • the fin field effect transistor arrangement 500 shown in FIG. 5 differs from the fin field effect transistor arrangements 300, 400 shown in FIGS. 3 and 4 in that the fin field effect transistor arrangement 500 is formed starting from a substrate, as described for example in Fig. 6 of [1]. There is described a substrate with a carrier layer and an insulator layer with a stepped surface with different surface areas on the carrier layer, a semiconductor layer having a different semiconductor thickness in different surface areas being formed on the stepped surface of the insulator layer that as a result a substrate with a planar surface is formed.
  • the silicon substrate 301 serves as the carrier layer in the fin field effect transistor arrangement 500.
  • the substrate shown contains a semiconductor layer which terminates with a planar surface. This semiconductor layer can only be seen in FIG. 5 in the form of the first silicon fin 303 and the second silicon fin 304.
  • the semiconductor layer thickness which is different in different areas of the substrate is structured such that the first silicon fin 303 and the second silicon fin 304 are formed thereby, which have different heights h x ⁇ h 2 , but whose upper end sections are arranged at the same height.
  • a fin field effect transistor arrangement 500 is thus provided, in which the n-MOS fin field effect transistor and the p-MOS fin field effect transistor have essentially the same height.
  • n-MOS field effect transistor 101 first source ZDrain region 102 second source ZDrain region 103 channel region 104 gate region 110 p-MOS field effect transistor 111 first source ZDrain region 112 second source ZDrain region 113 channel Region 114 gate region 120 n-MOS fin field effect transistor 121 first source ZDrain region 122 second source ZDrain region 123 channel region 124 gate region 125 first silicon partial fin 126 first silicon partial fin 130 p-MOS -Fin field effect transistor 131 first source ZDrain region 132 second source ZDrain region 133 channel region 134 gate region 135 silicon partial fins 200 n-MOS fin field effect transistor 201 first source ZDrain region 202 second source ZDrain Region 203 channel region 204 gate region 210 p-MOS fin field effect transistor 211 first source ZDrain region 212 second source ZDrain region 213 channel region 214 gate region 220 silicon substrate

Abstract

The invention relates to a fin field effect transistor arrangement comprising a substrate, a first fin field effect transistor on and/or in said substrate that has a fin in which the channel region is formed between the first and second source/drain region, and above which the gate region is formed, and comprising a second fin field effect transistor on and/or in the substrate that has a fin in which the channel region is formed between the first and second source/drain region, and above which the gate region is formed. The height of the fin of the first fin field effect transistor arrangement is greater than the height of the fin of the second fin field effect transistor.

Description

Beschreibungdescription
Fin-Feldeffekttransistor-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffekttransistor-AnordnungFin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
Die Erfindung betrifft eine Fin-Feldeffekttransistor- Anordnung und ein Verfahren zum Herstellen einer Fin- Feldeffekttransistor-Anordnung.The invention relates to a fin field effect transistor arrangement and a method for producing a fin field effect transistor arrangement.
In der CMOS-Technologie werden auf einem Substrat integrierte Schaltkreise gebildet, die n-Kanal-Feldeffekttransistoren und p-Kanal-Feldeffekttransistoren aufweisen. Bei gleicher Dimensionierung der Transistoren unterschiedlichen Leitungstyps kommt es vor, dass ein n-Kanal-Transistor eines CMOS-Schaltkreises eine andere Stromtreiberfähigkeit aufweist als ein p-Kanal -Transistor des Schaltkreises.In CMOS technology, integrated circuits are formed on a substrate, which have n-channel field effect transistors and p-channel field effect transistors. With the same dimensioning of the transistors of different conductivity types, it happens that an n-channel transistor of a CMOS circuit has a different current driver capability than a p-channel transistor of the circuit.
Bei integrierten Schaltkreiskomponenten in CMOS-Technologie, die n-MOS-Transistoren und p-MOS-Transistoren aufweisen (beispielsweise Inverter, Oszillatoren, etc.), wird gemäß dem Stand der Technik die unterschiedliche Stromtreiberfähigkeit der Transistoren unterschiedlichen Leitungstyps ausgeglichen, indem p-MOS-Transistoren mit einer anderen Transistorweite vorgesehen werden als n-MOS-Transistoren. Häufig wird ein p- Kanal-Transistor mit einer größeren (z.B. zwei bis dreifachen) Weite vorgesehen als der entsprechende n-Kanal- Transistor.In the case of integrated circuit components in CMOS technology which have n-MOS transistors and p-MOS transistors (for example inverters, oscillators, etc.), according to the prior art, the different current driving ability of the transistors of different conduction types is compensated for by p-MOS Transistors with a different transistor width than n-MOS transistors are provided. A p-channel transistor with a larger (e.g. two to three times) the width is often provided than the corresponding n-channel transistor.
Allerdings hat die Erhöhung der Transistorweite des p-Kanal- Transistors in einem CMOS-Schaltkreis den Nachteil, dass dadurch der Flächenbedarf zum Realisieren des Schaltkreises auf einem Silizium-Chip vergrößert wird. Dadurch geht wertvolle Silizium-Fläche verloren, was angesichts des Kostendrucks in der Halbleitertechnologie nachteilig ist. Im Weiteren werden bezugnehmend auf Fig.lA, Fig.lB ein n-MOS- Feldeffekttransistor 100 und ein p-MOS-Feldeffekttransistor 110 eines CMOS-Schaltkreises gemäß dem Stand der Technik beschrieben.However, increasing the transistor width of the p-channel transistor in a CMOS circuit has the disadvantage that it increases the area required to implement the circuit on a silicon chip. As a result, valuable silicon area is lost, which is disadvantageous in view of the cost pressure in semiconductor technology. An n-MOS field-effect transistor 100 and a p-MOS field-effect transistor 110 of a CMOS circuit according to the prior art are described below with reference to FIGS. 1A, 1B.
Der n-MOS-Feldeffekttransistor 100 aus Fig.lA enthält einen ersten Source-/Drain-Bereich 101 und einen zweiten Source- ZDrain-Bereich 102, zwischen denen ein Kanal-Bereich 103 gebildet ist. Die elektrische Leitfähigkeit des Kanal- Bereichs 103 kann mittels Anlegens einer elektrischen Spannung an einen Gate-Bereiche 104 gesteuert werden. Die Transistorweite des n-MOS-Feldeffekttransistors 100 ist in Fig.lA mit dx bezeichnet.The n-MOS field effect transistor 100 from FIG. 1A contains a first source / drain region 101 and a second source Z drain region 102, between which a channel region 103 is formed. The electrical conductivity of the channel region 103 can be controlled by applying an electrical voltage to a gate region 104. The transistor width of the n-MOS field-effect transistor 100 is denoted by d x in FIG. 1A.
In Fig.lB ist ein p-MOS-Feldeffekttransistor 110 gezeigt, der dieselbe Stromtreiberfähigkeit aufweisen soll wie der n-MOS- Feldeffekttransistor 100. Der p-MOS-Feldeffekttransistor 110 weist ebenfalls einen ersten Source-/Drain-Bereich 111 und einen zweiten Source-/Drain-Bereich 112 auf, zwischen denen ein Kanal-Bereich 113 gebildet ist. Die elektrische Leitfähigkeit des Kanal-Bereichs 113 kann mittels Anlegens eines elektrischen Signals an einen Gate-Bereich 114 gesteuert werden.FIG. 1B shows a p-MOS field-effect transistor 110 which is said to have the same current driving capability as the n-MOS field-effect transistor 100. The p-MOS field-effect transistor 110 likewise has a first source / drain region 111 and a second source - / Drain region 112, between which a channel region 113 is formed. The electrical conductivity of the channel region 113 can be controlled by applying an electrical signal to a gate region 114.
Wie in Fig.lB gezeigt, ist die Transistorweite d2 des p-MOS- Feldeffekttransistors 110 wesentlich größer als die Transistorweite di des n-MOS-Feldeffekttransistors 100.As shown in FIG. 1B, the transistor width d 2 of the p-MOS field-effect transistor 110 is substantially larger than the transistor width di of the n-MOS field-effect transistor 100.
Die unterschiedlichen Transistorweiten di, d2 sind erforderlich, um bei einer CMOS-Anordnung, in welcher der n- MOS-Feldeffekttransistor 100 und der p-MOS- Feldeffekttransistor 110 integriert sind, gleiche Stromtreiberfähigkeiten der Transistoren zu erreichen. Somit benötigt der p-MOS-Feldeffekttransistor 110 etwa die dreifache Fläche wie der n-MOS-Feldeffekttransistor 100, um die gleiche Stromtreiberfähigkeit in beiden Transistoren 100, 110 zu erreichen. Dies ist nachteilhaft, da dadurch die erforderliche Chipfläche zum Bilden der Transistoren 100, 110 vergrößert wird.The different transistor widths di, d 2 are required in order to be the same in a CMOS arrangement in which the n-MOS field-effect transistor 100 and the p-MOS field-effect transistor 110 are integrated To achieve current driving capabilities of the transistors. Thus, the p-MOS field effect transistor 110 requires approximately three times the area as the n-MOS field effect transistor 100 in order to achieve the same current driving capability in both transistors 100, 110. This is disadvantageous because it increases the chip area required to form transistors 100, 110.
Angesichts des Bedarfs an zunehmend kleineren integrierten Bauelementen und an Transistoren, die auch bei einer fortgesetzten Skalierung eine gute Steuerung der elektrischen Leitfähigkeit des Kanal-Bereichs ermöglichen, sind Alternativen zu herkömmlichen Feldeffekttransistoren Gegenstand aktueller Forschung und Entwicklung. Ein solcher neuartiger Typ eines Feldeffekttransistors ist der sogenannte Fin-Feldeffekttransistor oder Steg-Feldeffekttransistor. Bei einem Fin-Feldeffekttransistor sind in einer dünnen Finne, d.h. in einem dünnen Halbleitersteg mit einer Breite von beispielsweise 50nm und weniger, zwei Endabschnitte als Source-/Drain-Bereiche gebildet, wobei zwischen den beidenIn view of the need for increasingly smaller integrated components and for transistors, which allow good control of the electrical conductivity of the channel region even with continued scaling, alternatives to conventional field effect transistors are the subject of current research and development. Such a new type of field effect transistor is the so-called fin field effect transistor or fin field effect transistor. In a fin field effect transistor, a thin fin, i.e. formed in a thin semiconductor web with a width of, for example, 50 nm and less, two end sections as source / drain regions, between the two
Source-/Drain-Bereichen in der Finne ein Kanal-Bereich gebildet ist. Der Kanal-Bereich ist von einer Gateisolierenden Schicht bedeckt. Auf der Gate-isolierenden Schicht, d.h. über der Finne, ist eine Gate-Elektrode gebildet, welche eine seitliche Ansteuerung der elektrischen Leitfähigkeit der Finne ermöglicht.A channel region is formed in the source / drain regions in the fin. The channel area is covered by a gate insulating layer. On the gate insulating layer, i.e. A gate electrode is formed above the fin, which enables lateral control of the electrical conductivity of the fin.
Jedoch tritt auch bei Fin-Feldeffekttransistoren das Problem auf, dass p-Fin-Feldeffekttransistoren Stromtreiberfähigkeiten bzw. allgemeinHowever, the problem also arises with fin field effect transistors that p-fin field effect transistors have current driving capabilities or in general
Transistoreigenschaften aufweisen, die sich bei gleicher Dimensionierung von den Stromtreiberfähigkeiten bzw. Transistoreigenschaften eines n-Fin-Feldeffekttransistors unterscheiden.Have transistor properties that differ from the current driver capabilities or Differentiate transistor properties of an n-fin field effect transistor.
Aus [2] ist eine Fin-Feldeffekttransistor-Anordnung bekannt, bei der die Finnen eines n-MOS-Fin-Feldeffekttransistors und die Finne eines p-MOS-Fin-Feldeffekttransistors in mehrere nebeneinander gebildete Halbleiter-Teilfinnen aufgeteilt sind, wobei durch unterschiedliche Anzahl der Teilfinnen in dem n-MOS-Fin-Feldeffekttransistor und in dem p-MOS-Fin- Feldeffekttransistor die Stromtreiberfähigkeit der beidenA fin field effect transistor arrangement is known from [2], in which the fins of an n-MOS fin field effect transistor and the fins of a p-MOS fin field effect transistor are divided into a plurality of semiconductor partial fins formed next to one another, with a different number the partial fins in the n-MOS fin field effect transistor and in the p-MOS fin field effect transistor the current driving capability of the two
Transistoren aufeinander abgestimmt werden können. Allerdings weist dieses Konzept den Nachteil auf, dass mittels Aufteilens der Finne in mehrere Teilfinnen der Platzbedarf der Transistor-Anordnung erhöht wird, was dem Bestreben nach einer Erhöhung der Integrationsdichte entgegenwirkt.Transistors can be matched. However, this concept has the disadvantage that by dividing the fin into several sub-fins, the space requirement of the transistor arrangement is increased, which counteracts the attempt to increase the integration density.
Im Weiteren wird bezugnehmend auf Fig. IC ein n-MOS-Fin- Feldeffekttransistor 120 und wird bezugnehmend auf Fig.lD ein p-MOS-Fin-Feldeffekttransistor 130 gemäß dem Stand der Technik beschrieben, bei denen ähnlicheAn n-MOS fin field effect transistor 120 is described below with reference to FIG. IC and a p-MOS fin field effect transistor 130 according to the prior art is described with reference to FIG. ID, in which similar
Stromtreiberfähigkeiten dadurch angestrebt werden, dass jeweils eine Mehrzahl von Teilfinnen vorgesehen sind, deren Anzahl unterschiedlich groß ist.Current driving capabilities are sought in that a plurality of sub-fins are provided, the number of which is different.
Der n-MOS-Fin-Feldeffekttransistor 120 enthält zwei Silizium- Teilfinnen 125, 126. Ein Endabschnitt der zueinander parallel angeordneten Silizium-Teilfinnen 125, 126 des n-MOS-Fin- Feldeffekttransistors 120 bildet einen ersten Source-ZDrain- Bereich 121, und ein anderer Endabschnitt der zueinander parallelen Silizium-Teilfinnen 125, 126 des n-MOS-Fin- Feldeffekttransistors 120 bildet einen zweiten Source-ZDrain- Bereich 122. Zwischen dem ersten Source-ZDrain-Bereich 121 und dem zweiten Source-ZDrain-Bereich 122 ist ein Kanal- Bereich 123 gebildet, dessen Leitfähigkeit von einem Gate- Bereich 124 steuerbar ist, welcher auf den Silizium- Teilfinnen 125, 126 gebildet ist. Zwischen dem Gate-Bereich 124 und den Silizium-Teilfinnen ist eine Gate-isolierende Schicht (nicht gezeigt) angeordnet.The n-MOS fin field effect transistor 120 contains two silicon partial fins 125, 126. An end section of the silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 arranged in parallel forms a first source ZDrain region 121, and another end section of the mutually parallel silicon partial fins 125, 126 of the n-MOS fin field effect transistor 120 forms a second source ZDrain region 122. Between the first source ZDrain region 121 and the second source ZDrain region 122 a channel region 123 is formed, the conductivity of which is determined by a gate Area 124 is controllable, which is formed on the silicon partial fins 125, 126. A gate insulating layer (not shown) is arranged between the gate region 124 and the silicon partial fins.
Der p-MOS-Fin-Feldeffekttransistor 130 enthält sechs Silizium-Teilfinnen 135. Ein Endabschnitt der zueinander parallelen Silizium-Teilfinnen 135 des p-MOS-Fin- Feldeffekttransistors 130 bildet einen ersten Source-ZDrain- Bereich 131, und ein anderer Endabschnitt der zueinander parallel angeordneten Silizium-Teilfinnen 135 des n-MOS-Fin- Feldeffekttransistors 130 bildet einen zweiten Source-ZDrain- Bereich 132. Zwischen dem ersten Source-ZDrain-Bereich 131 und dem zweiten Source-ZDrain-Bereich 132 ist ein Kanal- Bereich 133 gebildet, dessen elektrische Leitfähigkeit von einem Gate-Bereich 134 steuerbar ist, welcher auf den Silizium-Teilfinnen 135 gebildet ist. Zwischen dem Gate- Bereich 134 und den Silizium-Teilfinnen 135 ist eine Gateisolierende Schicht (nicht gezeigt) angeordnet.The p-MOS fin field effect transistor 130 contains six silicon partial fins 135. One end section of the parallel silicon partial fins 135 of the p-MOS fin field effect transistor 130 forms a first source ZDrain region 131, and another end section of the one another Silicon partial fins 135 of the n-MOS fin field effect transistor 130 arranged in parallel form a second source ZDrain region 132. A channel region 133 is formed between the first source ZDrain region 131 and the second source ZDrain region 132 whose electrical conductivity can be controlled by a gate region 134 which is formed on the silicon partial fins 135. A gate insulating layer (not shown) is arranged between the gate region 134 and the silicon partial fins 135.
Wie aus Fig. IC, Fig.lD hervorgeht, ist der Flächenbedarf eines Feldeffekttransistors mit mehreren Teilfinnen umso größer, je größer die Anzahl der Teilfinnen ist. Somit erhöht das Vorsehen einer Mehrzahl von Teilfinnen den Flächenbedarf erheblich.As is apparent from FIG. IC, FIG. 1D, the larger the number of partial fins, the greater the area requirement of a field effect transistor with several partial fins. The provision of a plurality of partial fins thus considerably increases the space requirement.
Ferner ist in [3] ein Fin-Feldeffekttransistor-Device beschrieben, wobei gemäß einer dort beschriebenen Ausführungsform mehrere, voneinander durch jeweils eine dielektrische Schicht isolierte, übereinander gestapelte Feldeffekttransistoren vorgesehen sind. Weiterhin ist für diesen Stapel von Transistoren beschrieben, dass das Verhältnis der Weiten der NMOS-Feldeffekttransistoren und PMOS-Feldeffekttransistoren angepasst werden kann mittels Anpassens der Dicken der Halbleiterschichten.Furthermore, a fin field effect transistor device is described in [3], wherein, according to an embodiment described there, a plurality of field effect transistors stacked one above the other, each insulated by a dielectric layer, are provided. Furthermore, it is described for this stack of transistors that the ratio of the widths of the NMOS field-effect transistors and PMOS field effect transistors can be adjusted by adjusting the thickness of the semiconductor layers.
Aus [4] ist ein Verfahren zum Erzeugen einer Gate-Oxidschicht mit zwei Bereichen unterschiedlicher Schichtdicke bekannt.A method for producing a gate oxide layer with two regions of different layer thickness is known from [4].
[5] beschreibt einen MIS-Feldeffekttransistor, dessen Kanalbereich wesentlich kleiner ist als das Zweifache der maximalen Ausbreitung des Verarmungsbereichs, der sich in dem Kanalbereich ausbilden kann.[5] describes an MIS field-effect transistor, the channel area of which is significantly smaller than twice the maximum spread of the depletion area, which can form in the channel area.
Der Erfindung liegt insbesondere das Problem zugrunde, eine Fin-Feldeffekttransistor-Anordnung bereitzustellen, bei der die Stromtreiberfähigkeit unterschiedlicher Fin- Feldeffekttransistoren mit moderatem Flächenaufwand aufeinander abstimmbar sind.The invention is based in particular on the problem of providing a fin field effect transistor arrangement in which the current driver capability of different fin field effect transistors can be coordinated with one another with a moderate amount of space.
Das Problem wird durch eine Fin-Feldeffekttransistor- Anordnung und durch ein Verfahren zum Herstellen einer Fin- Feldeffektransistor-Anordnung mit den Merkmalen gemäß den unabhängigen Patentansprüchen gelöst .The problem is solved by a fin field effect transistor arrangement and by a method for producing a fin field effect transistor arrangement with the features according to the independent patent claims.
Die erfindungsgemäße Fin-Feldeffekttransistor-Anordnung enthält ein Substrat und einen ersten Fin- Feldeffekttransistor auf undZoder in dem Substrat, der eineThe fin field effect transistor arrangement according to the invention contains a substrate and a first fin field effect transistor on andZ or in the substrate, the one
Finne aufweist, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain-Bereich gebildet ist, und über welcher der Gate-Bereich gebildet ist. Ferner enthält die Fin-Feldeffekttransistor-Anordnung einen, beispielsweise lateral neben dem ersten Fin-Has fin, in which the channel region is formed between the first and the second source ZDrain region, and over which the gate region is formed. Furthermore, the fin field effect transistor arrangement contains one, for example laterally next to the first fin
Feldeffekttransistor angeordneten, zweiten Fin- Feldeffekttransistor auf undZoder in dem Substrat, der eine Finne aufweist, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain-Bereich gebildet ist, und über welcher der Gate-Bereich gebildet ist. Die Höhe der Finne des ersten Fin-Feldeffekttransistors ist größer als die Höhe der Finne des zweiten Fin-Feldeffekttransistors.Field effect transistor arranged, second fin field effect transistor on andZ or in the substrate, which has a fin in which the channel region between the first and the second source ZDrain region is formed, and over which the gate region is formed. The height of the fin of the first fin field effect transistor is greater than the height of the fin of the second fin field effect transistor.
Bei dem erfindungsgemäßen Verfahren zum Herstellen einer Fin- Feldeffekttransistor-Anordnung wird ein erster Fin- Feldeffekttransistor auf undZoder in einem Substrat gebildet und wird mit einer Finne gebildet, in welcher der Kanal- Bereich zwischen dem ersten und dem zweiten Source-ZDrain- Bereich gebildet wird, und über welcher der Kanal-Bereich gebildet wird. Ferner wird ein zweiter Fin- Feldeffekttransistor auf undZoder in dem Substrat gebildet und mit einer Finne gebildet, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain-Bereich gebildet wird, und über welcher der Gate-Bereich gebildet wird. Die Höhe der Finne des ersten Fin-Feldeffekttransistors wird größer vorgesehen als die Höhe der Finne des zweiten Fin-Feldeffekttransistors .In the method according to the invention for producing a fin field effect transistor arrangement, a first fin field effect transistor is formed on and Z or in a substrate and is formed with a fin in which the channel region between the first and the second source Z drain region is formed , and over which the channel area is formed. Furthermore, a second fin field effect transistor is formed on and Z or in the substrate and is formed with a fin in which the channel region is formed between the first and second source Z drain regions and over which the gate region is formed. The height of the fin of the first fin field effect transistor is provided to be greater than the height of the fin of the second fin field effect transistor.
Eine Grundidee der Erfindung ist darin zu sehen, dass erkannt wurde und ausgenutzt wird, dass bei Fin- Feldeffekttransistoren der Strom an den Seitenwänden der Finne fließt, und dass deshalb mittels Justierens der Höhe der Finnen unterschiedlicher Fin-Feldeffekttransistoren einer Fin-Feldeffekttransistor-Anordnung eine unterschiedliche Stromtreiberfähigkeit bzw. allgemein unterschiedliche Transistoreigenschaften unterschiedlicher Fin- Feldeffekttransistoren ausgeglichen werden können. Anders ausgedrückt kann die Höhe einer Finne als prozesstechnisch einfach zugänglicher Parameter verwendet werden, um mit geringem prozesstechnischen Aufwand die elektrischen Eigenschaften eines Fin-Feldeffekttransistors einzustellen bzw. diese auf die elektrischen Eigenschaften eines anderen Fin-Feldeffekttransistors abzustimmen.A basic idea of the invention is to be seen in the fact that it has been recognized and exploited that in the case of fin field effect transistors the current flows on the side walls of the fin, and therefore by adjusting the height of the fins of different fin field effect transistors of a fin field effect transistor arrangement different current driver capability or generally different transistor properties of different fin field effect transistors can be compensated. In other words, the height of a fin can be used as a parameter that is easily accessible in terms of process technology, in order to set the electrical properties of a fin field effect transistor with little outlay on process technology or to match these to the electrical properties of another fin field effect transistor.
Die Finne ist vorzugsweise aus Halbleiter-Material (z.B. aus Silizium) gebildet, kann aber auch aus metallischem Material gebildet sein.The fin is preferably made of semiconductor material (e.g. silicon), but can also be made of metallic material.
Im Unterschied zum Stand der Technik, bei dem die Stromtreiberfähigkeit von Transistoren einer CMOS-Schaltung mittels Einsteilens der Weite der Transistoren oder einzig mittels Einsteilens der Anzahl der Finnen eines Fin- Feldeffekttransistors eingestellt wird, führt das Einstellen der Stromtreiberfähigkeit bei der erfindungsgemäßen Fin- Feldeffekttransistor-Anordnung mittels Justierens der Höhe der Finnen nicht zu einer Erhöhung der Chipfläche, da sich diese Erhöhung nur in einer Dimension senkrecht zu der Chipoberfläche auswirkt, nicht hingegen in der Oberflächenebene des Substrats. Daher ist die erfindungsgemäße Fin-Feldeffekttransistor-Anordnung für eine fortgesetzte Skalierung gut geeignet. Ferner ist es erfindungsgemäß entbehrlich, die Stromtreiberfähigkeit eines p-Kanal-Fin-Feldeffekttransistors dadurch zu erhöhen, dass die Anzahl der Finnen pro Transistor erhöht wird, wodurch wiederum die erforderliche Chipoberfläche erhöht würde.In contrast to the prior art, in which the current driver capability of transistors of a CMOS circuit is set by dividing the width of the transistors or only by dividing the number of fins of a fin field effect transistor, the setting of the current driver capability in the fin field effect transistor according to the invention Arrangement by adjusting the height of the fins does not result in an increase in the chip area, since this increase has an effect only in one dimension perpendicular to the chip surface, but not in the surface plane of the substrate. The fin field effect transistor arrangement according to the invention is therefore well suited for continued scaling. Furthermore, it is unnecessary according to the invention to increase the current driver capability of a p-channel fin field effect transistor by increasing the number of fins per transistor, which in turn would increase the required chip surface area.
Die Finnenhöhe unterschiedlicher Fin-Feldeffekttransistoren einer Fin-Feldeffekttransistor-Anordnung wird erfindungsgemäß als Parameter genutzt, die Transistoreigenschaften (Schwellenspannungen, Stromtreiberfähigkeit, etc.) zu justieren und auf die Erfordernisse einer gewünschten Anwendung anzupassen. Insbesondere können für eine CMOS-Fin-Feldeffekttransistor- Anordnung die Höhe der Finnen der n-Kanal-Fin- Feldeffekttransistoren und der p-Kanal-Fin- Feldeffekttransistoren unterschiedlich eingestellt werden, so dass beide Transistortypen die gleiche Stromtreiberfähigkeit haben. Mittels Einsteilens der Finnenhδhe lässt sich für den p-Kanal-Fin-Feldeffekttransistor somit die gleiche Stromtreiberfähigkeit herstellen wie für einen n-Kanal-Fin- Feldeffekttransistor .The fin height of different fin field effect transistors of a fin field effect transistor arrangement is used according to the invention as parameters to adjust the transistor properties (threshold voltages, current driving capability, etc.) and to adapt them to the requirements of a desired application. In particular, for a CMOS fin field effect transistor arrangement, the height of the fins of the n-channel fin field effect transistors and the p-channel fin field effect transistors can be set differently, so that both transistor types have the same current driver capability. By dividing the fin height, the same current driver capability can be established for the p-channel fin field effect transistor as for an n-channel fin field effect transistor.
Bevorzugte Weiterbildungen der Erfindung ergeben sich aus den abhängigen Ansprüchen.Preferred developments of the invention result from the dependent claims.
Bei der Fin-Feldeffekttransistor-Anordnung kann die Finne des ersten Fin-Feldeffekttransistors Dotiermaterial des p-In the fin field effect transistor arrangement, the fin of the first fin field effect transistor can dopant material of the p
Leitungstyps (z.B. Arsen, Phosphor) aufweisen und die Finne des zweiten Fin-Feldeffekttransistors entweder Dotiermaterial des ■ n-Leitungstyps (z.B. Aluminium, Bor) aufweisen oder von Dotiermaterial frei sein (bzw. lediglich geringe Mengen intrinsischer Dotierung aufweisen) . Es ist also nicht erforderlich, dass die Kanal-Bereiche von beiden Fin- Feldeffekttransistoren der Fin-Feldeffekttransistor-Anordnung dotiert sind, vielmehr lassen sich die vorteilhaften Wirkungen der Erfindung auch dann erreichen, wenn einer der Kanal-Bereiche dotiert ist und der andere entweder mitHave conductivity type (eg arsenic, phosphorus) and the fin of the second fin field effect transistor either have doping material of the ■ n conductivity type (eg aluminum, boron) or be free of doping material (or only have small amounts of intrinsic doping). It is therefore not necessary for the channel regions to be doped by both fin field effect transistors of the fin field effect transistor arrangement, rather the advantageous effects of the invention can also be achieved if one of the channel regions is doped and the other either with
Dotieratomen des entgegengesetzten Leitungstyps dotiert ist oder undotiert ist.Doping atoms of the opposite conductivity type is doped or undoped.
Daher kann bei der Fin-Feldeffekttransistor-Anordnung die Finne des ersten Fin-Feldeffekttransistors entweder Dotiermaterial des p-Leitungstyps aufweisen oder von Dotiermaterial frei sein und die Finne des zweiten Fin- Feldeffekttransistors Dotiermaterial des n-Leitungstyps aufweisen.Therefore, in the fin field-effect transistor arrangement, the fin of the first fin field-effect transistor can either have doping material of the p-conductivity type or be free of doping material and the fin of the second fin Have field effect transistor dopant of the n-type.
Allgemeiner ausgedrückt können die beiden Fin- Feldeffekttransistoren unterschiedliche Leitungstypen aufweisen, wobei die daraus resultierenden unterschiedlichen Transistoreigenschaften (v.a. Stromtreiberfähigkeiten) mittels Einstellens unterschiedlicher Finnenhδhen ausgeglichen werden können.Expressed more generally, the two fin field effect transistors can have different line types, the resulting different transistor properties (especially current driver capabilities) being able to be compensated for by setting different fin heights.
Die Fin-Feldeffekttransistor-Anordnung der Erfindung kann als CMOS-Anordnung eingerichtet sein, d.h. als Anordnung aus n- Kanal-Fin-Feldeffekttransistoren und p-Kanal-Fin- Feldeffekttransistoren, wobei mittels Justierens der Höhe der Finne der beiden Transistortypen die Stromtreiberfähigkeiten und sonstige Transistoreigenschaften aufeinander abgestimmt werden können. Hierfür wird die Höhe des Fin- Feldeffekttransistors des p-Leitungstyps in der Regel höher gewählt als die des n-Fin-Feldeffekttransistors .The fin field effect transistor arrangement of the invention can be set up as a CMOS arrangement, i.e. as an arrangement of n-channel fin field effect transistors and p-channel fin field effect transistors, the current driver capabilities and other transistor properties being able to be matched to one another by adjusting the height of the fin of the two transistor types. For this purpose, the height of the fin field-effect transistor of the p-conduction type is generally chosen to be higher than that of the n-fin field-effect transistor.
Die Höhe der Finne des ersten Fin-Feldeffekttransistors und die Höhe der Finne des zweiten Fin-Feldeffekttransistors können derart justiert sein, dass die Stromtreiberfähigkeit des ersten Fin-Feldeffekttransistors im Wesentlichen gleich der Stromtreiberfähigkeit des zweiten Fin- Feldeffekttransistors ist. Ein derart erhaltener integrierter Schaltkreis weist eine gute Qualität und reproduzierbare Eigenschaften auf .The height of the fin of the first fin field effect transistor and the height of the fin of the second fin field effect transistor can be adjusted such that the current driving ability of the first fin field effect transistor is substantially equal to the current driving ability of the second fin field effect transistor. An integrated circuit obtained in this way has good quality and reproducible properties.
Das Substrat kann ein SOI-Substrat (Silicon-on-insulator) sein. In diesem Fall können die Finnen in der oberen Silizium-Schicht eine solchen SOI-Substrats gebildet werden. Da die Finnenhöhe in diesem Fall durch die Dicke des SOI- Substrats, insbesondere der oberen Silizium-Schicht eines SOI-Substrats bestimmt ist, ist ein SOI-Substrat vorteilhaft, das unterschiedliche Top-Silizium-Dicken aufweist.The substrate can be a SOI (silicone-on-insulator) substrate. In this case, the fins can be formed in the upper silicon layer of such an SOI substrate. Since the fin height in this case is determined by the thickness of the SOI Substrate, in particular the upper silicon layer of an SOI substrate, an SOI substrate is advantageous which has different top silicon thicknesses.
Die Finne des ersten Fin-Feldeffekttransistors undZoder die Finne des zweiten Fin-Feldeffekttransistors ist oder sind vorzugsweise zumindest zum Teil auf bzw. in der oberen Silizium-Schicht des SOI-Substrats gebildet.The fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are preferably formed at least in part on or in the upper silicon layer of the SOI substrate.
Bei der Fin-Feldeffekttransistor-Anordnung der Erfindung kann oder können die Finne des ersten Fin-Feldeffekttransistors undZoder die Finne des zweiten Fin-Feldeffekttransistors in mehrere nebeneinander gebildete Halbleiter-Teilfinnen aufgeteilt sein. Dadurch kann die Stromtreiberfähigkeit des Transistors durch die Kombination zweier Maßnahmen eingestellt werden, nämlich mittels Einsteilens unterschiedlicher Finnenhöhen und mittels Vorsehens der Finne als eine Anordnung mehrerer Halbleiter-Teilfinnen. Das Realisieren einer Finne als mehrere Teilfinnen ist in [2] beschrieben. Die mehreren Halbleiter-Teilfinnen können zwischen zwei gemeinsamen Source-ZDrain-Anschlüssen des Fin- Feldeffekttransistors vorgesehen sein und im Wesentlichen parallel zueinander angeordnet sein. Somit kann eine gewünschte Stromtreiberfähigkeit eines Transistors eingestellt werden, indem zwischen der Anzahl der Teilfinnen (je weniger, desto geringer der Flächenbedarf) und der Höhe der Teilfinnen (je geringer, desto geringer die Topologie) ein für einen Anwendungsfall geeigneter Ausgleich getroffen wird.In the fin field effect transistor arrangement of the invention, the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can be divided into a plurality of semiconductor sub-fins formed side by side. As a result, the current driving ability of the transistor can be adjusted by combining two measures, namely by dividing different fin heights and by providing the fin as an arrangement of several semiconductor sub-fins. The realization of a fin as several sub-fins is described in [2]. The plurality of semiconductor partial fins can be provided between two common source ZDrain connections of the fin field effect transistor and can be arranged essentially parallel to one another. A desired current driving capability of a transistor can thus be set by balancing the number of sub-fins (the fewer, the smaller the area requirement) and the height of the sub-fins (the lower, the less the topology) suitable for an application.
Bei der Fin-Feldeffekttransistor-Anordnung gemäß dieser Ausgestaltung können die Höhe der Finne des ersten Fin- Feldeffekttransistors und die Höhe der Finne des zweiten Fin- Feldeffekttransistors und die Anzahl der Teilfinnen des ersten Fin-Feldeffekttransistors und die Anzahl der Teilfinnen des zweiten Fin-Feldeffekttransistors derart justiert sein, dass die Stromtreiberfähigkeit des ersten Fin- Feldeffekttransistors im Wesentlichen gleich derIn the case of the fin field effect transistor arrangement according to this embodiment, the height of the fin of the first fin field effect transistor and the height of the fin of the second fin Field effect transistor and the number of sub-fins of the first fin field-effect transistor and the number of sub-fins of the second fin field-effect transistor can be adjusted such that the current driver capability of the first fin field-effect transistor is substantially equal to that
Stromtreiberfähigkeit des zweiten Fin-Feldeffekttransistors ist. Mit anderen Worten wird eine gewünschte Stromtreiberfähigkeit oder sonstige Transistoreigenschaft eingestellt, indem die Finnenhδhe und die Finnenanzahl als Justierparameter verwendet werden. Vorzugsweise weist zumindest einer der Fin-Feldeffekttransistor-Anordnung mindestens zwei Teilfinnen auf.Current driving ability of the second fin field effect transistor is. In other words, a desired current driver capability or other transistor property is set by using the fin height and the number of fins as adjustment parameters. At least one of the fin field effect transistor arrangements preferably has at least two partial fins.
Im Weiteren wird das erfindungsgemäße Verfahren zum Herstellen einer Fin-Feldeffekttransistor-Anordnung beschrieben. Ausgestaltungen der Fin-Feldeffekttransistor- Anordnung gelten auch für das Verfahren zum Herstellen einer Fin-Feldeffekttransistor-Anordnung und umgekehrt.The method according to the invention for producing a fin field effect transistor arrangement is described below. Refinements of the fin field effect transistor arrangement also apply to the method for producing a fin field effect transistor arrangement and vice versa.
Im Weiteren werden insbesondere Ausgestaltungen derart beschrieben, wie Finnen unterschiedlicher Höhe der Fin- Feldeffekttransistoren realisiert werden können.In addition, configurations are described in particular such as how fins of different heights of the fin field effect transistors can be realized.
Gemäß einer Ausgestaltung kann hierfür zwischen dem Substrat und der Finne des zweiten Fin-Feldeffekttransistors eine elektrisch isolierende Schicht gebildet werden. Die Dicke der elektrisch isolierenden Schicht kann z.B. so vorgesehen werden, dass die Dicke gemeinsam mit der Höhe der Finne des zweiten Fin-Feldeffekttransistors im Wesentlichen gleich der Höhe der Finne des ersten Fin-Feldeffekttransistors ist.According to one embodiment, an electrically insulating layer can be formed for this purpose between the substrate and the fin of the second fin field effect transistor. The thickness of the electrically insulating layer can e.g. be provided such that the thickness together with the height of the fin of the second fin field effect transistor is substantially equal to the height of the fin of the first fin field effect transistor.
Dadurch können die unterschiedlichen Topologien aufgrund der unterschiedlichen Höhen der Finne des ersten und des zweiten Fin-Feldeffekttransistors ausgeglichen werden, was für eine nachfolgende Prozessierung vorteilhaft sein kann.This allows the different topologies due to the different heights of the fin of the first and second Fin field effect transistors can be compensated, which can be advantageous for subsequent processing.
Alternativ zu der beschriebenen Ausgestaltung kann auf der Finne des zweiten Fin-Feldeffekttransistors eine elektrisch isolierende Schicht gebildet werden. In diesem Fall ist die Finne des zweiten Fin-Feldeffekttransistors z.B. direkt auf dem Substrat gebildet und eine elektrisch isolierende Schicht darüber abgeschieden. Dadurch ist es möglich, mit der elektrisch isolierenden Schicht als Abstandhalter bzw. alsAs an alternative to the embodiment described, an electrically insulating layer can be formed on the fin of the second fin field effect transistor. In this case the fin of the second fin field effect transistor is e.g. formed directly on the substrate and an electrically insulating layer deposited over it. This makes it possible to use the electrically insulating layer as a spacer or as
Höhenausgleichsstruktur die unterschiedlichen Höhen der Finne der ersten und des zweiten Feldeffekttransistoren auszugleichen, und dadurch eine Schicht-Anordnung mit einer gleichmäßigeren Topologie zu erhalten. Insbesondere kann die Dicke der elektrisch isolierenden Schicht gemäß der beschriebenen Ausgestaltungen derart justiert werden, dass die elektrisch isolierende Schicht gemeinsam mit der Finne des zweiten Fin-Feldeffekttransistors eine Höhe hat, die im Wesentlichen gleich der Höhe der Finne des ersten Fin- Feldeffekttransistors ist.Height compensation structure to compensate for the different heights of the fin of the first and the second field effect transistors, and thereby to obtain a layer arrangement with a more uniform topology. In particular, the thickness of the electrically insulating layer can be adjusted in accordance with the described embodiments such that the electrically insulating layer together with the fin of the second fin field effect transistor has a height which is substantially equal to the height of the fin of the first fin field effect transistor.
Gemäß einer alternativen Ausgestaltung können die Finne des ersten Fin-Feldeffekttransistors und die Finne des zweiten Fin-Feldeffekttransistors gebildet werden, indem eine gemeinsame Halbleiter-Schicht auf dem Substrat gebildet und strukturiert wird, so dass eine die Finne des ersten Fin- Feldeffekttransistors bildende erste lateral begrenzte Schicht gebildet wird und eine zweite lateral begrenzte Schicht gebildet wird. Die Finne des zweiten Fin- Feldeffekttransistors kann dann gebildet werden, indemAccording to an alternative embodiment, the fin of the first fin field effect transistor and the fin of the second fin field effect transistor can be formed by forming and structuring a common semiconductor layer on the substrate, so that a first one laterally forming the fin of the first fin field effect transistor limited layer is formed and a second laterally limited layer is formed. The fin of the second fin field effect transistor can then be formed by
Material der zweiten lateral begrenzten Schicht entfernt wird. Anders ausgedrückt wird zum Bilden der Finne des zweiten Fin-Feldeffekttransistors Halbleitermaterial von der zweiten lateral begrenzten Schicht entfernt (beispielsweise mittels Ätzens entfernt, wobei dann die Finne des ersten Fin- Feldeffekttransistors mittels Bedeckens mit einer Hilfsstruktur vor einem Ätzen geschützt sein sollte) , wodurch die Höhe der Finne des zweiten Fin-Feldeffekttransistors gegenüber der Höhe der Finne des ersten Fin- Feldeffekttransistors verringert wird.Material of the second laterally delimited layer is removed. In other words, semiconductor material is used to form the fin of the second fin field effect transistor second laterally delimited layer (for example removed by etching, in which case the fin of the first fin field effect transistor should be protected from etching by covering with an auxiliary structure), as a result of which the height of the fin of the second fin field effect transistor compared to the height of the fin of the first Fin field effect transistor is reduced.
Gemäß einem anderen alternativen Verfahren wird die Finne des ersten Fin-Feldeffekttransistors und die Finne des zweiten Fin-Feldeffekttransistors aus einer Oberflächen- Halbleiterschicht eines planaren Substrats gebildet, welche Oberflächen-Halbleiterschicht im Bereich des ersten Fin- Feldeffekttransistors eine größere Dicke aufweist als in dem Bereich des zweiten Fin-Feldeffekttransistors. Hierfür kann die aus [1], insbesondere aus Fig.6 von [1], bekannte Schichtenfolge als Ausgangssubstrat verwendet werden. Demgemäß wird eine Isolator-Schicht mit einer gestuften Oberfläche vorgesehen, wobei auf der gestuften Oberfläche eine Halbleiter-Schicht mit unterschiedlichen Dicken vorgesehen ist. Indem der erste Fin-Feldeffekttransistor (jener mit der höheren Finne) in einem Halbleiterbereich des Substrats gemäß [1] gebildet wird, in welcher die Halbleiter- Schicht eine größere Dicke aufweist, und indem die Finne des zweiten Fin-Feldeffekttransistors (jener mit der niedrigeren Finne) in einem Bereich des Substrats [1] gebildet wird, in welchem die Halbleiter-Schicht eine geringere Dicke aufweist, ist eine Fin-Feldeffekttransistor-Anordnung fertigbar, die eine geringe Oberflächentopologie aufweist .According to another alternative method, the fin of the first fin field effect transistor and the fin of the second fin field effect transistor are formed from a surface semiconductor layer of a planar substrate, which surface semiconductor layer has a greater thickness in the region of the first fin field effect transistor than in the region of the second fin field effect transistor. For this, the layer sequence known from [1], in particular from FIG. 6 of [1], can be used as the starting substrate. Accordingly, an insulator layer with a stepped surface is provided, a semiconductor layer with different thicknesses being provided on the stepped surface. By forming the first fin field effect transistor (the one with the higher fin) in a semiconductor region of the substrate according to [1], in which the semiconductor layer has a greater thickness, and by the fin of the second fin field effect transistor (the one with the lower Fin) is formed in a region of the substrate [1] in which the semiconductor layer has a smaller thickness, a fin field effect transistor arrangement can be manufactured which has a low surface topology.
Als Substrat kann ein SOI-Substrat (Silicon-on-insulator) verwendet werden, das insbesondere teilweise oder vollständig an Ladungsträgern verarmt sein kann undZoder ein Dünnschicht- SOI-Substrat sein kann.An SOI substrate (silicone-on-insulator) can be used as the substrate, in particular partially or completely may be depleted of carriers and may be Z or a thin film SOI substrate.
Die Finne des ersten Fin-Feldeffekttransistors und Zoder die Finne des zweiten Fin-Feldeffekttransistors kann oder können zumindest zum Teil aus der oberen Silizium-Schicht des SOI- Substrats gebildet werden.The fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor can or can be at least partially formed from the upper silicon layer of the SOI substrate.
In die Finne des ersten Fin-Feldeffekttransistors undZoder in die Finne des zweiten Fin-Feldeffekttransistors kannIn the fin of the first fin field effect transistor and Zoder in the fin of the second fin field effect transistor
Dotiermaterial eingebracht werden. Dieses Dotiermaterial kann in jedem der Fin-Feldeffekttransistoren Dotiermaterial des p- Leitungstyps (zum Beispiel Arsen oder Phosphor) oder des n- Leitungstyps (zum Beispiel Aluminium oder Bor) sein. Dadurch kann eine CMOS-Anordnung geschaffen werden oder eine sonstige Schaltkreis-Anordnung, in der sowohl p-Kanal-Transistoren als auch n-Kanal-Transistoren mit aufeinander anpassbaren Transistoreigenschaften enthalten sind.Doping material can be introduced. This doping material in each of the fin field effect transistors can be doping material of the p-conductivity type (for example arsenic or phosphorus) or of the n-conductivity type (for example aluminum or boron). In this way, a CMOS arrangement or another circuit arrangement can be created, in which both p-channel transistors and n-channel transistors with mutually adaptable transistor properties are contained.
Das Dotiermaterial kann insbesondere unter Verwendung des Plasma Immersion Ion Implantation Verfahrens, das Rapid Vapor-Phase Doping Verfahrens oder des Solid Phase Diffusion Verfahrens eingebracht werden. Diese Verfahren eignen sich besonders als Dotierverfahren zum Dotieren von Finnen, insbesondere von Finnen einer großen Höhe.The doping material can in particular be introduced using the plasma immersion ion implantation method, the rapid vapor phase doping method or the solid phase diffusion method. These methods are particularly suitable as doping methods for doping fins, in particular fins of great height.
Ausführungsbeispiele der Erfindung sind in den Figuren dargestellt und werden im Weiteren näher erläutert .Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.
Es zeigen:Show it:
Figuren 1A und 1B Draufsichten eines n-MOS-Transistors und eines p-MOS-Transistors gemäß dem Stand der Technik, Figuren IC und 1D Draufsichten eines n-MOS-Fin- Feldeffekttransistors und eines p-MOS-Fin- Feldeffekttransistors, jeweils mit einer Mehrzahl von Teilfinnen, gemäß dem Stand der Technik,1A and 1B are top views of an n-MOS transistor and a p-MOS transistor according to the prior art, Figures IC and 1D top views of an n-MOS fin field effect transistor and a p-MOS fin field effect transistor, each with a plurality of sub-fins, according to the prior art,
Figuren 2A und 2B perspektivische Ansichten eines n-MOS-Fin- Feldeffekttransistors und eines p-MOS-Fin- Feldeffekttransistors gemäß einem Ausführungsbeispiel der Erfindung,2A and 2B are perspective views of an n-MOS fin field effect transistor and a p-MOS fin field effect transistor according to an embodiment of the invention,
Figur 3 eine Querschnittsansicht einer Fin- Feldeffekttransistor-Anordnung gemäß einem Ausführungsbeispiel der Erfindung,FIG. 3 shows a cross-sectional view of a fin field effect transistor arrangement according to an exemplary embodiment of the invention,
Figur 4 eine Querschnittsansicht einer Fin- Feldeffekttransistor-Anordnung gemäß einem anderen Ausführungsbeispiel der Erfindung,FIG. 4 shows a cross-sectional view of a fin field effect transistor arrangement according to another exemplary embodiment of the invention,
Figur 5 eine Querschnittsansicht einer Fin- Feldeffekttransistor-Anordnung gemäß noch einem anderen Ausführungsbeispiel der Erfindung.Figure 5 is a cross-sectional view of a fin field effect transistor arrangement according to yet another embodiment of the invention.
Gleiche oder ähnliche Komponenten in unterschiedlichen Figuren sind mit gleichen Bezugsziffern versehen.The same or similar components in different figures are provided with the same reference numbers.
Die Darstellungen in den Figuren sind schematisch und nicht maßstäblich.The representations in the figures are schematic and not to scale.
Im Weiteren werden bezugnehmend auf Fig.2A, Fig.2B ein n-MOS-2A, FIG. 2B, an n-MOS
Fin-Feldeffekttransistor 200 und ein p-MOS-Fin- Feldeffekttransistor 210 beschrieben, welche in einer erfindungsgemäßen Fin-Feldeffekttransistor-Anordnung und in gemeinsamen Substrat integriert sind. Die Fin-Feldeffekttransistor-Anordnung aus Fig.2A, Fig.2B, welche den n-MOS-Fin-Feldeffekttransistor 200 und den p-MOS- Fin-Feldeffekttransistor 210 enthält, weist ein Silizium- Substrat 220 auf, auf welchem eine Siliziumoxid-Schicht 221 gebildet ist. Obgleich in Fig.2A, Fig.2B Transistoren 200, 210 separat dargestellt sind, sind beide Fin- Feldeffekttransistoren 200, 210 in demselben Substrat 220 monolithisch integriert.Fin field effect transistor 200 and a p-MOS fin field effect transistor 210 are described, which are integrated in a fin field effect transistor arrangement according to the invention and in a common substrate. 2A, 2B, which contains the n-MOS fin field effect transistor 200 and the p-MOS fin field effect transistor 210, has a silicon substrate 220 on which a silicon oxide Layer 221 is formed. Although transistors 200, 210 are shown separately in FIGS. 2A, 2B, both fin field effect transistors 200, 210 are monolithically integrated in the same substrate 220.
Der n-MOS-Fin-Feldeffekttransistor 200 enthält eine Silizium- Finne der Höhe hx. In der Silizium-Finne des n-MOS-Fin- Feldeffekttransistors 200 ist ein erster Source-ZDrain- Bereich 201 und ein zweiter Source-ZDrain-Bereich 202 gebildet. Zwischen dem ersten Source-ZDrain-Bereich 201 und dem zweiten Source-ZDrain-Bereich 202 ist ein Kanal-Bereich 203 gebildet, dessen elektrische Leitf higkeit mittels eines Gate-Bereichs 204 steuerbar ist, welcher über der Silizium- Finne gebildet ist. Zwischen dem Gate-Bereich 204 und der Silizium-Finne ist eine Gate-isolierende Schicht (nicht gezeigt) angeordnet.The n-MOS fin field effect transistor 200 contains a silicon fin of height h x . A first source ZDrain region 201 and a second source ZDrain region 202 are formed in the silicon fin of the n-MOS fin field effect transistor 200. A channel region 203 is formed between the first source Z-drain region 201 and the second source Z-drain region 202, the electrical conductivity of which can be controlled by means of a gate region 204, which is formed above the silicon fin. A gate insulating layer (not shown) is arranged between the gate region 204 and the silicon fin.
Der in Fig.2B gezeigte p-MOS-Fin-Feldeffekttransistor 210 enthält eine Silizium-Finne der Höhe h2. In der Silizium- Finne des p-MOS-Fin-Feldeffekttransistors 210 sind ein erster Source-ZDrain-Bereich 211 und ein zweiter Source-ZDrain- Bereich 212 als implantierte Bereiche der Finne gebildet, wobei zwischen den Source-ZDrain-Bereichen 211, 212 ein Kanal-Bereich 213 angeordnet ist. Die elektrische Leitfähigkeit des Kanal-Bereichs 213 ist mittels Anlegens eines elektrischen Signals an einem Gate-Bereich 214 steuerbar, welcher von dem Kanal-Bereich mittels einer Gateisolierenden Schicht (nicht gezeigt) elektrisch isoliert ist. Indem die Höhe der Silizium-Finne des n-MOS-Fin- Feldeffekttransistors 200 geringer vorgesehen wird als bei dem p-MOS-Fin-Feldeffekttransistor 210 (hχ<h2) , sind die Stromtreiberfähigkeiten der Transistoren 200, 210 identisch. Im Unterschied zu den herkömmlichen Anordnungen in Fig.lA, Fig.lB bzw. in Fig.2A, Fig.2B führt die Anpassung der Stromtreiberfähigkeiten der Transistoren 200, 210 nicht zu einer Erhöhung des Platzbedarfs der Transistoren 200, 210 auf dem Silizium-Substrat 220, da lediglich in einer Dimension senkrecht zur Substratoberfläche unterschiedliche Dimensionen der Bauelemente (nämlich der Silizium-Finnen) erforderlich sind. Somit ist eine Optimierung der erforderlichen Layout- Fläche bei der erfindungsgemäßen CMOS-Fin- Feldeffekttransistor-Anordnung aus Fig.2A, Fig.2B erreicht.The p-MOS fin field effect transistor 210 shown in FIG. 2B contains a silicon fin of height h 2 . In the silicon fin of the p-MOS fin field effect transistor 210, a first source ZDrain region 211 and a second source ZDrain region 212 are formed as implanted regions of the fin, between the source ZDrain regions 211, 212 a channel region 213 is arranged. The electrical conductivity of the channel region 213 can be controlled by applying an electrical signal to a gate region 214 which is electrically insulated from the channel region by means of a gate insulating layer (not shown). By making the height of the silicon fin of the n-MOS fin field effect transistor 200 lower than that of the p-MOS fin field effect transistor 210 (hχ <h 2 ), the current driving capabilities of the transistors 200, 210 are identical. In contrast to the conventional arrangements in FIG. 1A, FIG. 1B or in FIG. 2A, FIG. 2B, the adaptation of the current driver capabilities of the transistors 200, 210 does not lead to an increase in the space requirement of the transistors 200, 210 on the silicon substrate 220, since different dimensions of the components (namely the silicon fins) are required only in one dimension perpendicular to the substrate surface. An optimization of the required layout area is thus achieved in the inventive CMOS fin field effect transistor arrangement from FIGS. 2A, 2B.
Im Weiteren wird bezugnehmend auf Fig.3 eine Fin- Feldeffekttransistor-Anordnung 300 gemäß einem Ausführungsbeispiel der Erfindung beschrieben.A fin field effect transistor arrangement 300 according to an exemplary embodiment of the invention is described below with reference to FIG.
Die Fin-Feldeffekttransistor-Anordnung 300 ist in einemThe fin field effect transistor arrangement 300 is in one
Silizium-Substrat 301 integriert, auf dem eine Siliziumoxid- Schicht 302 gebildet ist. Auf einem ersten Oberflächenbereich der Fin-Feldeffekttransistor-Anordnung 300, nämlich in einem n-MOS-Fin-Feldeffekttransistor-Bereich 305, ist eine erste Silizium-Finne einer Höhe hx gebildet, die geringer ist als die Höhe h2 einer zweiten Silizium-Finne 304 in einem p-MOS- Fin-Feldeffekttransistor-Bereich 306. Die Fin- Feldeffekttransistor-Anordnung 300 ist auf bzw. in einem SOI- Substrat (Silicon-on-insulator) gebildet. Der Gate-Bereich, die Gate-isolierende Schicht und die Source-ZDrain-Bereiche der Fin-Feldeffekttransistoren der Fin- Feldeffekttransistoren-Anordnung 300 sind in Fig.3 nicht gezeigt . Die Fin-Feldeffekttransistor-Anordnung 300 wird gebildet, indem das SOI-Substrat einem Lithographie- und einem Ätzverfahren unterzogen wird, so dass aus der oberen Silizium-Schicht des SOI-Substrats (das heißt der Silizium- Schicht, die oberhalb der Siliziumoxid-Schicht 302 angeordnet war) eine erste lateral begrenzte Schichtenfolge und eine zweite lateral begrenzte Schichtenfolge gebildet werden. Die erste lateral begrenzte Schichtenfolge bildet die zweite Silizium-Finne 304. Um Silizium-Finnen 303, 304 unterschiedlicher Höhen (hι<h2) zu erreichen, wird in einem nachfolgenden Verfahrensschritt der p-MOS-Fin- Feldeffekttransistor-Bereich 306 mit Photoresistmaterial bedeckt und so vor einem Entfernen von Siliziummaterial von der zweiten Silizium-Finne 304 geschützt. Nachfolgend wird die zweite lateral begrenzte Schichtenfolge einem Ätzverfahren unterzogen, wodurch die zweite lateral begrenzte Schichtenfolge derart zurückgeätzt wird, dass dadurch die erste Silizium-Finne 303 mit einer geringeren Höhe hi als die Silizium-Finne 304 (Höhe h2) gebildet wird. Anders ausgedrückt wird eine niedrigere Siliziumhöhe mittels Rückätzens von Silizium erreicht.Integrated silicon substrate 301, on which a silicon oxide layer 302 is formed. A first silicon fin of a height h x , which is less than the height h 2 of a second silicon, is formed on a first surface region of the fin field effect transistor arrangement 300, namely in an n-MOS fin field effect transistor region 305. Fin 304 in a p-MOS fin field effect transistor region 306. The fin field effect transistor arrangement 300 is formed on or in an SOI substrate (silicon-on-insulator). The gate region, the gate insulating layer and the source Zdrain regions of the fin field effect transistors of the fin field effect transistor arrangement 300 are not shown in FIG. 3. The fin field effect transistor arrangement 300 is formed by subjecting the SOI substrate to a lithography and an etching process, so that the top silicon layer of the SOI substrate (that is to say the silicon layer that lies above the silicon oxide layer) 302) a first laterally delimited layer sequence and a second laterally delimited layer sequence are formed. The second laterally delimited layer sequence forms the second silicon fin 304. In order to achieve silicon fins 303, 304 of different heights (h 1 <h 2 ), the p-MOS fin field effect transistor region 306 is covered with photoresist material in a subsequent method step and so protected from removal of silicon material from the second silicon fin 304. The second laterally delimited layer sequence is subsequently subjected to an etching process, as a result of which the second laterally delimited layer sequence is etched back in such a way that the first silicon fin 303 is formed with a lower height hi than the silicon fin 304 (height h 2 ). In other words, a lower silicon height is achieved by etching back silicon.
Im Weiteren wird bezugnehmend auf Fig.4 eine Fin- Feldeffekttransistor-Anordnung 400 gemäß einem anderen Ausführungsbeispiel der Erfindung beschrieben.A fin field effect transistor arrangement 400 according to another exemplary embodiment of the invention is described below with reference to FIG.
Die in Fig.4 gezeigte Fin-Feldeffekttransistor-Anordnung 400 unterscheidet sich von der in Fig.3 gezeigten Fin- Feldeffekttransistor-Anordnung 300 dadurch, dass zusätzlich auf der ersten Silizium-Finne 303 eine Siliziumoxid-Struktur 401 aufgebracht ist. Diese zusätzliche Siliziumoxid-Struktur 401, welche alternativ auch aus Siliziumnitrid-Material hergestellt werden kann, bewirkt, dass in dem p-MOS-Fin- Feldeffekttransistor-Bereich 305 dieselbe Topologie (d.h. dieselbe Oberflächenstruktur) erreicht ist wie in dem p-MOS- Fin-Feldeffekttransistor-Bereich 306. Dies bewirkt Vorteile bei nachfolgenden Lithographie- und Planarisierungsschritten.The fin field effect transistor arrangement 400 shown in FIG. 4 differs from the fin field effect transistor arrangement 300 shown in FIG. 3 in that a silicon oxide structure 401 is additionally applied to the first silicon fin 303. This additional silicon oxide structure 401, which alternatively also consists of silicon nitride material has the effect that the same topology (ie the same surface structure) is achieved in the p-MOS fin field effect transistor region 305 as in the p-MOS fin field effect transistor region 306. This brings about advantages in subsequent lithography and planarization steps.
Im Weiteren wird bezugnehmend auf Fig.5 eine Fin- Feldeffekttransistor-Anordnung 500 gemäß noch einem anderen Ausführungsbeispiel der Erfindung beschrieben.A fin field effect transistor arrangement 500 according to yet another exemplary embodiment of the invention is described below with reference to FIG.
Die in Fig.5 gezeigte Fin-Feldeffekttransistor-Anordnung 500 unterscheidet sich von den in Fig.3 und Fig.4 gezeigten Fin- Feldeffekttransistor-Anordnungen 300, 400 dadurch, dass die Fin-Feldeffekttransistor-Anordnung 500 ausgehend von einem Substrat gebildet wird, wie es beispielsweise in Fig.6 von [1] beschrieben ist. Dort ist ein Substrat mit einer Trägerschicht und einer Isolator-Schicht mit einer gestuften Oberfläche mit unterschiedlichen Oberflächenbereichen auf der Trägerschicht beschrieben, wobei auf der gestuften Oberfläche der Isolator-Schicht eine Halbleiter-Schicht gebildet ist, welche in unterschiedlichen Oberflächenbereichen eine unterschiedliche Halbleiterdicke aufweist, so dass im Ergebnis ein Substrat mit planarer Oberfläche gebildet ist. Als Trägerschicht dient bei der Fin-Feldeffekttransistor- Anordnung 500 das Silizium-Substrat 301. Die gestufteThe fin field effect transistor arrangement 500 shown in FIG. 5 differs from the fin field effect transistor arrangements 300, 400 shown in FIGS. 3 and 4 in that the fin field effect transistor arrangement 500 is formed starting from a substrate, as described for example in Fig. 6 of [1]. There is described a substrate with a carrier layer and an insulator layer with a stepped surface with different surface areas on the carrier layer, a semiconductor layer having a different semiconductor thickness in different surface areas being formed on the stepped surface of the insulator layer that as a result a substrate with a planar surface is formed. The silicon substrate 301 serves as the carrier layer in the fin field effect transistor arrangement 500. The stepped one
Oberfläche wird dadurch gebildet, dass in dem n-MOS-Fin- Feldeffektransistor-Bereich 305 eine Siliziumoxid-Struktur vorhanden ist, die aus der Siliziumoxid-Schicht 302 und der darauf gebildeten Zusatz-Siliziumoxid-Schicht 501 gebildet ist. In dem p-MOS-Fin-Feldeffekttransistor-Bereich 306 ist die Zusatz-Siliziumoxid-Schicht 501 nicht vorgesehen, so dass die Siliziumoxid-Schicht in diesem Bereich einzig von der Siliziumoxid-Schicht 302 gebildet ist. Das in Fig.6 von [1] gezeigte Substrat enthält eine Halbleiter-Schicht, welche mit einer planaren Oberfläche abschließt .- Diese Halbleiter- Schicht ist in Fig.5 nur noch in Form der ersten Silizium- Finne 303 und der zweiten Silizium-Finne 304 zu erkennen. Unter Verwendung eines Lithographie- und eines Ätzverfahrens wird ausgehend von Fig.6 von [1] die in unterschiedlichen Bereichen des Substrats unterschiedliche Halbleiter- Schichtdicke derart strukturiert, dass dadurch die erste Silizium-Finne 303 bzw. die zweite Silizium-Finne 304 gebildet werden, welche unterschiedliche Höhen hx<h2 aufweisen, deren obere Endabschnitte jedoch auf der gleichen Höhe angeordnet sind.Surface is formed by the fact that in the n-MOS fin field effect transistor region 305 there is a silicon oxide structure which is formed from the silicon oxide layer 302 and the additional silicon oxide layer 501 formed thereon. The additional silicon oxide layer 501 is not provided in the p-MOS fin field effect transistor region 306, so that the silicon oxide layer in this region is formed solely by the silicon oxide layer 302. The in Fig. 6 of [1] The substrate shown contains a semiconductor layer which terminates with a planar surface. This semiconductor layer can only be seen in FIG. 5 in the form of the first silicon fin 303 and the second silicon fin 304. Using a lithography and an etching method, starting from FIG. 6 of [1], the semiconductor layer thickness which is different in different areas of the substrate is structured such that the first silicon fin 303 and the second silicon fin 304 are formed thereby, which have different heights h x <h 2 , but whose upper end sections are arranged at the same height.
Somit ist eine Fin-Feldeffekttransistor-Anordnung 500 bereitgestellt, bei welcher der n-MOS-Fin- Feldeffekttransistor und der p-MOS-Fin-Feldeffekttransistor im Wesentlichen dieselbe Höhe aufweisen. A fin field effect transistor arrangement 500 is thus provided, in which the n-MOS fin field effect transistor and the p-MOS fin field effect transistor have essentially the same height.
In diesem Dokument sind folgende Veröffentlichungen zitiert : The following publications are cited in this document:
[2] Anil, KG et al . (2003) 'Layout Density Analysis of FinFETs', ESSDERC 2003, 16.-18.09.2003 Estoril, Portugal;[2] Anil, KG et al. (2003) 'Layout Density Analysis of FinFETs', ESSDERC 2003, September 16-18, 2003 Estoril, Portugal;
[3] US 6,413,802 Bl; [3] US 6,413,802 B1;
[5] US 4,996,574. [5] US 4,996,574.
BezugszeichenlisteLIST OF REFERENCE NUMBERS
100 n-MOS-Feldeffekttransistor 101 erster Source-ZDrain-Bereich 102 zweiter Source-ZDrain-Bereich 103 Kanal-Bereich 104 Gate-Bereich 110 p-MOS-Feldeffekttransistor 111 erster Source-ZDrain-Bereich 112 zweiter Source-ZDrain-Bereich 113 Kanal-Bereich 114 Gate-Bereich 120 n-MOS-Fin-Feldeffekttransistor 121 erster Source-ZDrain-Bereich 122 zweiter Source-ZDrain-Bereich 123 Kanal-Bereich 124 Gate-Bereich 125 erste Silizium-Teilfinne 126 erste Silizium-Teilfinne 130 p-MOS-Fin-Feldeffekttransistor 131 erster Source-ZDrain-Bereich 132 zweiter Source-ZDrain-Bereich 133 Kanal-Bereich 134 Gate-Bereich 135 Silizium-Teilfinnen 200 n-MOS-Fin-Feldeffekttransistor 201 erster Source-ZDrain-Bereich 202 zweiter Source-ZDrain-Bereich 203 Kanal-Bereich 204 Gate-Bereich 210 p-MOS-Fin-Feldeffekttransistor 211 erster Source-ZDrain-Bereich 212 zweiter Source-ZDrain-Bereich 213 Kanal-Bereich 214 Gate-Bereich 220 Silizium-Substrat100 n-MOS field effect transistor 101 first source ZDrain region 102 second source ZDrain region 103 channel region 104 gate region 110 p-MOS field effect transistor 111 first source ZDrain region 112 second source ZDrain region 113 channel Region 114 gate region 120 n-MOS fin field effect transistor 121 first source ZDrain region 122 second source ZDrain region 123 channel region 124 gate region 125 first silicon partial fin 126 first silicon partial fin 130 p-MOS -Fin field effect transistor 131 first source ZDrain region 132 second source ZDrain region 133 channel region 134 gate region 135 silicon partial fins 200 n-MOS fin field effect transistor 201 first source ZDrain region 202 second source ZDrain Region 203 channel region 204 gate region 210 p-MOS fin field effect transistor 211 first source ZDrain region 212 second source ZDrain region 213 channel region 214 gate region 220 silicon substrate
221 Siliziumoxid-Schicht221 silicon oxide layer
300 Fin-Feldeffekttransistor-Anordnung 301 Silizium-Substrat 302 Siliziumoxid-Schicht300 fin field effect transistor arrangement 301 silicon substrate 302 silicon oxide layer
303 erste Silizium-Finne303 first silicon fin
304 zweite Silizium-Finne304 second silicon fin
305 n-MOS-Fin-Feldeffekttransistor-Bereich 306 p-MOS-Fin-Feldef ekttransistor-Bereich305 n-MOS fin field effect transistor area 306 p-MOS fin field effect transistor area
400 Fin-Feldeffekttransistor-Anordnung400 fin field effect transistor arrangement
401 Siliziumoxid-Struktur401 silicon oxide structure
500 Fin-Feldeffekttransistor-Anordnung500 fin field effect transistor arrangement
501 Zusatz-Siliziumoxid-Schicht 501 additional silicon oxide layer

Claims

Patentansprüche: claims:
1 . Fin-Feldef fekttransistor-Anordnung1 . Fin field effect transistor arrangement
• mit einem Substrat ; • mit einem ersten Fin-Feldeffekttransistor auf undZoder in dem Substrat, der eine Finne aufweist, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain-Bereich gebildet ist, und über welcher der Gate-Bereich gebildet ist; • mit einem lateral neben dem ersten Fin- Feldeffekttransistor angeordneten zweiten Fin- Feldeffekttransistor auf undZoder in dem Substrat, der eine Finne aufweist, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain- Bereich gebildet ist, und über welcher der Gate-Bereich gebildet ist;• with a substrate; With a first fin field effect transistor on andZ or in the substrate, which has a fin in which the channel region is formed between the first and second source Zdrain regions and over which the gate region is formed; With a second fin field effect transistor arranged laterally next to the first fin field effect transistor on andZ or in the substrate, which has a fin in which the channel region is formed between the first and the second source Zdrain region, and over which the Gate area is formed;
• wobei die Höhe der Finne des ersten Fin- Feldeffekttransistors größer ist als die Höhe der Finne des zweiten Fin-Feldeffekttransistors.• The height of the fin of the first fin field effect transistor is greater than the height of the fin of the second fin field effect transistor.
2. Fin-Feldeffekttransistor-Anordnung nach Anspruch 1, bei welcher die Finne des ersten Fin-Feldeffekttransistors Dotiermaterial des p-Leitungstyps aufweist und die Finne des zweiten Fin-Feldeffekttransistors entweder Dotiermaterial des n-Leitungstyps aufweist oder von Dotiermaterial im Wesentlichen frei ist.2. Fin field effect transistor arrangement according to claim 1, wherein the fin of the first fin field effect transistor comprises doping material of the p-conduction type and the fin of the second fin field effect transistor either comprises doping material of the n conduction type or is essentially free of doping material.
3. Fin-Feldeffekttransistor-Anordnung nach Anspruch 1, bei welcher die Finne des ersten Fin-Feldeffekttransistors Dotiermaterial des p-Leitungstyps aufweist oder von3. Fin field effect transistor arrangement according to claim 1, wherein the fin of the first fin field effect transistor comprises doping material of the p-conductivity type or of
Dotiermaterial im Wesentlichen frei ist und bei der die Finne des zweiten Fin-Feldeffekttransistors Dotiermaterial des n- Leitungstyps aufweist.Doping material is essentially free and in which the fin of the second fin field effect transistor has doping material of the n-conductivity type.
4. Fin-Feldeffekttransistor-Anordnung nach einem der Ansprüche 1 bis 3 , eingerichtet als CMOS-Anordnung. 4. Fin field effect transistor arrangement according to one of claims 1 to 3, set up as a CMOS arrangement.
5. Fin-Feldeffekttransistor-Anordnung nach einem der Ansprüche 1 bis 4, bei der die Höhe der Finne des ersten Fin- Feldeffekttransistors und die Höhe der Finne des zweiten Fin- Feldeffekttransistors derart justiert sind, dass die Stromtreiberfähigkeit des ersten Fin-Feldeffekttransistors im Wesentlichen gleich der Stromtreiberfähigkeit des zweiten Fin-Feldeffekttransistors ist.5. Fin field effect transistor arrangement according to one of claims 1 to 4, wherein the height of the fin of the first fin field effect transistor and the height of the fin of the second fin field effect transistor are adjusted such that the current driving ability of the first fin field effect transistor essentially is equal to the current driving ability of the second fin field effect transistor.
6. Fin-Feldeffekttransistor-Anordnung nach einem der Ansprüche 1 bis 5, bei der das Substrat ein Silicon-on-insuiator-Substrat ist.6. Fin field effect transistor arrangement according to one of claims 1 to 5, wherein the substrate is a silicone-on-insuiator substrate.
7. Fin-Feldeffekttransistor-Anordnung nach Anspruch 6, bei der die Finne des ersten Fin-Feldeffekttransistors undZoder die Finne des zweiten Fin-Feldeffekttransistors zumindest zum Teil aus der oberen Silizium-Schicht des Silicon-on-insulator-Substrats gebildet ist oder sind.The fin field effect transistor arrangement according to claim 6, wherein the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are formed at least in part from the upper silicon layer of the silicon-on-insulator substrate.
8. Fin-Feldeffekttransistor-Anordnung nach einem der Ansprüche 1 bis 7, bei der die Finne des ersten Fin-Feldeffekttransistors undZoder die Finne des zweiten Fin-Feldeffekttransistors in mehrere nebeneinander gebildete Halbleiter-Teilfinnen aufgeteilt ist oder sind.Fin field effect transistor arrangement according to one of Claims 1 to 7, in which the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are divided into a plurality of semiconductor partial fins formed next to one another.
9. Fin-Feldeffekttransistor-Anordnung nach Anspruch 8, bei der die Höhe der Finne des ersten Fin- Feldeffekttransistors und die Höhe der Finne des zweiten Fin- Feldeffekttransistors und die Anzahl der Teilfinnen des ersten Fin-Feldeffekttransistors und die Anzahl der Teilfinnen des zweiten Fin-Feldeffekttransistors derart justiert sind, dass die Stromtreiberfähigkeit des ersten Fin- Feldeffekttransistors im Wesentlichen gleich der9. fin field effect transistor arrangement according to claim 8, wherein the height of the fin of the first fin field effect transistor and the height of the fin of the second fin field effect transistor and the number of fins of the first fin field effect transistor and the number of fins of the second fin -Field effect transistors are adjusted such that the current driving ability of the first fin-field effect transistor is substantially equal to that
Stromtreiberfähigkeit des zweiten Fin-Feldeffekttransistors ist. Current driving ability of the second fin field effect transistor is.
10. Verfahren zum Herstellen einer Fin-Feldeffekttransistor- Anordnung, bei dem • ein erster Fin-Feldeffekttransistor auf undZoder in einem Substrat gebildet wird und mit einer Finne gebildet wird, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain-Bereich gebildet wird, und über welcher der Gate-Bereich gebildet wird; • ein lateral neben dem ersten Fin-Feldeffekttransistor angeordneten zweiter Fin-Feldeffekttransistor auf undZoder in dem Substrat gebildet wird und mit einer Finne gebildet wird, in welcher der Kanal-Bereich zwischen dem ersten und dem zweiten Source-ZDrain- Bereich gebildet wird, und über welcher der Gate-Bereich gebildet wird; • wobei die Höhe der Finne des ersten Fin- Feldeffekttransistors größer vorgesehen wird als die Höhe der Finne des zweiten Fin-Feldeffekttransistors.10. A method for producing a fin field effect transistor arrangement, in which a first fin field effect transistor is formed on and Z or in a substrate and is formed with a fin in which the channel region between the first and the second source Z drain Area is formed, and over which the gate area is formed; A second fin field effect transistor arranged laterally next to the first fin field effect transistor is formed on andZ or in the substrate and is formed with a fin in which the channel region is formed between the first and the second source Zdrain region and above which the gate area is formed; • The height of the fin of the first fin field effect transistor is provided to be greater than the height of the fin of the second fin field effect transistor.
11. Verfahren nach Anspruch 10, bei dem zwischen dem Substrat und der Finne des zweiten Fin- Feldeffekttransistors eine elektrisch isolierende Schicht gebildet wird.11. The method of claim 10, wherein an electrically insulating layer is formed between the substrate and the fin of the second fin field effect transistor.
12. Verfahren nach Anspruch 11, bei dem auf der Finne des zweiten Fin-Feldeffekttransistors eine elektrisch isolierende Schicht gebildet wird.12. The method of claim 11, wherein an electrically insulating layer is formed on the fin of the second fin field effect transistor.
13. Verfahren nach Anspruch 10 oder 11, bei dem die Dicke der elektrisch isolierenden Schicht derart justiert wird, dass die elektrisch isolierende Schicht gemeinsam mit der Finne des zweiten Fin-Feldeffekttransistors eine Höhe hat, die im Wesentlichen gleich der Höhe der Finne des ersten Fin-Feldeffekttransistors ist.13. The method of claim 10 or 11, wherein the thickness of the electrically insulating layer is adjusted such that the electrically insulating layer together with the fin of the second fin field effect transistor has a height which is substantially equal to the height of the fin of the first fin Field effect transistor is.
14. Verfahren nach Anspruch 10, bei dem die Finne des ersten Fin-Feldeffekttransistors und die Finne des zweiten Fin-Feldeffekttransistors gebildet werden, indem14. The method according to claim 10, in which the fin of the first fin field effect transistor and the fin of the second fin field effect transistor are formed by
• eine gemeinsame Halbleiter-Schicht auf dem Substrat gebildet und strukturiert wird, womit eine die Finne des ersten Fin-Feldeffekttransistors bildende erste lateral begrenzte Schicht gebildet wird und eine zweite lateral begrenzte Schicht gebildet wird;A common semiconductor layer is formed and structured on the substrate, with which a first laterally delimited layer forming the fin of the first fin field effect transistor is formed and a second laterally delimited layer being formed;
• die Finne des zweiten Fin-Feldeffekttransistors gebildet wird, indem Material der zweiten lateral begrenzten Schicht entfernt wird.The fin of the second fin field effect transistor is formed by removing material from the second laterally delimited layer.
15. Verfahren nach Anspruch 10, bei dem die Finne des ersten Fin-Feldeffekttransistors und die Finne des zweiten Fin-Feldeffekttransistors aus einer Oberflächen-Halbleiter-Schicht eines planaren Substrats gebildet werden, welche Oberflächen-Halbleiter-Schicht in dem Bereich des ersten Fin-Feldeffekttransistors eine größere Dicke aufweist als in dem Bereich des zweiten Fin- Feldeffekttransistors.15. The method of claim 10, wherein the fin of the first fin field effect transistor and the fin of the second fin field effect transistor are formed from a surface semiconductor layer of a planar substrate, which surface semiconductor layer in the region of the first fin Field effect transistor has a greater thickness than in the region of the second fin field effect transistor.
16. Verfahren nach einem der Ansprüche 10 bis 15, bei dem als Substrat ein Silicon-on-insulator-Substrat verwendet wird.16. The method according to any one of claims 10 to 15, in which a silicone-on-insulator substrate is used as the substrate.
17. Verfahren nach Anspruch 16, bei dem die Finne des ersten Fin-Feldeffekttransistors undZoder die Finne des zweiten Fin-Feldeffekttransistors zumindest zum Teil aus der oberen Silizium-Schicht des Silicon-on-insulator-Substrats gebildet wird oder werden.The method of claim 16, wherein the fin of the first fin field effect transistor and Z or the fin of the second fin field effect transistor is or are formed at least in part from the top silicon layer of the silicon-on-insulator substrate.
18. Verfahren nach einem der Ansprüche 10 bis 17, bei dem in die Finne des ersten Fin-Feldeffekttransistors undZoder in die Finne des zweiten Fin-Feldeffekttransistors Dotiermaterial eingebracht wird.Method according to one of claims 10 to 17, in which doping material is introduced into the fin of the first fin field effect transistor and Z or into the fin of the second fin field effect transistor.
19. Verfahren nach Anspruch 18, bei dem das Dotiermaterial unter Verwendung von19. The method according to claim 18, in which the dopant using
• Plasma Immersion Ion Implantation;• plasma immersion ion implantation;
• Rapid Vapor-Phase Doping; oder• Rapid vapor phase doping; or
• Solid Phase Diffusion eingebracht wird. • Solid phase diffusion is introduced.
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US20070096196A1 (en) 2007-05-03

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