Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

• the present invention relates to a method for producing a structure comprising a thin layer of semiconductor material on a substrate, comprising the steps consisting in:
• the invention also relates to the structures obtained by such a process.
• implantation of species means any bombardment of atomic or ionic species capable of introducing these species into the material of the implanted substrate, with a maximum concentration of the implanted species located at a determined depth of the substrate relative to the surface. bombed. Processes of the type mentioned above are already known. SMARTCUT ® type processes are an example of such a process. These methods correspond to a preferred embodiment of the invention.
• the roughness of the thin layer is indeed a parameter which determines to some extent the quality of the components which will be produced on the structure.
• Roughness is generally expressed either by a quadratic mean value called RMS (according to the acronym of the English expression “Root Mean Square”), or by a power spectral density called PSD (according to the acronym of expression Anglo-Saxon “Power Spectral Density”). For example, it is common to find roughness specifications not to exceed 5 Angstroms in RMS value.
• Roughness measurements can in particular be carried out using an AFM atomic force microscope (according to the acronym of the Anglo-Saxon name Atomic Force Microscop).
• the roughness is measured on surfaces scanned by the tip of the AFM microscope, ranging from 1x1 // m 2 to 10x10 // m 2 , and more rarely 50 x50 / m 2 , see 100x100 ⁇ m 2 .
• Roughness can be characterized, in particular, in two ways. According to one of these methods, the roughness is said to be at high frequencies and corresponds to swept surfaces of small dimensions (of the order of 1x1 ⁇ 2 ). According to another of these methods, the roughness is said to be at low frequencies and corresponds to swept areas of larger dimensions (of the order of 10 ⁇ 10 ⁇ m 2 , or more).
• the “high frequencies” and “low frequencies” mentioned above thus correspond to spatial frequencies linked to the roughness measurement.
• finishing steps have in particular the objective of erasing all the roughnesses, that is to say both the roughness at high frequencies and the roughness at low frequencies.
• finishing steps generally involve operations such as chemical mechanical polishing (or CMP according to the acronym of the English expression Chemical-Mechanical Polishing), oven annealing, rapid annealing, a sequence of oxidation / deoxidation.
• a first type of known method for reducing the surface roughness thus consists in carrying out a chemical mechanical polishing of the free surface of the thin layer. This type of process effectively makes it possible to reduce the roughness of the free surface of the thin layer by reducing all the undulations, and in particular those at lower frequencies.
• Thermal annealing under a reducing atmosphere containing hydrogen makes it possible to erase the high frequency roughness by a reconstruction of the surface.
• this treatment does not completely eliminate roughness at lower frequencies (5 to 10 micrometers).
• a rapid thermal annealing step is carried out under a reducing atmosphere as well as a chemical mechanical polishing step (CMP), these steps being distinguished by their effects on different frequency ranges.
• the invention proposes, according to a first aspect, a method for producing a structure comprising a thin layer of semiconductor material on a substrate, comprising the steps consisting in:
• the implantation step implements a co-implantation of at least two different atomic species so as to. minimize low frequency roughness at the level of the structure obtained after detachment; • and the method further comprises a finishing step comprising at least one rapid thermal annealing operation so as to minimize the high frequency roughness at the structure obtained after detachment.
• the implanted helium dose is substantially between 0.7.10 16 .cm "2 and 1, 2.10 16 .cm ⁇ 2 and in that the implanted hydrogen dose is substantially between 0.7.10 16 .cm " 2 and 2J 0 16 .cm "2 ;
• RTA rapid thermal annealing
• - RTA annealing is carried out under an atmosphere comprising a mixture of hydrogen and argon, or an atmosphere of pure argon, or an atmosphere of pure hydrogen;
• Said finishing step can also comprise at least one stabilized StabOx oxidation operation of the structure obtained after detachment; - said operation of StabOx successively implements an oxidation operation, an annealing operation and a deoxidation operation;
• the RTA annealing operation can be carried out prior to the StabOx operation
• finishing step may include a plurality of RTA / StabOx sequences; - during the finishing step, the StabOx operation can also be carried out prior to the RTA annealing operation;
• the finishing step may include a plurality of StabOx / RTA sequences; - the StabOx operation or operations can be replaced by a simple oxidation operation, said simple oxidation operation comprising an oxidation operation of the structure obtained after detachment followed by a deoxidation operation;
• the invention also relates to the structures produced by implementing the method according to the first aspect of the invention.
• FIG. 1 represents roughness measurements of the PSD type carried out at the center of different structures, and illustrates the reduction in roughness at low frequencies which can be carried out by implementing the method according to the invention, with respect to what is obtained by a simple heat treatment of RTA type;
• FIG. 2 represents RMS roughness measurements and illustrates the reduction of low frequency roughness carried out using the method according to the invention, without resorting to a CMP step; .
• FIGS. 3a and 3b are representations similar to that of FIG. 1, which illustrate the reduction in roughness obtained thanks to the invention, respectively at the center of a structure and at the edge of this structure.
• the invention relates to the production of structures comprising a thin layer of semiconductor material on a support substrate, the thin layer being obtained by detachment at the level of a donor substrate previously weakened by implantation of species.
• the structure may, in general, be any type of structure comprising on a surface exposed to the external environment (free surface) a thin layer of a semiconductor material.
• the thin layer of semiconductor material can be made of silicon Si, silicon carbide SiC, germanium Ge, silicon-germanium SiGe, gallium arsenide AsGa, etc.
• the support substrate can be made of silicon Si, quartz, etc.
• An oxide layer can also be interposed between the support substrate and the thin layer, the structure thus formed being a semiconductor-on-insulator structure (SeOI structure according to the acronym of the English expression “Semi-Conductor On Insulator ", And in particular for example SOI structure).
• the invention may in particular allow to improve the quality of the thin layer of a structure obtained by implementation of a SMARTCUT ® type transfer method.
• the invention can be implemented with profit to reduce the roughness of one or the other of the two surfaces of semiconductor material which result from the detachment at the level of the embrittlement, or of these two surfaces.
• the step of implanting species aiming to create a weakening zone is carried out by co-implantation of at least two different species under one face of the donor substrate, • the procedure is carried out in addition, after detachment at the level of the embrittlement zone, at a stage of finishing by rapid thermal annealing.
• it is the hydrogen and helium species which are thus co-implanted under the face of the donor substrate to form the embrittlement zone.
• co-implantation is carried out by sequentially implanting Helium then Hydrogen.
• the Applicant has observed that the co-implantation of Helium and Hydrogen leads to the transfer of thin layers with a reduced level of roughness compared to the transfer following an implantation of Hydrogen alone. More specifically, the Applicant has observed that the frequencies at which this improvement in roughness appears most notably correspond to the roughness frequencies of lower spatial frequencies, that is to say the frequencies generally well treated by the CMP.
• the face of the donor substrate having undergone co-implantation is then brought into intimate contact with the support substrate. The donor substrate is then detached at the level of the embrittlement zone, in order to transfer part of the donor substrate to the support substrate and form the thin layer thereon.
• the method according to the invention also includes a finishing step aimed in particular at minimizing the high frequency roughness at the level of the structure obtained after detachment.
• a finishing step therefore includes at least one rapid thermal annealing step.
• rapid thermal annealing is meant rapid annealing (that is to say carried out for a period of a few seconds or a few tens of seconds), under a controlled atmosphere.
• annealing is commonly designated by the designation of annealing RTA (corresponding to the acronym of the English expression Rapid Thermal Annealing).
• RTA Rapid Thermal Annealing
• the structure is annealed at a high temperature, which may for example be of the order of 900 ° C. to 1300 ° C., for 1 to 60 seconds.
• RTA annealing is carried out under a controlled atmosphere. This atmosphere may for example be an atmosphere comprising a mixture of hydrogen and argon, or an atmosphere of pure argon, or even an atmosphere of pure hydrogen.
• the RTA annealing step makes it possible in particular to reduce the roughness of the surface of the thin layer, essentially by surface reconstruction and smoothing.
• RTA annealing promotes in particular a reduction in roughness at high frequencies.
• the crystal defects present in the thin layer, and generated in particular during implantation and detachment are at least partly cured by this RTA annealing.
• the method according to the invention for obtaining a structure with a good quality thin layer does not therefore use CMP, but nevertheless makes it possible to reduce both the high frequency roughness and the low frequency roughness.
• the implementation of the method according to the invention thus makes it possible to obtain a structure comprising a thin layer the quality of which is sufficient and compatible with the use of this thin layer in micro or optoelectronic applications.
• said finishing step can also include at least one stabilized oxidation step (also called StabOx hereinafter).
• a StabOx step is conventionally implemented in a transfer process, following the detachment step, in particular for: • check the thickness of the thin layer and reduce the density of defects;
• • a heat treatment comprising successively:> an oxidation of the structure.
• X Such an oxidation, conventionally known to those skilled in the art, can for example be carried out by heating said structure to around 900 ° C. under gaseous oxygen.
• • S Following this oxidation, an oxide layer is then formed on the thin layer. > annealing the structure at approximately 1100 ° C for two hours, under an Argon atmosphere for example. This annealing enables both of: -y strengthen the interface between the support substrate and the face of the donor substrate which has undergone the implantation, and • S cure certain defects generated during the implantation steps and detachment.
• a deoxidation operation which is carried out following the heat treatment, so as to remove the oxide layer formed during the oxidation operation.
• deoxidation known per se, can for example be carried out by immersing the structure for a few minutes, in a solution of hydrofluoric acid at 10% or 20% for example.
• the oxide layer formed during oxidation makes it possible to protect, during the annealing which follows the underlying thin layer.
• part of the thin layer, close to its free surface is thus consumed during such a StabOx operation.
• the RTA annealing makes it possible to reconstruct the surface of the thin layer, and to cure certain defects in the thickness of the latter. If this healing can, in certain cases, be only partial, the carrying out of an additional step of StabOx allows removal, of the material comprising a large part of the defects located in the vicinity of the free surface of the thin layer and in the thickness of it. This therefore again corresponds to an improvement in the quality of the structure.
• This variant of the method according to the invention, in which the finishing step comprises an RTA step and at least one StabOx step is thus particularly advantageous when there exists for the defects a gradient of increasing concentration towards the surface. free of the thin layer, and a large concentration of defects at.
• a StabOx step is carried out, during the finishing step, after the RTA step.
• This RTA / StabOx sequence makes it possible to obtain better oxidation uniformity than when the StabOx step is carried out directly after detachment, without prior implementation of the smoothing RTA step.
• the surface roughness is lower and the surface of the thin layer is more uniform.
• the speed of oxidation is close to that which is obtained when one oxidizes a polished structure, and is moreover, the same at all points of the structure.
• it may be useful to cure the crystal defects present in the thin layer (thanks to the RTA) before consuming its thickness (during the StabOx / deoxidation sequence). This is all the more advantageous when the thin layer is particularly thin, and a consumption of its thickness is likely, for example, to lead to holes which have not previously been cured and filled with an RTA annealing.
• the finishing step comprising at least one RTA operation can consist of one of the following sequences:
• finishing step comprises at least one additional RTA processing (as may be the case when RTA / StabOX or StabOx / RTA sequences are repeated several times), the processing
• Additional RTA allows to continue smoothing the free surface of the thin layer.
• Said additional RTA treatment can also be carried out at a lower temperature (for example 1000 to 1100 ° C.) than the first RTA treatment. It is thus possible to reduce the thermal budget for the repetition of the sequences mentioned above, by carrying out a RTA treatment at lower temperature.
• a so-called simple oxidation operation is performed in place of a StabOx step as mentioned above. This simple oxidation operation successively comprises an oxidation step and a deoxidation step. The thermal budget can then also be reduced since the second operation of the StabOx (thermal annealing for about two hours) is not implemented.
• This embodiment relates to the production of structures S1, S2, S3 comprising a thin layer on a support substrate.
• the thickness of the thin layer of these respective structures is between 50 and 2000 Angstroms, the total thickness of these structures being approximately 700 ⁇ m.
• These structures S1, S2, S3 are produced by implementing, during the step of implantation of species, a co-implantation of Helium then of Hydrogen, with respective doses of:
• an S4 structure is produced via an implantation of Hydrogen alone, with a dose of 5.5 ⁇ 10 16 .cm "2 , ie a dose almost three times greater than the total dose implanted during co-implantation.
• a classically observed advantage of the co-implantation technique is therefore highlighted here, with a reduction by a factor of approximately 3 of the implanted dose compared to an implantation of a single type of species.
• FIG. 1 thus makes it possible to illustrate the difference in roughness between the structures S1, S2, S3, S4, at the end of the RTA treatment of the step of finishing said structures.
• a first curve C4 illustrates the roughness of the structure S4 conventionally produced by implantation of hydrogen alone.
• Three other curves C1, C2, C3 illustrate the roughness of the structures respectively S1, S2 and S3 produced according to the method of the invention, combining co-implantation and annealing RTA. These three curves C1, C2, C3 correspond to different doses of the co-implanted species.
• FIG. 1 characterizes the fracture facies through the analysis of the frequencies making up the roughness, and demonstrates the advantage provided by the association, according to the invention, of co-implantation with the RTA.
• FIG. 1 effectively shows that the low frequency roughness of the structures S1, S2 and S3 produced according to the invention is significantly lower than that of the structure S4 produced in a conventional manner.
• a marked reduction in roughness is observed for spatial periods substantially between 3 and 15 ⁇ m.
• Co-implantation thus makes it possible to limit the roughness at low frequencies, while the roughness at high frequencies is equivalent, or even slightly lower, in the case of an implantation of hydrogen alone.
• the finishing step comprises, in addition to the RTA step, successive steps of StabOx, RTA and StabOx (i.e. a finishing step comprising a repetition of two RTA / StabOx sequences).
• a finishing step makes it possible to:
• FIG. 2 makes it possible to compare the RMS roughness of the surface of the structure .
• S3 type obtained by the mode of implementation of the invention to that of the surface of the S4 type structure obtained by a conventional process.
• Roughness measurements were therefore carried out using an AFM microscope scanning surfaces of 10 * 10 ⁇ m 2 and 40 * 40 ⁇ m 2 both at the center of the structures and at their edges (ie area where is initiated Detachment).
• FIG. 2 (ordinate axis in RMS Angstroms), the bars in the foreground represent the roughness measured for the structure of type S3, while the bars in the foreground represent the roughness measured for the structure of type S4.
• FIG. 2 shows that the bars in the foreground represent the roughness measured for the structure of type S3.
• FIGS. 3a and 3b are representations similar to that of FIG. 1, which illustrate the reduction in roughness obtained thanks to the invention, respectively at the center of a structure and at the edge of this structure.
• FIGS. 3a and 3b make it possible to compare the roughness PSD of a structure of type S3 obtained by the mode of implementation of the invention with that of a structure of type S4 obtained by a conventional process both at the center of said structures ( Figure 3a), that at their edge ( Figure 3b).
• the scanned surfaces had a dimension of 40 * 40 ⁇ m 2 .

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Power Engineering (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Recrystallisation Techniques (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)

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• 2004
  • 2004-07-29 JP JP2006521623A patent/JP2007500435A/ja active Pending
  • 2004-07-29 KR KR1020067001760A patent/KR20060030911A/ko active Search and Examination
  • 2004-07-29 WO PCT/FR2004/002038 patent/WO2005013318A2/fr active Application Filing
  • 2004-07-29 EP EP04786008A patent/EP1652230A2/fr not_active Withdrawn
• 2006
  • 2006-06-05 US US11/446,357 patent/US20060223283A1/en not_active Abandoned
• 2015
  • 2015-02-18 US US14/625,407 patent/US20150221545A1/en not_active Abandoned

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