FR2914495B1 - Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. - Google Patents
Amelioration de la qualite d'une couche mince par recuit thermique haute temperature.Info
- Publication number
- FR2914495B1 FR2914495B1 FR0754131A FR0754131A FR2914495B1 FR 2914495 B1 FR2914495 B1 FR 2914495B1 FR 0754131 A FR0754131 A FR 0754131A FR 0754131 A FR0754131 A FR 0754131A FR 2914495 B1 FR2914495 B1 FR 2914495B1
- Authority
- FR
- France
- Prior art keywords
- improving
- quality
- thin film
- high temperature
- recover high
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0754131A FR2914495B1 (fr) | 2007-03-29 | 2007-03-29 | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
US11/873,299 US7871900B2 (en) | 2007-03-29 | 2007-10-16 | Quality of a thin layer through high-temperature thermal annealing |
EP08719378A EP2130217B1 (fr) | 2007-03-29 | 2008-03-14 | Amélioration de la qualité d'une couche mince par un recuit thermique haute température |
CN2008800096825A CN101641775B (zh) | 2007-03-29 | 2008-03-14 | 通过高温热退火改善薄层品质 |
KR1020097017835A KR101423078B1 (ko) | 2007-03-29 | 2008-03-14 | 고온 열적 어닐링을 통한 박막 품질 개선방법 |
JP2010500380A JP5354303B2 (ja) | 2007-03-29 | 2008-03-14 | 高温熱アニールによる薄層の質の向上 |
PCT/IB2008/000736 WO2008120074A1 (fr) | 2007-03-29 | 2008-03-14 | Amélioration de la qualité d'une couche mince par un recuit thermique haute température |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0754131A FR2914495B1 (fr) | 2007-03-29 | 2007-03-29 | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2914495A1 FR2914495A1 (fr) | 2008-10-03 |
FR2914495B1 true FR2914495B1 (fr) | 2009-10-02 |
Family
ID=38442599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0754131A Active FR2914495B1 (fr) | 2007-03-29 | 2007-03-29 | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
Country Status (7)
Country | Link |
---|---|
US (1) | US7871900B2 (fr) |
EP (1) | EP2130217B1 (fr) |
JP (1) | JP5354303B2 (fr) |
KR (1) | KR101423078B1 (fr) |
CN (1) | CN101641775B (fr) |
FR (1) | FR2914495B1 (fr) |
WO (1) | WO2008120074A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5493343B2 (ja) * | 2008-12-04 | 2014-05-14 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
FR2968121B1 (fr) | 2010-11-30 | 2012-12-21 | Soitec Silicon On Insulator | Procede de transfert d'une couche a haute temperature |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3412449B2 (ja) * | 1997-05-29 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
CN1118087C (zh) * | 1999-09-27 | 2003-08-13 | 中国科学院半导体研究所 | 一种制备半导体衬底的方法 |
WO2002084725A1 (fr) * | 2001-04-17 | 2002-10-24 | California Institute Of Technology | Procede utilisant un transfert de la couche au germanium au si pour applications photovoltaiques, et heterostructures realisees par ce procede |
JP2003347176A (ja) * | 2002-03-20 | 2003-12-05 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
FR2839385B1 (fr) * | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
FR2874455B1 (fr) * | 2004-08-19 | 2008-02-08 | Soitec Silicon On Insulator | Traitement thermique avant collage de deux plaquettes |
JP3886959B2 (ja) * | 2002-12-10 | 2007-02-28 | エス オー アイ テック シリコン オン インシュレータ テクノロジーズ エス.アー. | 材料複合体の製造方法 |
US20040262686A1 (en) * | 2003-06-26 | 2004-12-30 | Mohamad Shaheen | Layer transfer technique |
FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
KR20060030911A (ko) * | 2003-07-29 | 2006-04-11 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 공동-임플란트 및 열적 아닐링에 의한 개선된 품질의 박층제조방법 |
JP4792694B2 (ja) * | 2003-11-13 | 2011-10-12 | セイコーエプソン株式会社 | 電気光学装置用基板の製造方法、電気光学装置用基板、電気光学装置、電子機器 |
FR2867307B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
DE102004041378B4 (de) * | 2004-08-26 | 2010-07-08 | Siltronic Ag | Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung |
-
2007
- 2007-03-29 FR FR0754131A patent/FR2914495B1/fr active Active
- 2007-10-16 US US11/873,299 patent/US7871900B2/en active Active
-
2008
- 2008-03-14 EP EP08719378A patent/EP2130217B1/fr active Active
- 2008-03-14 JP JP2010500380A patent/JP5354303B2/ja active Active
- 2008-03-14 CN CN2008800096825A patent/CN101641775B/zh active Active
- 2008-03-14 WO PCT/IB2008/000736 patent/WO2008120074A1/fr active Application Filing
- 2008-03-14 KR KR1020097017835A patent/KR101423078B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CN101641775A (zh) | 2010-02-03 |
US20080237804A1 (en) | 2008-10-02 |
US7871900B2 (en) | 2011-01-18 |
CN101641775B (zh) | 2012-04-04 |
JP2010522980A (ja) | 2010-07-08 |
KR101423078B1 (ko) | 2014-07-25 |
EP2130217A1 (fr) | 2009-12-09 |
WO2008120074A1 (fr) | 2008-10-09 |
KR20100014859A (ko) | 2010-02-11 |
EP2130217B1 (fr) | 2012-09-26 |
FR2914495A1 (fr) | 2008-10-03 |
JP5354303B2 (ja) | 2013-11-27 |
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Legal Events
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Owner name: SOITEC, FR Effective date: 20120423 |
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