ATE441206T1 - Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern - Google Patents

Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern

Info

Publication number
ATE441206T1
ATE441206T1 AT04806549T AT04806549T ATE441206T1 AT E441206 T1 ATE441206 T1 AT E441206T1 AT 04806549 T AT04806549 T AT 04806549T AT 04806549 T AT04806549 T AT 04806549T AT E441206 T1 ATE441206 T1 AT E441206T1
Authority
AT
Austria
Prior art keywords
holes
layer
obtaining
thin layer
low density
Prior art date
Application number
AT04806549T
Other languages
English (en)
Inventor
Mohamed Nadia Ben
Eric Neyret
Daniel Delprat
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE441206T1 publication Critical patent/ATE441206T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Separation Using Semi-Permeable Membranes (AREA)
  • Formation Of Insulating Films (AREA)
AT04806549T 2004-12-28 2004-12-28 Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern ATE441206T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2004/004390 WO2006070220A1 (en) 2004-12-28 2004-12-28 Method for obtaining a thin layer having a low density of holes

Publications (1)

Publication Number Publication Date
ATE441206T1 true ATE441206T1 (de) 2009-09-15

Family

ID=34960268

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04806549T ATE441206T1 (de) 2004-12-28 2004-12-28 Verfahren zum erhalten einer dünnen schicht mit einer geringen dichte von líchern

Country Status (7)

Country Link
US (1) US7485545B2 (de)
EP (1) EP1831922B9 (de)
JP (1) JP2008526010A (de)
CN (1) CN100550342C (de)
AT (1) ATE441206T1 (de)
DE (1) DE602004022882D1 (de)
WO (1) WO2006070220A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2903809B1 (fr) * 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
JP5135935B2 (ja) * 2007-07-27 2013-02-06 信越半導体株式会社 貼り合わせウエーハの製造方法
EP2161741B1 (de) * 2008-09-03 2014-06-11 Soitec Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte
FR2943458B1 (fr) * 2009-03-18 2011-06-10 Soitec Silicon On Insulator Procede de finition d'un substrat de type "silicium sur isolant" soi
JP5703920B2 (ja) * 2011-04-13 2015-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法
JP2013143407A (ja) 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウェーハの製造方法
JP5673572B2 (ja) 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2016082093A (ja) * 2014-10-17 2016-05-16 信越半導体株式会社 貼り合わせウェーハの製造方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH1084100A (ja) * 1996-09-06 1998-03-31 Shin Etsu Handotai Co Ltd Ｓｏｉ基板の製造方法
CA2225131C (en) * 1996-12-18 2002-01-01 Canon Kabushiki Kaisha Process for producing semiconductor article
US6245161B1 (en) * 1997-05-12 2001-06-12 Silicon Genesis Corporation Economical silicon-on-silicon hybrid wafer assembly
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JPH11307472A (ja) * 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
FR2797714B1 (fr) * 1999-08-20 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
FR2797713B1 (fr) * 1999-08-20 2002-08-02 Soitec Silicon On Insulator Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede
JP2002110688A (ja) 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
FR2827423B1 (fr) * 2001-07-16 2005-05-20 Soitec Silicon On Insulator Procede d'amelioration d'etat de surface
US7084046B2 (en) * 2001-11-29 2006-08-01 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
FR2846786B1 (fr) * 2002-11-05 2005-06-17 Procede de recuit thermique rapide de tranches a couronne
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
FR2852143B1 (fr) 2003-03-04 2005-10-14 Soitec Silicon On Insulator Procede de traitement preventif de la couronne d'une tranche multicouche
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
JP2007500435A (ja) 2003-07-29 2007-01-11 エス．オー．アイ．テック、シリコン、オン、インシュレター、テクノロジーズ 共注入と熱アニールによって特性の改善された薄層を得るための方法
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation

Also Published As

Publication number Publication date
WO2006070220A1 (en) 2006-07-06
CN100550342C (zh) 2009-10-14
EP1831922A1 (de) 2007-09-12
EP1831922B9 (de) 2010-02-24
EP1831922B1 (de) 2009-08-26
US7485545B2 (en) 2009-02-03
JP2008526010A (ja) 2008-07-17
DE602004022882D1 (de) 2009-10-08
US20060141755A1 (en) 2006-06-29
CN101091242A (zh) 2007-12-19

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