EP1605524A1 - Element de montage pour un element electroluminescent, et dispositif a semi-conducteur utilisant celui-ci - Google Patents

Element de montage pour un element electroluminescent, et dispositif a semi-conducteur utilisant celui-ci Download PDF

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Publication number
EP1605524A1
EP1605524A1 EP04720727A EP04720727A EP1605524A1 EP 1605524 A1 EP1605524 A1 EP 1605524A1 EP 04720727 A EP04720727 A EP 04720727A EP 04720727 A EP04720727 A EP 04720727A EP 1605524 A1 EP1605524 A1 EP 1605524A1
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EP
European Patent Office
Prior art keywords
element mounting
emitting element
light
mounting surface
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP04720727A
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German (de)
English (en)
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EP1605524A4 (fr
EP1605524B1 (fr
Inventor
Sadamu c/o Itami Works ISHIDU
Kenjiro C/O Itami Works Higaki
Takashi c/o Itami Works ISHII
Yasushi c/o Itami Works Tsuzuki
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Publication of EP1605524A1 publication Critical patent/EP1605524A1/fr
Publication of EP1605524A4 publication Critical patent/EP1605524A4/fr
Application granted granted Critical
Publication of EP1605524B1 publication Critical patent/EP1605524B1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0225—Out-coupling of light
    • H01S5/02255—Out-coupling of light using beam deflecting elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings

Definitions

  • the present invention relates to a light-emitting element mounting member and a semiconductor device using the same. More specifically, the present invention relates to a light-emitting mounting element for mounting a light-emitting diode, a semiconductor laser, or the like and a semiconductor device using the same.
  • a substrate and a ceramic window frame surrounding a light-emitting element is formed from a ceramic having as its main component aluminum oxide, aluminum nitride, or the like.
  • a metallized layer having W or Mo must generally be formed first.
  • a method is used in which a metal paste having W or Mo as its main component is first applied to a green sheet and then this is fired together with the main aluminum nitride ceramic unit (co-fired metallizing). With this method, however, thermal deformation and the like take place during firing, making it difficult to precisely form a metallized layer with a fine pattern, e.g., of less than 100 microns.
  • the object of the present invention is to overcome the problems described above and to provide a light-emitting element mounting member and semiconductor device that uses the same that has high thermal conductivity and that is easy to process.
  • the present inventors performed various investigations regarding light-emitting element mounting members that adequately dissipate heat generated by semiconductor light-emitting elements and that are easy to process. As a result, it was found that preferable characteristics can be obtained by using a mounting member with high thermal conductivity by including metal in a reflective member.
  • a light-emitting element mounting member includes: a substrate including an element mounting surface mounting a semiconductor light-emitting element and first and second conductive regions disposed on the element mounting surface and connected to the semiconductor light-emitting element; a reflective member including a reflective surface defining an internal space for housing the semiconductor light-emitting element and containing a metal disposed on the element mounting surface; and a metal layer disposed on the reflective surface.
  • the reflective surface is sloped relative to the element mounting surface so that a diameter of the internal space is greater away from the element mounting surface.
  • the substrate serves as a high thermal conductivity member, thus allowing adequate dissipation of the heat generated by the semiconductor light-emitting element. Furthermore, since the reflective member contains metal, processing is made easier compared to a structure in which the reflective member is formed from ceramic. This makes it possible to provide a light-emitting element mounting member that is easier to process.
  • the reflective member contains metal, the bond with the metal layer disposed on the reflective surface of the reflective member improves. As a result, a light-emitting element mounting member that is easy to produce can be provided.
  • the light-emitting element mounting member prefferably includes a bonding layer bonding the element mounting surface and the reflective member.
  • a heat resistance temperature of the bonding layer is at least 300 deg C.
  • the bonding layer melts at a temperature of no more than 700 deg C and bonds the element mounting surface and the reflective member.
  • the bonding layer since the bonding layer has a heat resistance temperature of at least 300 deg C, the bonding layer can prevent peeling of the substrate and the reflective member and is practical even if the temperature when the semiconductor light-emitting element is mounted on the light-emitting element mounting member is 250 - 300 deg C.
  • a highly reliable light-emitting element mounting member can be obtained.
  • the bonding temperature is no more than 700 deg C
  • metallized patterns formed from Au, Ag or Al or the like are formed on the surface of the substrate, degradation of the metallized patterns can be prevented.
  • the heat resistance temperature of these metallized patterns are generally no more than 700 deg C, the bonding can be performed without degradation of the metallized patterns by bonding at a temperature of no more than 700 deg C.
  • the substrate is insulative, first and second through-holes are formed on the substrate, the first conductor region is formed at the first through-hole, and the second conductor region is formed at the second through-hole.
  • first and second conductor regions extend from the surface of the substrate on which the element mounting surface is formed to the opposite surface, electrical power can be supplied to the first and the second conductor regions from the opposite surface.
  • a minimum formation dimension of metal film patterns of the first and/or the second conductor region is at least 5 microns and less than 100 microns. As a result, light-emitting elements can be mounted using the flip-chip method. More preferably, the dimension is less than 50 microns.
  • the minimum formation dimension of patterns here refers to the minimum widths, minimum distances between patterns, and the like in the metallized patterns.
  • a semiconductor device includes a light-emitting element mounting member as described in any of the above; and a semiconductor light-emitting element mounted on the element mounting surface.
  • the semiconductor light-emitting element includes a main surface facing the element mounting surface and the substrate includes a bottom surface positioned opposite from the element mounting surface.
  • a ratio H/L between a distance H from the bottom surface to the element mounting surface and a distance L along a direction of a long side of the main surface of the semiconductor light-emitting element is at least 0.3.
  • the ratio H/L between the long-side length L and the distance H from the bottom surface to the element mounting surface is optimized, a semiconductor device with high heat dissipation can be obtained. If the ratio H/L between the long-side length L and the distance H from the bottom surface to the element mounting surface is less than 0.3, the distance H from the bottom surface to the element mounting surface becomes too small relative to the long-side length L, preventing adequate heat dissipation.
  • an electrode it would be preferable for an electrode to be disposed on the main surface side of the semiconductor light-emitting element and electrically connected to the first and/or the second conductor region.
  • the electrode since the electrode is disposed on the main surface side and the electrode is directly connected electrically to the first and/or the second conductor region, the heat generated by the light-emission layer, which is the section of the semiconductor light-emitting element that especially generates heat, is transmitted directly to the substrate by way of the electrode.
  • the heat generated by the light-emission layer is efficiently dissipated to the substrate, providing a light-emitting element mounting member with superior cooling properties.
  • the main surface it would also be preferable for the main surface to have an area of at least 1 mm 2 .
  • Fig. 1 is a cross-section drawing of a light-emitting element mounting member according to a first embodiment of the present invention and a semiconductor device using the same.
  • Fig. 1A is a cross-section drawing of a semiconductor device according to one aspect.
  • Fig. 1B is a cross-section drawing of a semiconductor device according to another aspect.
  • Fig. 2 is a perspective drawing of the semiconductor device shown in Fig. 1A.
  • Fig. 3 is a perspective drawing of the semiconductor light-emitting element shown in Fig. 1A.
  • a semiconductor device 100 includes: a light-emitting element mounting member 200; and a semiconductor light-emitting element 1 mounted on an element mounting surface 2a.
  • the semiconductor light-emitting element 1 includes a main surface 1a facing the element mounting surface 2a.
  • the main surface 1a is formed as a rectangle including a longer first side 11 and a shorter second side 12.
  • a substrate 2 includes a bottom surface 2b opposite from the element mounting surface 2a.
  • a distance H from the bottom surface 2b to the element mounting surface 2a and a length L of the first side 11 have a ratio H/L of at least 0.3.
  • the light-emitting element mounting member 200 includes the substrate 2 and a reflective surface 6a and is equipped with a reflective member 6 and a metal layer 13.
  • the substrate 2 includes: the mounting surface 2a for mounting a semiconductor light-emitting element 1; and first and second conductor regions 21, 22 disposed on the element mounting surface 2a and connected to the semiconductor light-emitting element 1.
  • the reflective surface 6a defines an inner space 6b which houses the semiconductor light-emitting element 1.
  • the reflective member 6 is disposed on the element mounting surface 2a and contains metal.
  • the metal layer 13 is disposed on the reflective surface 6a.
  • the reflective surface 6a is sloped relative to the element mounting surface 2a so that the diameter of the inner space 6b is larger away from the element mounting surface 2a.
  • the light-emitting element 200 is further equipped with a bonding layer 9 that joins the element mounting surface 2a and the reflective member 6.
  • the bonding layer 9 has a temperature rating of at least 300 deg C, and the bonding layer 9 melts at a temperature of no more than 700 deg C to bond the element mounting surface 2a and the reflective member 6.
  • the substrate 2 is insulative and is formed with first and second through-holes 2h, 2i.
  • the first conductor region 21 is disposed on the first through-hole 2h
  • the second conductor region 22 is disposed on the second through-hole 2i.
  • the minimum pattern width and the minimum distance between patterns for the metal film formed on the element mounting surface at the first and/or second conductor regions 21, 22 are kept within the range of at least 5 microns and less than 10 microns. This allows flip-chip light-emitting elements and the like to be mounted.
  • a range of at least 10 microns and less than 50 microns is preferable.
  • smaller distances are preferable between patterns in the first and second conductor regions 21, 22 as long as bad connections are avoided. The reason for this is that reflection efficiency improves when a larger area is metallized. At less than 5 microns, bad connections tend to form.
  • Electrode layers 1b and 1f are disposed on the main surface 1a of the semiconductor light-emitting element 1 and are connected to the first and second conductor regions 21, 22.
  • the area of the main surface 1a is at least 1 mm 2 .
  • the substrate 2 is electrically insulative and formed from a material with good heat conductivity.
  • the material can be selected based on the usage environment.
  • the material can be ceramics having as the main component aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), boron nitride (BN), silicon carbide (SiC), or the like.
  • AlN aluminum nitride
  • Si 3 N 4 silicon nitride
  • BN aluminum oxide
  • SiC silicon carbide
  • a material that has as the main component electrically insulative silicon (Si), or a composite material or a combination of the above can be used.
  • the substrate 2 acts as a heat sink that dissipates heat.
  • higher heat conduction is preferable, and a heat conduction rate of at least 140 W/m ⁇ K would be preferable, with a rate of at least 170 W/m ⁇ K being more preferable.
  • the thermal expansion coefficient linear expansivity
  • Au films 3a, 3b, 3 are formed on the element mounting surface 2a.
  • the Au film 3 serves to improve the bond between the bonding layer 9 and the substrate 2.
  • the Au film 3 is formed from a material that improves the bond between the bonding layer 9 and the substrate 2.
  • the Au film 3 is used since, in this embodiment, nitride aluminum, a ceramic, is used for the substrate 2, and Au-Ge is used for the bonding layer 9. If the material used in the bonding layer is changed, then it would be possible to form the Au films 3, 3a, 3b as layers having aluminum as the main component or silver as the main component.
  • the Au films 3, 3a, 3b are formed by plating, vapor deposition, or the like. It would also be possible to interpose an intermediate layer to improve the bond, e.g., a titanium layer or a platinum layer, between the Au films 3, 3a, 3b and the element mounting surface 2a.
  • Examples of intermediate layers disposed between the element mounting surface 2a and the Au films 3, 3a, 3b include Ni, Ni-Cr, Ni-P, Ni-B, and NiCo. These can be formed by plating, vapor deposition, or the like. If vapor deposition is to be performed, materials such as Ti, V, Cr, Ni, NiCr alloy, Zr, Nb, Ta can be used. It would also be possible to stack plated layers and/or vapor deposition layers. It would be preferable for the thickness of the intermediate layer to be at least 0.01 mm and no more than 5 mm, and more preferably at least 0.1 mm and no more than 1 mm.
  • an intermediate layer e.g., formed from a Ti/Pt layered film, between the substrate 2 and the Au films 3, 3a, 3b.
  • the film containing Ti in this stacked film serves as a bonding layer to improve bonding with the substrate 2 and is formed so that it comes into contact with the upper surface of the substrate 2.
  • the material for the bonding layer does not need to be titanium and can be, for example, vanadium (V), chrome (Cr), nickel-chrome alloy (NiCr), zirconium (Zr), niobium (Nb), tantalum (Ta), or a compound of thereof.
  • the platinum (Pt) film in the Ti/Pt stacked film is a diffusion barrier layer and is formed on the upper surface of the Ti film.
  • the material does not need to be platinum (Pt), and can be palladium (Pd), nickel-chrome alloy (NiCr), nickel (Ni), molybdenum (Mo), copper (Cu), or the like.
  • the Ti/Pt stacked film and the Au films described above are collectively referred to as a metallized film.
  • the metallized film can be formed using conventional film-forming methods described above. For example, vapor deposition, sputtering, or plating can be used.
  • the patterning of the Ti/Pt stacked film and the Au films can be performed using metal masking, dry etching, chemical etching, or lift-off involving photolithography. These methods are suitable when forming fine patterns restricted to less than 100 microns or less than 50 microns.
  • the thickness of the titanium (Ti) film in the Ti/Pt stacked film prefferably be at least 0.01 mm and no more than 1.0 mm, and the thickness of the platinum (Pt) film to be at least 0.01 mm and no more than 1.5 mm.
  • the thickness of the substrate 2, i.e., the distance H from the bottom surface 2b to the element mounting surface 2a, can be set up according to the dimensions of the semiconductor element 1, but, as an example, the distance H can be set to at least 0.3 mm and no more than 10 mm.
  • the semiconductor light-emitting element 1 is disposed so that it comes into contact with the Au films 3a, 3b.
  • the semiconductor light-emitting element 1 can be formed from a group II-VI compound semiconductor light-emitting element or a group III-V compound semiconductor light-emitting element.
  • the group II elements here include zinc (Zn) and cadmium (Cd).
  • the group III elements include boron (B), aluminum (Al), gallium (Ga), and indium (In).
  • the group V elements include nitrogen (N), phosphorous (P), arsenic (As), and antimony (Sb).
  • the group VI elements include oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).
  • the semiconductor light-emitting element 1 can be formed as a compound semiconductor that is GaAs-based, InP-based, GaN-based, or the like.
  • Through-holes 2h, 2i are formed as via holes on the substrate 2.
  • the conductors used to fill the through-holes 2h, 2i form the first and second conductor regions 21, 22.
  • the main component for the conductor (via fill) is preferably a metal with a high melting point, particularly tungsten (W) or molybdenum (Mo). It would also be possible to further include a transitional metal such as titanium (Ti) or a glass component or substrate material (e.g., aluminum nitride (AlN)). Also, the through-holes 2h, 2i do not need to be filled with conductor if the inner surfaces thereof are metallized by plating or the like.
  • the surface roughness of the element mounting surface 2a is preferably no more than 1 micron Ra and more preferably no more than 0.1 micron Ra.
  • the flatness is preferably no more than 5 microns and more preferably 1 micron. If the Ra exceeds 1 micron or the flatness exceeds 5 microns, gaps tend to form between the semiconductor light-emitting element 1 and the substrate 2 during bonding, leading to reduced cooling of the semiconductor light-emitting element.
  • Surface roughness Ra and the flatness are defined according to JIS standards (JIS B0601 and JIS B0621, respectively).
  • the compound semiconductors described above are examples of materials for the semiconductor light-emitting element 1 of the present invention, but it would also be possible to stack these layers or bulks on a substrate such as a sapphire substrate.
  • the light-emitting section can be at either the top surface or the bottom surface.
  • the light-emitting layer 1c is disposed on the substrate side. Since the light-emitting layer 1c, which is the heat-generating section, is disposed closer to the substrate, heat dissipation for the semiconductor element can be improved.
  • a metallized layer e.g., an electrode layer and insulation layer formed from silicon oxide film (SiO 2 ) can be formed on the surface of the semiconductor light-emitting element 1 disposed on the substrate 2. It would be preferable for the thickness of the gold (Au) serving as the electrode layer to be at least 0.1 microns and no more than 10 microns.
  • the semiconductor light-emitting element 1 includes: a base unit 1e formed from sapphire or the like; a semiconductor layer 1d in contact with the base unit 1e; a light-emitting layer 1c in contact with a section of the semiconductor layer 1d; a semiconductor layer 1g in contact with the light-emitting layer 1c; an electrode layer 1b in contact with the semiconductor layer 1g; and an electrode layer 1f in contact with the semiconductor layer 1d.
  • the structure of the semiconductor light-emitting element 1 is not restricted to what is shown in Fig. 1A.
  • electrodes are present on both the front and back of the semiconductor light-emitting element 1, and the electrode layer 1b is connected by an Au bonding line 71 to the Au film 3b.
  • Fig. 1B only the first conductor region is directly bonded to the semiconductor light-emitting element 1.
  • the first side 11 is the long side and the second side 12 is the short side.
  • the first side 11 is the short side and the second side 12 be the long side.
  • the main surface of the semiconductor light-emitting element is rectangular, so the long side corresponds to the length L along the direction of the long side.
  • the first side 11 extends roughly perpendicular to the direction in which the light-emitting layer 1c extends.
  • the second side 12 extends roughly parallel to the light-emitting layer 1c.
  • the first side 11 and the second side 12 can be roughly the same length.
  • the first side 11 and the second side 12 are roughly the same length, the first side 11 is treated as the long side.
  • the main surface 1a is not rectangular, e.g., if the corners are rounded, the long side is defined based on an approximation of the main surface 1a to a rectangle.
  • the opposite surface will generally be roughly the same shape, but this does not need to be the case.
  • the main surface can be non-rectangular.
  • the length along the direction of the long side of the main surface of the semiconductor element of the present invention is measured from the outline of the image projected in a direction perpendicular to the main surface.
  • Fig. 3B1 through Fig. 3B5 are examples of this, and the indicated lengths L are the lengths along the direction of the long side.
  • the shape is a circle or a square, the length would be the diameter or one of the sides, respectively. If the shape is an ellipse, the length of the major axis is used.
  • the long-side length L of the semiconductor light-emitting element 1 corresponds to the length of the first side 11. It would be preferable for the ratio H/L between this length and the distance H from the bottom surface 2b to the element mounting surface 2a to be at least 0.3. It would be more preferable for the ratio H/L to be at least 4.5 and no more than 1.5. It would be even more preferable for the ratio H/L to be at least 0.5 and no more than 1.25.
  • the reflective member 6 is disposed so that it surrounds the semiconductor light-emitting element 1.
  • a material having a thermal coefficient close to the aluminum nitride forming the substrate 2 is used.
  • the reflective member can have a thermal expansion coefficient of at least 3 x 10 -6 /K and no more than 7 x 10 -6 /K. It would be preferable for the reflective member 6 to have a thermal expansion coefficient of at least 4 x 10 -6 /K and no more than 6 x 10 -6 /K.
  • the reflective member 6 is formed from a Ni-Co-Fe alloy, with the main components being Ni with a proportion of 29% by mass, Co with a proportion of 18% by mass, and Fe with a proportion of 53% by mass.
  • the reflective surface 6a is a tapered, sloped surface disposed on the reflective member 6.
  • the reflective surface 6a forms an angle relative to the element mounting surface 2a preferably in the range of 30 deg to 70 deg and more preferably in the range of 40 deg to 60 deg.
  • a plating layer 7 formed from Ni/Au is disposed on the reflective member 6. This plating layer is used when an Au-based solder (Au-Ge) is to be used for the bonding layer 9 and serves to increase the bonding strength between the bonding layer 9 and the reflective member 6.
  • Au-Ge Au-based solder
  • a plating layer 7 can also be disposed along the entire perimeter of the reflective member 6.
  • a metal layer 13 is formed to cover the surface of the reflective member 6.
  • the metal layer 13 is formed by plating or vapor deposition and serves to let out light emitted from the semiconductor light-emitting element 1.
  • the reflective surface 6a defines the inner space 6b, and the inner space 6b forms a cone shape.
  • the circular cone shape shown in Fig. 2 is an example.
  • the inner space 6b can be formed as an angular cone shape such as a four-side cone or a triangular cone.
  • the reflective surface 6a can be formed as a curved surface such as a parabolic surface.
  • Fig. 4 is a flow chart illustrating the method for making the semiconductor device shown in Fig. 1.
  • Fig. 5 through Fig. 12 are figures for the purpose of describing the method for making the semiconductor device shown in Fig. 3.
  • a substrate is produced first (step 201). Since the length and width of this type of substrate 2 is very small, on the order of a few millimeters, a substrate base with length and width of approximately 50 mm is produced and the through holes 2h, 2i are formed on the substrate base material. The first and second conductive regions 21, 22 are formed on the through-holes 2h, 2i. Then, the substrate base is finely cut to a predetermined size.
  • the size of the substrate base in this method can be, for example, 50 mm in width, 50 mm in length, and 0.3 mm in thickness.
  • the sintered aluminum nitride, which is the substrate material is made using a standard method. The cutting and splitting the substrate base to a predetermined size can, for example, be performed after bonding (step 206) or at another step.
  • the surface of the substrate from the second step is abraded (step 202).
  • the surface roughness of the abraded substrate surface is preferably an Ra of no more than 1.0 microns and more preferably no more than 0.1 microns.
  • the abrading can be performed using a standard method such as with a grinder, sand blasting, sand paper, or other methods using abrasive particles.
  • an Au film is formed using plating or vapor deposition on the element mounting surface 2a and the bottom surface 2b of the substrate 2 (step 203). More specifically, in the case of this embodiment, for example, Ti/Pt is first vaporized to serve as a backing layer and an Au film is vaporized on this.
  • the vapor deposition method can, for example, involve photolithography, where resist film is formed on the sections of the substrate outside of the regions at which the films are to be formed, with the layers being formed on the resist film and the substrate.
  • the Ti film serving as the bonding layer is vaporized, followed by the Pt film serving as the diffusion barrier layer, and then finally the Au film, which is the electrode layer, is vaporized as the outermost layer. Then, lift-off of the resist is performed. More specifically, the resist film formed in the above step is removed along with the films from the bonding layer, the diffusion barrier layer and the electrode layer using a resist removal fluid. As a result, as shown in Fig. 6 and Fig. 7, the Au films 3, 3a, 3b, 3c, 3d are formed in predetermined patterns on the substrate. The Au films 3a, 3b are formed at the central section of the substrate, and the Au film 3 is formed to surround these films.
  • patterns with pattern dimensions of no more than 100 microns can be formed, and it would also be possible to form patterns with dimensions of no more than 50 microns.
  • the dimensions refer to the smallest distance between patterns, the pattern widths, and the like.
  • peripheral members that require high-precision dimensions such as flip-chip semiconductor light-emitting elements.
  • the reflective member 6 is prepared, as shown in Fig. 4 and Fig. 8. As described above, the reflective member 6 is formed from a material with a thermal expansion coefficient close to that of aluminum nitride, e.g., an alloy with low thermal expansion formed from Ni-Co-Fe.
  • the reflective surface 6a is formed by processing the reflective member 6 (step 204).
  • the reflective surface 6a expands outward, forming an angle (e.g., 45 deg) relative to the widest surface of the reflective member 6.
  • a plating layer 7 is formed on the reflective member 6 (step 205).
  • the plating layer 7 is an Ni/Au stack. Forming the plating layer 7 along the entire perimeter of the reflective member 6 is acceptable.
  • the bonding layer 9 can be solder, sealing/coating glass, heat-resistant adhesive, or the like, and connects the reflective member and the substrate at a temperature that does not exceed the temperature tolerance of the metallized patterns.
  • solder is Au-Ge solder.
  • the use of solder is preferable due to bonding strength and its Pb-free content.
  • heat-resistant adhesives include inorganic adhesives and resin adhesives.
  • solder is Ag-based solder.
  • inorganic adhesives include glass and ceramic adhesives.
  • resin adhesives include polyimide resins, polyamide-imide resin, epoxy resin, acrylic epoxy resin, and liquid-crystal polymer resin.
  • the metal layer 13 is formed, e.g., through plating or vapor deposition (step 207).
  • the metal layer 13 serves to let out light emitted from the semiconductor light-emitting element, and it would be preferable for the outermost layer to be formed from a material with a high reflectivity, e.g., Ag, Al, or metals with these elements as main components. If the reflectivity of the reflective member 6 itself is high, the metal layer 13 can be eliminated. Also, in some cases, the metal layer 13 on the Au film 3a, 3b where the element is mounted may be eliminated in order to improve the reliability of the bond with the semiconductor element.
  • the semiconductor light-emitting element is mounted (step 208).
  • the mounting is performed in this case using a flip-chip connection, with the light-emitting layer 1c disposed toward the substrate 2.
  • the heat generated by the light-emitting layer 1c is transferred immediately to the substrate 2, providing good heat dissipation.
  • members used in the connection include Sn-based solder such as Sn, Au-Sn, Ag-Sn, and Pb-Sn solder, as well as bumps formed from Au or any of these solders.
  • the reflective member 6 contains metal.
  • the metal layer 13 can be formed directly on the surface of the reflective member 6. Also, if the reflective member 6 is to be processed in the step shown in Fig. 9, the processing is made easy and production costs can be reduced.
  • Fig. 13 is a cross-section drawing of a light-emitting element mounting member and a semiconductor device that uses the same according to a second embodiment of the present invention.
  • metal films 4, 4a, 4b are formed on the element mounting surface 2a, and the metal films 4, 4a, 4b are formed from Ag or Al.
  • the metal layer 13 formed only on the reflective member 6.
  • the reflective member 6 was attached to the element mounting surface 2a of the substrate 2 formed from aluminum nitride, interposed by the bonding layer 9.
  • the reflective member 6 is an Ni-Co-Fe alloy with an Ni proportion of 29% by mass, a Co proportion of 18% by mass, and an Fe proportion of 53% by mass. Also, the dimensions of the reflective member 6 were set to 5 mm x 5 mm x 1 mm (height x width x thickness).
  • the bonding layer was left in an atmosphere with a temperature of 300 deg C for one minute and for 24 hours at the same temperature.
  • the samples in which the bonding layer 9 did not melt again or soften and for which the drop in bonding strength, as measured according to the method indicated in Fig. 1, was less than 10% was evaluated as good and a circle was entered in the "Heat resistance” column.
  • the results from 300 deg C for one minute was entered in the "Heat resistance 1" column and the result from the same temperature at 24 hours was entered in the "Heat resistance 2" column.
  • an "X" was entered in the "Heat resistance” column.
  • the drop in bonding strength was calculated using the formula ((A1-A2)/A1), where A1 is the initial strength and A2 is the strength at room temperature after being heated at 300 deg C.
  • a bonding temperature of at least 300 deg C refers to when the bonding layer 9 does not re-melt or soften even after the bonding layer is kept in a 300 deg C atmosphere for 1 minute and that has a bonding strength drop of less than 10% when measured according to the method indicated in Fig. 1.
  • the drop in bonding strength is calculated using the formula ((A1-A2)/A1), where A1 is the initial strength (bonding strength before the layer is kept in a temperature of 300 deg C) and A2 is the strength at room temperature after being kept in a 300 deg C atmosphere for 1 minute.
  • the deterioration of the electrode metallization patterns was measured as well. More specifically, visual inspections and thickness measurements were performed on the electrode metallized patterns after the light-emitting element mounting member 200 was kept in a 300 deg C atmosphere for 24 hours. Samples in which deterioration such as discoloration did not take place for Au films 3, 3a, 3b were indicated as circles. If there was discoloration in the Au films 3, 3a, 3b or if the thickness of the Au films 3, 3a, 3b decreased, an "X" was indicated.
  • a light-emitting element mounting member and a semiconductor device that uses the same that can be easily processed and that has superior heat dissipation properties can be provided.

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EP04720727A 2003-03-18 2004-03-15 Element de montage pour un element electroluminescent, et dispositif a semi-conducteur utilisant celui-ci Expired - Fee Related EP1605524B1 (fr)

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CN1833322A (zh) 2006-09-13
WO2004084319A1 (fr) 2004-09-30
KR20050116377A (ko) 2005-12-12
EP1605524A4 (fr) 2009-01-07
US20060198162A1 (en) 2006-09-07
US7518155B2 (en) 2009-04-14
JP3918858B2 (ja) 2007-05-23
KR101045507B1 (ko) 2011-06-30
JPWO2004084319A1 (ja) 2006-06-29
CN100459188C (zh) 2009-02-04
DE602004027890D1 (de) 2010-08-12
EP1605524B1 (fr) 2010-06-30

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