EP1535338A2 - Procede pour fabriquer des cellules memoires sonos, cellule memoire sonos et champ de cellules memoires - Google Patents

Procede pour fabriquer des cellules memoires sonos, cellule memoire sonos et champ de cellules memoires

Info

Publication number
EP1535338A2
EP1535338A2 EP03794774A EP03794774A EP1535338A2 EP 1535338 A2 EP1535338 A2 EP 1535338A2 EP 03794774 A EP03794774 A EP 03794774A EP 03794774 A EP03794774 A EP 03794774A EP 1535338 A2 EP1535338 A2 EP 1535338A2
Authority
EP
European Patent Office
Prior art keywords
trench
layer
oxide
walls
metal silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03794774A
Other languages
German (de)
English (en)
Inventor
Joachim Deppe
Christoph Ludwig
Christoph Kleint
Josef Willer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Qimonda Flash GmbH
Original Assignee
Infineon Technologies AG
Qimonda Flash GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, Qimonda Flash GmbH filed Critical Infineon Technologies AG
Publication of EP1535338A2 publication Critical patent/EP1535338A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method for producing SONOS memory cells, in particular NROM memory cells, a memory cell which can be produced by this method and a semiconductor memory formed from such memory cells.
  • Memory cell arrays made of NROM memory cells can be further miniaturized in that the memory cells are not arranged next to one another in one plane, but instead on the walls of trenches that are etched out on the top of a semiconductor body. A large number of such trenches run parallel to one another at a distance and thus form a kind of comb structure on the surface of the NROM memory cells (planar SONOS memory cells, programmable by channel hot electrons and erasable with hot holes, US Pat. No. 5,768,192, US Pat. No. 6,011,725, WO 99/60631) can be further miniaturized in that the memory cells are not arranged next to one another in one plane, but instead on the walls of trenches that are etched out on the top of a semiconductor body. A large number of such trenches run parallel to one another at a distance and thus form a kind of comb structure on the surface of the
  • the channels of the memory transistors are arranged vertically on the trench walls.
  • the source and drain regions are arranged on the top of the semiconductor body adjacent to the trenches and in the trench bottoms.
  • the source / drain regions are connected with bit lines.
  • the gate electrodes of the memory transistors are arranged in the trenches and connected to word lines arranged transversely to the bit lines on the upper side of the memory cell array.
  • the word lines run transverse to the direction of the trenches and must therefore be electrically isolated from the source and drain regions in the semiconductor material.
  • a thin gate dielectric must be attached to the trench walls, while a thicker electrically insulating layer is provided on the top of the source and drain regions must to achieve sufficient electrical isolation between the word lines and the source and drain regions with low capacitive coupling.
  • the gate dielectric is formed on the walls of the trenches by a memory layer sequence, for which an oxide-nitride-oxide layer sequence is usually used.
  • the nitride layer is provided as the actual storage layer in which electrons are trapped between the oxide boundary layers when the cell is programmed.
  • oxide growth of uniform thickness is either too thick a gate dielectric layer or forms an insulation layer that is too thin.
  • An optimal tunnel oxide thickness is around 6 nm, which is too little for the insulation layer on the source and drain regions.
  • a deposited oxide is out
  • the object of the present invention is to provide a SONOS memory cell, in particular a NROM memory cell, and a method for producing this memory cell, in which the lower oxide applied to the semiconductor material of the memory layer sequence forming the gate dielectric has a preferred thickness and at the same time adequate electrical isolation of the word lines from the source and
  • Claim 10 is directed to a memory cell array formed with such memory cells.
  • Silicon is used as the semiconductor material, in which a trench or a comb-like trench structure is formed.
  • Metallized bit lines are generated by a salicide process (self-aligned silicide), especially with cobalt silicide. Thermal oxidation, in particular wet oxidation, creates an oxide layer on the metal silicide which serves to isolate the bit lines.
  • the lower boundary layer made of oxide (bottom oxide) in the gate dielectric is produced in such a way that the thicknesses of the oxide layers can largely be set independently of one another.
  • the storage layer sequence is preferably produced as an ONO layer sequence (oxide-nitride-oxide).
  • the comb-like trench structure has horizontal upper sides of the source / drain regions and vertical trench walls in which the channel regions are provided.
  • nitrogen is first implanted into the vertical trench walls with the aid of an obliquely directed implantation.
  • the nitrogen in the semiconductor material inhibits later thermal oxide growth.
  • the nitrogen implant reduces the growth rate of the oxide by a factor of up to 2 compared to silicon not implanted with nitrogen.
  • thermal oxidation preferably wet oxidation
  • an oxide layer of typically about 6 nm thickness is produced on the trench walls.
  • ⁇ .demiere oxidation process a much thicker oxide (Si0 2) is formed on the zid provided with the Metallsili- bit line.
  • the ratio of the layer thicknesses formed can be adjusted in a manner known per se via the conditions of the nitrogen implantation.
  • a thermal oxide is generated after the trench etching, which is formed on the trench walls as a lower boundary layer (bottom oxide of the storage layer sequence) and has a corresponding layer thickness of typically about 6 nm.
  • the trench walls are covered with spacers, which is preferably done using a nitride spacer process.
  • the source / drain implantation is then carried out, with which the source / drain regions are formed on the upper side adjacent to the trench and in the trench bottom.
  • the oxide on the horizontal surfaces is removed by anisotropic dry etching.
  • a metal silicide preferably cobalt silicide
  • a cover made of SiO 2 on the source / drain regions The spacers on the side walls of the trenches prevent further oxidation of the tunnel oxide on the trench walls, so that decoupling of the oxide thicknesses is also achieved with this variant.
  • the spacers on the trench walls are removed.
  • the storage layer sequence can be completed in the same way in both of the variants described, the gate electrode arranged in the trench and the word line applied and structured.
  • These process steps can be carried out together with the production of control components of the periphery in a manner known per se.
  • the lower bit lines of the mutually adjacent trenches of an arrangement formed with such cells in a memory cell array are preferably separated from one another by trench-shaped insulation strips. These insulation strips are preferably produced as STI trenches (shallow trench isolation).
  • a memory cell array designed in this way requires only 2 P 2 area per bit.
  • Figures 1 to 4 show cross sections through intermediate products of the memory cell after various steps of a first manufacturing process.
  • FIGS. 5 to 8 show cross sections through intermediate products of the memory cell after various steps of a second production process.
  • FIG. 9 shows an arrangement of storage cells in trenches which are arranged parallel to one another and separated from one another by insulation strips in cross section.
  • FIGS. 1 to 4 A first exemplary embodiment of a preferred production method is described with reference to FIGS. 1 to 4. This also results in a preferred embodiment of the memory cell.
  • 1 shows in cross section a semiconductor body 1 made of silicon, in which a trench 2 is etched on an upper side.
  • the semiconductor material can also be a silicon layer on a substrate.
  • the trench has a bottom 3 and lateral walls 4 which are located to each other in the schematic cross section of the Figure 1 plane and at right angles, but also slightly inclined depending on the applied etching method or ve 'may be rêt against each other.
  • the silicon is preferably provided with a weak basic p-type doping.
  • a dopant is introduced into the areas provided for the source and drain regions on the upper side of the semiconductor body 1 adjacent to the trench and on the bottom 3 of the trench, in the example of a basic p-doping dopant for n + line , preferably by implantation. In this way, the source and drain regions 5 are formed as shown.
  • a thin thermal oxide 18 is then produced, which is used as a sacrificial layer, in particular as a blocking layer for the subsequent salicide. Process that is provided. Using a lacquer mask 17, which covers the horizontal surfaces of the semiconductor material, an oblique implantation 6 of nitrogen is introduced into the walls 4 of the trench 2. Then the resist mask 17 is removed.
  • the thermal oxide 18 on the horizontal surfaces is then removed. This happens e.g. B. by anisotropic reactive ion etching (RIE).
  • RIE reactive ion etching
  • a metallization for forming the bit lines can then be produced on the source and drain regions 5. This is preferably done by means of a salicide process with which a thin metal silicide layer 8 is formed on the specified surfaces. The production of a cobalt silicide layer (CoSi 2 ) is preferred here.
  • the remaining thermal oxide 18 is z. B. removed by immersion in HF.
  • pure SiO 2 is formed on CoSI 2 and other metal silicides, the silicide layer penetrating deeper into the semiconductor material.
  • the electrical properties of this layer intended for the function as a bit line do not deteriorate.
  • the properties of the oxide layer formed thereon are comparable to Si0 2 layers that grow directly on a silicon body.
  • the growth rates are essentially independent of the thickness of the metal silicide layer and of the same order of magnitude as on a silicon body.
  • Layer of the storage layer sequence is provided. Because of the nitrogen implant, the oxide grows on the walls of the gra- bens 2 slower than on silicon not implanted with nitrogen.
  • the combination of the metal silicide layer 8 on the upper sides of the source and drain regions 5 with the nitrogen implant in the side walls of the trench therefore makes it possible to determine the layer thicknesses of these simultaneously produced oxide layers differently in the intended manner. Wet oxidation is primarily suitable for the oxidation.
  • the storage layer 10 is then completed by applying the actual storage layer 12 and the upper boundary layer 13, in this example over the whole area.
  • the actual storage layer 12 is preferably nitride.
  • the upper boundary layer 13 is preferably oxide again.
  • the storage layer 10 is thus formed in the preferred embodiment as an oxide-nitride-oxide layer sequence.
  • a gate electrode 14 can then be arranged in the trench. This is preferably done by depositing electrically conductive polysilicon in the trench. This material is preferably also deposited on the upper side, so that a word line 15 is produced by structuring in a manner known per se. The top of this word line can be covered with a metal silicide layer 16 or the like. This additional layer is intended to reduce the lead resistance of the word line.
  • spacers 7 covering the walls of the trench 2 are produced in accordance with the cross section shown in FIG. 5 after the trench etching and the production of the thermal oxide 18. This is preferably done using a nitride spacer process. As described above, the source and drain regions 5 are formed by implanting dopant.
  • the thermal oxide 18 is from the horizontal Surfaces preferably wet-chemically removed; anisotropic RIE is also possible.
  • the metal silicide layer 8 is also preferably here a salicide layer.
  • CoSi 2 is preferred as the metal silicide.
  • the covering oxide layer 9 is then produced on the metal silicide layer 8. Then the covering spacers 7 are removed selectively with respect to the oxide. B. can be done by means of phosphoric acid.
  • the exposed oxide 18 can now itself be used as the lower boundary layer 11 of the storage layer 10 or else can be removed by wet chemical means, the oxide layer 9 also being thinned.
  • the lower boundary layer 11 is produced by a new oxidation.
  • the oxide layer 9 is further reinforced. The storage layer can then be completed as described above.
  • the structure with the complete storage layer 10 is shown in cross section in FIG.
  • the gate electrode 14, which can also be conductively doped polysilicon here, is arranged in the trench.
  • the word line 15, which can optionally comprise a metal silicide layer 16, is applied and structured in the manner described.
  • FIG. 9 shows a cross section through an arrangement of a plurality of trenches with memory cells which are arranged parallel to one another at a distance.
  • a grid-like arrangement of memory cells in particular NROM memory cells, can be formed in a memory cell array.
  • the lower source and drain regions 5 on the Bottoms 3 of the trenches can each be isolated from one another by a trench-like insulation strip 19, which is arranged parallel to the trenches between two mutually adjacent trenches, at least reaches the depth of the source / drain regions 5 arranged on the bottoms 3 of the trenches, and preferably is produced in the manner of an STI structure as an oxide-filled trench.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Dans un élément en silicium (1) est façonné un puits (2) dont les parois (4) sont dotées d'une implantation d'azote (6). Une couche d'oxyde située entre les zones source/drain (5) et un canal mots disposé sur la face supérieure croît plus en volume qu'une couche d'oxyde inférieure d'une couche de mémoire ONO fonctionnant comme diélectrique de grille sur la paroi du puits. A la place d'une implantation d'azote dans les parois du puits, une couche de siliciure de métal peut être façonnée sur les faces supérieures des zones source/drain pour accélérer la croissance de l'oxyde à ces emplacements.
EP03794774A 2002-09-04 2003-07-31 Procede pour fabriquer des cellules memoires sonos, cellule memoire sonos et champ de cellules memoires Withdrawn EP1535338A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10240893A DE10240893A1 (de) 2002-09-04 2002-09-04 Verfahren zur Herstellung von SONOS-Speicherzellen, SONOS-Speicherzelle und Speicherzellenfeld
DE10240893 2002-09-04
PCT/DE2003/002576 WO2004025731A2 (fr) 2002-09-04 2003-07-31 Procede pour fabriquer des cellules memoires sonos, cellule memoire sonos et champ de cellules memoires

Publications (1)

Publication Number Publication Date
EP1535338A2 true EP1535338A2 (fr) 2005-06-01

Family

ID=31724341

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03794774A Withdrawn EP1535338A2 (fr) 2002-09-04 2003-07-31 Procede pour fabriquer des cellules memoires sonos, cellule memoire sonos et champ de cellules memoires

Country Status (5)

Country Link
US (1) US7323388B2 (fr)
EP (1) EP1535338A2 (fr)
DE (1) DE10240893A1 (fr)
TW (1) TWI234240B (fr)
WO (1) WO2004025731A2 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014223904A1 (de) 2014-11-24 2016-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Kondensator und Verfahren zum Herstellen desselben
EP3024033A1 (fr) 2014-11-24 2016-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Condensateur et son procédé de fabrication
US10937696B2 (en) 2014-11-24 2021-03-02 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Capacitor and method for producing the same
US11854890B2 (en) 2014-11-24 2023-12-26 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Capacitor and method for producing the same
EP4354512A2 (fr) 2014-11-24 2024-04-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Condensateur et son procédé de fabrication

Also Published As

Publication number Publication date
US20050196923A1 (en) 2005-09-08
WO2004025731A2 (fr) 2004-03-25
TW200408067A (en) 2004-05-16
WO2004025731A3 (fr) 2004-08-19
DE10240893A1 (de) 2004-03-18
US7323388B2 (en) 2008-01-29
TWI234240B (en) 2005-06-11

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