Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
  • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/05—Making the transistor

Definitions

• the present patent application relates to a semiconductor memory cell and a method for its production.
• the semiconductor memory cell comprises a selection transistor and a trench capacitor which is formed in a trench.
• Memory components such as DRAMs (Dynamic Random Access Memories) consist of a cell array and a control periphery, with individual memory cells being arranged in the cell array.
• DRAMs Dynamic Random Access Memories
• One of the diffusion areas is connected to a bit line, the other diffusion area to the capacitor and the gate to a word line.
• the transistor is controlled so that a current flow between the diffusion regions through the channel is switched on and off.
• the progressive miniaturization of memory components increases the integration density continuously.
• the continuous increase in the integration density means that the area available per memory cell continues to decrease.
• the selection transistor is formed, for example, as a planar transistor, the lateral distance between the selection transistor and the trench capacitor consequently decreases further and further. This leads to a reduction in the blocking capability of the selection transistor, which blocks more poorly anyway as the channel length decreases due to the short channel effect.
• the increased leakage currents discharge the trench capacitor prematurely, as a result of which the information stored in the trench capacitor and the memory cell is lost.
• the doping region of the selection transistor must usually be formed in single-crystal silicon in order to avoid leakage currents through the selection transistor. Since the buried strap is usually formed from polycrystalline silicon, which adjoins the monocrystalline silicon of the doping region of the selection transistor, crystal crossings occur at elevated temperatures, starting from the
• a disadvantage of an epitaxially grown buried contact is that crystal dislocations are formed at the transition between the single-crystal epitaxially grown silicon and a polycrystalline grown silicon. This defect formation leads to increased leakage currents in the selection transistor. During the further manufacturing process of the DRAM, the dislocations slide and can short-circuit the selection transistor.
• a substrate which has a substrate surface and in which a trench is arranged which has an upper region
• the epitaxially grown layer has a lower diffusion length in the epitaxially grown layer than in the adjacent bulk silicon in which the selection transistor is formed. This means that the dopant diffused out of the buried strap does not diffuse into the channel of the selection transistor, thereby preventing an amplification of the short channel effect in the selection transistor.
• the first intermediate layer has the advantage that crystal dislocations formed in the buried strap do not grow into the single-crystal substrate in which the selection transistor is arranged. This avoids crystal defects at the doping region of the transistor, whereby an improved transistor with low leakage currents can be achieved.
• the epitaxially grown layer is arranged in the direction of the substrate surface above the insulation collar on the side wall of the trench. This improves the dopant profile of the out-diffusion above the insulation collar.
• a capacitor dielectric is usually arranged in the trench between the conductive trench filling and the substrate.
• the trench insulation has an insulation layer which is arranged on the buried contact and on the facet.
• the insulation layer arranged on the buried contact and on the facet has the advantage that, in the case of a planar selection transistor, a passing word line isolated from the trench capacitor can be arranged on the trench insulation.
• an active word line for driving the cell transistor runs above the trench.
• a further embodiment of the invention provides that the insulation collar consists of two layers that can be selectively etched to one another.
• the object according to the invention is achieved by a method for producing a semiconductor memory with a trench capacitor and a selection transistor with the steps:
• FIG. 12 SEM image of a memory cell according to the invention
• FIGS. 21 and 22 process steps for filling an annular gap between the epitaxial layer and the insulation collar.
• the first recess depth 110 is formed approximately 100 nm below the substrate surface 25. If a vertical transistor is arranged in the trench capacitor, the first recess depth 110 is sunk into the trench 30, starting from the substrate surface 25, about 350 nm deep.
• a passing wordline is arranged on the trench isolation (STI) and the active wordline runs next to the trench in order to drive the planar selection transistor there. This is described in more detail with reference to FIG. 9.
• the active wordline is arranged above the trench in order to contact and drive a gate arranged in the trench.
• the passing wordline is arranged next to the trench.
• the dielectric layer 35 is then removed. This can be accomplished, for example, by wet chemistry, using, for example, hydrofluoric acid buffered with ethylene glycol (HF / EG) to remove a dielectric layer consisting of an oxynitride.
• HF / EG hydrofluoric acid buffered with ethylene glycol
• the conductive trench filling 50 is sunk into the trench 30 to a second recess depth 115. Part of the dielectric layer 35 is thereby exposed.
• the insulation collar 55 is then removed from the side wall of the trench 30.
• the insulation collar 55 remains on the side wall of the trench 30 where it passes through the dielectric layer 35 LO LO to to P> P 1
• ⁇ P ⁇ ⁇ d Hj ⁇ ⁇ ⁇ LQ d cd P- 01 H- 1 ⁇ 1 ⁇ LO LQ 01
• N rt tr CL P ⁇ P- d HS H- " ⁇ rt Hh CL P- H- 1 ⁇ rr P rt ⁇ rt P- Hh P ⁇ cn LQ P- P- P ⁇ ! K ⁇ X • ⁇
• P- - - ⁇ 01 PP 1 P- P Hi PP CQ ⁇ P- HS X cn ⁇ ⁇ CL r to P ⁇ • n 0 3 ⁇ CL Hi o to

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Semiconductor Memories (AREA)
• Semiconductor Integrated Circuits (AREA)

Applications Claiming Priority (3)

Publications (1)

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Country Status (6)

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Family Cites Families (9)

• 2002
  • 2002-03-05 KR KR1020037011590A patent/KR100631092B1/ko not_active IP Right Cessation
  • 2002-03-05 WO PCT/DE2002/000788 patent/WO2002073657A2/de active Application Filing
  • 2002-03-05 JP JP2002572609A patent/JP2004523918A/ja active Pending
  • 2002-03-05 EP EP02727188A patent/EP1366517A2/de not_active Withdrawn
  • 2002-03-08 TW TW091104370A patent/TW554520B/zh active
• 2003
  • 2003-09-10 US US10/657,928 patent/US6828192B2/en not_active Expired - Fee Related

Non-Patent Citations (1)

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