EP1305834A1 - Transistor a effet de champ, circuit, et procede de fabrication d'un tel transistor a effet de champ - Google Patents

Transistor a effet de champ, circuit, et procede de fabrication d'un tel transistor a effet de champ

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Publication number
EP1305834A1
EP1305834A1 EP01960126A EP01960126A EP1305834A1 EP 1305834 A1 EP1305834 A1 EP 1305834A1 EP 01960126 A EP01960126 A EP 01960126A EP 01960126 A EP01960126 A EP 01960126A EP 1305834 A1 EP1305834 A1 EP 1305834A1
Authority
EP
European Patent Office
Prior art keywords
field effect
effect transistor
region
nanotube
nano
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP01960126A
Other languages
German (de)
English (en)
Inventor
Johannes Kretz
Richard Johannes Luyken
Wolfgang Roesner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1305834A1 publication Critical patent/EP1305834A1/fr
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/60—Organic compounds having low molecular weight
    • H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region

Definitions

  • the invention relates to a field effect transistor, a circuit arrangement and a method for producing a field effect transistor.
  • Such a field effect transistor such a circuit arrangement and a method for producing a field effect transistor are known from [1].
  • a conventional field effect transistor has a source region, a drain region and a channel region located between the source region and the drain region.
  • a conventional field effect transistor has a gate region in which the electrical conductivity of the channel region is controlled by applying a voltage, that is to say an electrical potential to the gate region, in such a way that the field effect transistor is either electrically blocking or electrically is operable in a managerial manner.
  • a common field effect transistor is based on pure semiconductor microelectronics, which uses silicon technology, for example.
  • Conventional silicon microelectronics has physical limits, in particular when the size of the electronic components is reduced, for example when the size of a field effect transistor is reduced.
  • the known semiconductor technology in which semiconductor layers are deposited one above the other and the individual regions of the field effect transistor are formed in the individual layers by doping the respective regions with doping atoms, is not suitable for a real three-dimensional Dimensional integration in an electrical circuit arrangement is suitable.
  • carbon nanotubes Fundamentals of so-called carbon nanotubes, which are referred to hereinafter as carbon nanotubes, are also known from [2].
  • a method for producing carbon nanotubes by growing the carbon nanotubes on a substrate is known from [3] and [4].
  • a method for producing a silicon nanowire is also known from [5].
  • the invention is based on the problem of specifying a field effect transistor, a circuit arrangement and a method for producing a field effect transistor which is better suited for three-dimensional integration than field effect transistors which are based exclusively on the technology principles described in [1].
  • a field effect transistor has a source region, a drain region and a gate region.
  • the gate region is arranged between the source region and the drain region.
  • the gate region which is formed from conductive material, for example from a conductive layer with aluminum, titanium, tungsten, gold, silver or an alloy of at least one of the aforementioned materials, has at least a through hole, which is also referred to as a pore. Basically, any number of through holes are provided in the gate area.
  • At least one nano-element is provided, which is electrically coupled to the source region and the drain region of the field effect transistor.
  • a nanoelement is understood to mean, for example, a nanotube and / or a nanowire, for example a semiconducting carbon nanotube or a semiconducting silicon nanowire.
  • the nanoelement can also have a heterostructure with a plurality of regions, preferably a first metallically conductive region, a second electrically conductive region and an electrically insulating region which is arranged between the first metallically conductive and the second metallically conductive region.
  • the regions can be formed both in a one-piece structure, for example a carbon nanotube, by forming different electrical properties in different regions of the respective nanotube or in a silicon nanowire.
  • the heterostructure can also be formed as a sub-element by correspondingly joining together the individual regions, which results in the hetero structure described above, with sufficient accuracy.
  • the invention makes it possible for the first time to use a field-effect transistor which can be used for real three-dimensional integration within an integrated circuit in the context of microelectronics. Furthermore, the dimension, that is to say the space required on a chip area of such a field effect transistor, is considerably smaller than that of a known field effect transistor, since the nanowire or the nanotube forming the channel region is designed to be very small, that is to say it has a diameter of up to only 1 nm.
  • the first metallically conductive region of the nanotube is a metallically conductive carbon nanotube or part of a carbon nanotube that is metallically conductive in the first metallically conductive region.
  • the second metallically conductive region can likewise be a metallically conductive carbon nanotube or a partial region of the carbon nanotube which also has the first metallically conductive region, the second metallically conductive region also being metallically conductive.
  • an electrically insulating area of the nanotube is formed as a boron nitride nanotube.
  • the respective electrically insulating region is formed by correspondingly doping the respective region with boron atoms and nitrogen atoms as described in [6].
  • the source region can contain a material which is catalytically active for the formation, that is to say the growth or deposition, from the gas phase, as described in [3] and [4].
  • the catalytically active for the formation of the nanotubes Materi ⁇ al may contain nickel, cobalt, iron or an alloy of at least one of the aforementioned materials.
  • the nano-element is arranged and designed in the through hole such that it passes over the gate region in its
  • the resulting structure that is to say the field effect transistor resulting therefrom, has the particular advantage that a carbon nanotube is very easy to handle and stable, so that the susceptibility to errors of such a field effect transistor continues is reduced.
  • a field-effect transistor is clearly formed, which is based on a tunnel principle of electrical charge carriers, the tunneling being controllable on the basis of the electrical potential which is applied to the gate region.
  • the drain area contains nickel, cobalt or an alloy of nickel and / or cobalt.
  • a circuit arrangement has at least one field effect transistor of the type shown above.
  • Such a circuit arrangement has, in particular, the advantage of the increased integration, which is now also possible three-dimensionally more completely and the associated reduction Space requirement, that is, a considerably increased integration density of the components on a chip.
  • a source layer is applied to a substrate, and undoped or doped silicon, glass, quartz or also sapphire can be used as the substrate.
  • An electrically conductive gate layer is applied to the source layer.
  • at least one through hole is formed in the gate layer, preferably by means of dry etching, since when using a dry etching method to form the through holes in the gate region, in particular vertical structures can be very precisely etched.
  • At least one nano-element which is electrically coupled to the source layer, is introduced into the through hole.
  • the nanoelement is arranged and designed such that its conductivity can be controlled via the gate region, so that the nanoelement forms the channel region of the field effect transistor.
  • the nano-element is grown or deposited, for example, on a catalyst material located on the bottom of the through hole.
  • a carbon nanotube outside the through hole and then to place it mechanically in the through hole, for example using an atomic force microscope in such a way that the carbon nanotube introduced into the through hole is in electrical contact with the ground, that is to say with the top Surface of the source layer comes.
  • a drain layer is applied to the gate layer such that the drain layer is likewise electrically coupled to the nano-element.
  • the nano-element has a length which is greater than the length of the through-hole, so that the nano-element still extends beyond the surface of the through-hole and thus extends on the gate when the drain layer is grown or deposited Layer automatically forms an electrical contact between the drain layer and the nanoelement.
  • Fig.la shows a substrate, according to this embodiment made of silicon dioxide 101.
  • quartz or sapphire can also be used as the substrate 101 instead of the silicon dioxide.
  • a source layer 102 made of nickel is applied and structured using photolithography.
  • the source layer 102 forms the source region of the field effect transistor to be formed.
  • any suitable metal in particular cobalt or iron, can in principle be used as the alternative material for the source layer 102.
  • a dialuminium trioxide layer (Al 2 O 3) 103 is deposited on the structured source layer 102 forming the source electrode and on the substrate 101.
  • This dialuminium trioxide layer 103 which is relatively thin compared to the source layer 102, serves as a dielectric with which the gate electrode, which is formed by a gate layer described below, is electrically insulated from the source layer 102.
  • the source layer 102 is approximately 100 nm thick and the dialuminium trioxide layer 103 has a layer thickness of approximately 20 nm.
  • an aluminum layer is deposited and structured on the dialuminium trioxide layer 103, so that the structured aluminum layer, which is referred to as gate layer 104 hereinafter, is the gate of the one to be formed Field effect transistor 100 represents.
  • the gate layer 104 also has a thickness of approximately 100 nm and is applied by means of a suitable CVD method or a sputtering method, a vapor deposition method or an epitaxy method.
  • titanium, tungsten, silver or gold can be used for the gate layer 104 instead of the aluminum.
  • a further layer 105 made of dialuminium trioxide is deposited by means of a suitable CVD process or a sputtering process or an evaporation process and the further layer 105 which is formed and is of any desired thickness is reduced to a thickness by means of a chemical mechanical polishing process (CMP process) such that the upper surface of the further layer 105 made of dialuminium trioxide.
  • CMP process chemical mechanical polishing process
  • Layer 105 is level with the top surface of gate layer 104.
  • photoresist is applied to the gate layer and the further layer 105 in the gate layer 104 by means of, for example, photolithography and self-adjusted known narrowing methods, and structuring takes place in such a way that in a further step, holes 106 in the gate are dry-etched. Layer 105 are etched.
  • the through holes 106 formed in this way have a diameter of approximately 1 nm to 10 nm.
  • the dry etching process is carried out until both the material of the gate layer 104 and the material of the dialuminium trioxide layer 103 underneath it are removed in the holes 106 formed.
  • material 107 is applied in the through holes 106 in a further step, which material is used for further described growth or deposition of carbon nanotubes or silicon nanowires Through hole 106 acts catalytically.
  • nickel, cobalt or iron is used as material 107.
  • the deposition takes place in such a way that the respective carbon nanotubes are electrically coupled to the source layer 102 via the catalytically active metals 107.
  • the grown carbon nanotubes are semiconducting carbon nanotubes.
  • the carbon nanotubes can be controlled in terms of their conductivity by means of the known field effect by applying an electrical voltage to the gate region, that is to say to the gate layer 104, so that the carbon nanotubes 108 clearly have the functionality of the channel region of a field effect transistor.
  • silicon nanowires can be grown into the through holes 106, as described above, using selective silicon epitaxy in accordance with the method known from [5].
  • silicon nanowires can also be used as a channel region of a field effect transistor by means of a field effect which is developing.
  • part of the metal of the gate layer 104 in particular, for example, the aluminum of the gate layer 104, is oxidized, so that a thin oxidized gate layer, for example made of dialuminium trioxide 109, is between the metal, for example aluminum Gate layer and the nano-elements, for example the carbon nanotubes or the silicon nanowires.
  • a further metal layer 110 is deposited on the oxidized layer 109 and the further layer 105 as a drain layer forming the drain of the field effect transistor and structured by means of lithographic methods.
  • the drain layer 110 can have nickel, alternatively also cobalt.
  • the carbon nanotubes 108 or the silicon nanowires have a length such that they protrude beyond the upper surface of the oxidized layer 109 after their deposition or their growth.
  • an electrical contact to the nanoelement is automatically created, that is to say, for example, to the carbon nanotube 108 or to the silicon nanowire.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

La zone de grille d'un transistor à effet de champ présente au moins une ouverture de passage comportant un élément nanométrique couplé électriquement à la source et au drain. La conductivité de l'élément nanométrique peut être commandée par l'intermédiaire de la grille, de manière que cet élément nanométrique forme une zone canal du transistor à effet de champ.
EP01960126A 2000-07-28 2001-07-19 Transistor a effet de champ, circuit, et procede de fabrication d'un tel transistor a effet de champ Ceased EP1305834A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10036897A DE10036897C1 (de) 2000-07-28 2000-07-28 Feldeffekttransistor, Schaltungsanordnung und Verfahren zum Herstellen eines Feldeffekttransistors
DE10036897 2000-07-28
PCT/DE2001/002708 WO2002011216A1 (fr) 2000-07-28 2001-07-19 Transistor a effet de champ, circuit, et procede de fabrication d'un tel transistor a effet de champ

Publications (1)

Publication Number Publication Date
EP1305834A1 true EP1305834A1 (fr) 2003-05-02

Family

ID=7650588

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01960126A Ceased EP1305834A1 (fr) 2000-07-28 2001-07-19 Transistor a effet de champ, circuit, et procede de fabrication d'un tel transistor a effet de champ

Country Status (4)

Country Link
US (1) US6740910B2 (fr)
EP (1) EP1305834A1 (fr)
DE (1) DE10036897C1 (fr)
WO (1) WO2002011216A1 (fr)

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