EP1556893A2 - Cellule de memoire, ensemble de cellules de memoire, ensemble de structuration et procede de fabrication d'une cellule de memoire - Google Patents

Cellule de memoire, ensemble de cellules de memoire, ensemble de structuration et procede de fabrication d'une cellule de memoire

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Publication number
EP1556893A2
EP1556893A2 EP03778241A EP03778241A EP1556893A2 EP 1556893 A2 EP1556893 A2 EP 1556893A2 EP 03778241 A EP03778241 A EP 03778241A EP 03778241 A EP03778241 A EP 03778241A EP 1556893 A2 EP1556893 A2 EP 1556893A2
Authority
EP
European Patent Office
Prior art keywords
nanostructure
memory cell
substrate
switching transistor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03778241A
Other languages
German (de)
English (en)
Inventor
Andrew Graham
Franz Hofmann
Wolfgang HÖNLEIN
Johannes Kretz
Franz Kreupl
Erhard Landgraf
Richard Johannes Luyken
Wolfgang RÖSNER
Thomas Schulz
Michael Specht
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1556893A2 publication Critical patent/EP1556893A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/16—Memory cell being a nanotube, e.g. suspended nanotube
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/60—Organic compounds having low molecular weight
    • H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Definitions

  • Memory cell memory cell arrangement, structuring arrangement and method for producing a memory cell
  • the invention relates to a memory cell, a memory cell arrangement, a structuring arrangement and a method for producing a memory cell.
  • DRAM memory dynamic random access memory
  • a DRAM memory is a dynamic semiconductor memory in whose memory matrix there is a capacitor per bit as the memory cell. Binary information is stored by charging this capacity.
  • a memory cell is addressed via a switching transistor, via which the capacitance is coupled to a bit line.
  • the word line is brought to a sufficiently high electrical potential so that the switching transistor becomes conductive and the memory cell is coupled to the bit line.
  • the capacity is loaded or unloaded during programming.
  • a DRAM memory cell is usually designed as an integrated semiconductor circuit.
  • the problem arises that the expansion of each component of a DRAM memory cell in each dimension has at least the size F, where F is that in a respective
  • FRAM ferrroelectric random access memory
  • a FRAM memory cell is a MOS field-effect transistor, in which a ferroelectric layer is provided instead of the gate insulating layer.
  • a preferred direction of the permanent ferroelectric dipole moments in the ferroelectric layer ie the programming of the FRAM memory cell, is carried out by means of a suitably selected gate voltage.
  • the electrical conductivity of the channel region adjoining the ferroelectric layer is characteristically influenced.
  • the strength of the electrical current depends between the two source / drain regions, between which the channel region is arranged, depends on the state in which the ferroelectric dipoles of the ferroelectric layer are as a result of a programming event which has taken place previously.
  • a structure is used as in the DRAM memory cell described above, with the difference that a ferroelectric (for example lead zirconate titanate, Pb (Zr ⁇ _ x Ti x )) is used between the capacitor electrodes instead of a dielectric. 0 3 , PZT) is used.
  • a ferroelectric for example lead zirconate titanate, Pb (Zr ⁇ _ x Ti x )
  • Pb lead zirconate titanate
  • PZT lead zirconate titanate
  • Nanotubes in particular carbon nanotubes, are regarded as a possible successor to conventional semiconductor electronics. An overview of this technology is given, for example, [1].
  • a carbon nanotube is a single-walled or walled tube-like carbon compound.
  • at least one inner nanotube is coaxially surrounded by an outer nanotube.
  • Single-walled nanotubes typically have diameters of approximately 1 nm, and the length of a nanotube can be several 100 nm. The ends of a nanotube are often terminated with half a fullerene molecule. Nanotubes often have good electrical conductivity, which is why nanotubes are suitable for the construction of circuits with dimensions in the nanometer range.
  • nanotubes are suitable for a large number of applications, for example for electrical coupling technology in integrated circuits, for components in microelectronics and as an electron emitter.
  • nanotubes made from other materials for example on tungsten sulfide and other chalcogenides, are also known.
  • nanorods In addition to nanotubes are nanorods (“nanorods”) as
  • nanorods also have a diameter in the nanometer range and can be several micrometers long.
  • Typical materials for nanorods are the semiconductors silicon, germanium, indium phosphide and gallium arsenide. Both nanotubes and nanorods can be separated from the gas phase using catalytic processes. For example, an overview of the technology of nanostructures is given [2].
  • [6] discloses a method of manufacturing a semiconductor device in which a triple copolymer block is formed with a first copolymer as an inner column, a second copolymer as an outer column and a third copolymer surrounding the second copolymer.
  • [7] discloses a field effect transistor, a
  • the invention is based on the problem of creating a memory cell with a memory capacitor, which
  • Memory cell can be produced in a miniaturized manner, and in which memory cell short-channel effects are avoided with a field effect transistor contained in the memory cell.
  • the problem is solved by a memory cell, a
  • Memory cell arrangement a structuring arrangement and a method for producing a memory cell with the features according to the independent claims.
  • a memory cell with a vertical switching transistor and a storage capacitor is provided, the vertical switching transistor having a semiconducting nanostructure which has been grown on at least part of the storage capacitor.
  • Memory cell provided, in which a vertical switching transistor and a storage capacitor are formed, a semiconducting nanostructure of the vertical switching transistor being formed, which is grown on at least part of the storage capacitor.
  • a structuring arrangement is also created, with a nanostructure which extends essentially orthogonally to the surface of a substrate and which is at least partially arranged outside the substrate, with material to be structured on the part of the nanostructure arranged outside the substrate, with an etchant.
  • Feeding device which is set up in such a way that it can be used to etch the material to be structured at a predeterminable angle to the nanostructure onto the nanostructure covered with the material to be structured in such a way that only those partial areas of the material to be structured can be removed before being removed as a result of etching are protected, which are shaded by the nanostructure with respect to the etchant.
  • the memory cell according to the invention can clearly be used as a DRAM memory cell or as a FRAM memory cell.
  • a memory cell of the invention can be selected in a memory cell arrangement by means of the vertical switching transistor, so that the information stored in the memory capacitor can be read out or programmed.
  • the vertical switching transistor has a semiconducting nanostructure, for example a carbon nanotube, a carbon-nitrogen nanotube, or a carbon-boron-nitrogen nanotube.
  • the memory cell according to the invention can be miniaturized by using a nanostructure in the vertical switching transistor.
  • a vertical carbon nanotube which can be used as a nanostructure, has a dimension of one or a few nanometers in cross section, so that in principle one
  • Memory cell with a space requirement of this magnitude can be designed according to the invention.
  • the switching transistor with the semiconducting nanostructure as a vertical transistor, miniaturization is simultaneously possible while avoiding short-channel effects.
  • the nanostructure can have an extent of hundreds of nanometers or even a ⁇ in the vertical direction and therefore the channel region can be made sufficiently long as part of the nanostructure so that disruptive short-channel effects are avoided.
  • the vertical switching transistor and the storage capacitor are preferably formed at least partially in and / or at least partially on a substrate.
  • the substrate is preferably a semiconductor substrate and in particular a silicon substrate.
  • the nanostructure can extend substantially orthogonally to the surface of the substrate.
  • a first end section of the nanostructure is preferably arranged inside the substrate and a second end section of the nanostructure is arranged outside the substrate.
  • this part can serve as a “template” for the formation and in particular for the selective removal of material on the nanostructure and / or on the substrate.
  • an etchant can be directed onto the nanostructure and the substrate at a predetermined angle, the area on the nanotube or on the substrate which is shaded by the nanotube with respect to the etchant being protected from etching.
  • the vertical switching transistor is preferably a field effect transistor.
  • the first section of the nanostructure can have a first source / drain region
  • the second end section of the nanostructure can have a second source / drain region
  • an intermediate region of the nanostructure arranged between the two end sections can have a channel Form the area of the vertical switching transistor.
  • a dielectric layer can be located between the first end section of the nanostructure and the substrate be formed, the first end portion of the nanostructure forming a first electrically conductive capacitor element, the dielectric layer forming a capacitor dielectric and the substrate forming a second electrically conductive capacitor element of the storage capacitor.
  • the nanostructure fulfills both the functionality as a component of the vertical switching transistor and the functionality as the first conductive one
  • Capacitor element of the storage capacitor is the analogue to a capacitor plate of a conventional capacitor.
  • the memory cell according to the invention can be used as an FRAM memory cell with the functionality described above.
  • Catalyst material for catalyzing the formation of the nanostructure can be arranged between at least part of the dielectric layer and the nanostructure.
  • the spatial growth of the nano structures can be predetermined by means of the catalyst material. Therefore, it is by providing an orderly arrangement of not necessarily contiguous areas of
  • Catalyst material enables orderly growth of the nanostructure. It should be noted that In particular, if the nanostructure is designed as a carbon nanotube, iron, cobalt or nickel is a good choice as the catalyst material.
  • At least part of the intermediate region of the nanostructure can be surrounded by an electrically insulating ring structure, which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ring structure can be surrounded by a first electrically conductive region, which forms the gate electrode of the vertical switching transistor and the word line.
  • a gate insulating layer is provided, which is surrounded by the first electrically conductive region functioning as a gate electrode.
  • the conductivity of the nanostructure can be influenced in the intermediate area of the nanostructure, functioning as a channel area, so that the nanostructure together with the electrically insulating ring structure and the first electrically conductive area Functionality of a
  • Field effect transistor met.
  • an annular gate electrode By using an annular gate electrode, the amplitude of an electric field generated by applying an electrical voltage to the gate electrode near the nanostructure can be made particularly large due to an electrostatic peak effect, so that particularly precise control of the electrical conductivity of the channel region is made possible is.
  • Nanostructure can also act as a shadow mask for the formation of the first electrically conductive region. Therefore the components mentioned are formed by means of a self-adjusting method, which enables a less complex formation of these components.
  • the second end section of the nanotube is preferably surrounded by a second electrically conductive region which forms the bit line.
  • the nanostructure also functions as a shadow mask when the bit line is formed, as described in detail below.
  • the semiconducting nanostructure can have a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod.
  • a semiconducting nanostructure designed as a nanorod can have silicon germanium, indium phosphide and / or gallium arsenide. If the nanostructure is designed as a semiconducting nanotube, this can be a semiconducting carbon nanotube, a semiconducting carbon-boron nanotube or a semiconducting carbon-nitrogen nanotube.
  • the memory cell can be formed exclusively from dielectric material, metallic material and the material of the nanostructure.
  • the substrate can consist of polycrystalline or amorphous material.
  • the memory cell according to the invention can only consist of electrically conductive material, dielectric material and material of the nanostructure (preferably a carbon nanotube).
  • the memory cell can be manufactured without expensive semiconductor technology processes.
  • a polycrystalline or amorphous material that is to say a non-single-crystalline material, can be used as the substrate in order to produce the memory cell.
  • An expensive, single-crystalline substrate for example a silicon wafer
  • any starting substrate can be used according to the invention.
  • the memory cell arrangement according to the invention which has a plurality of memory cells according to the invention, preferably in an essentially matrix-like arrangement, is a memory cell arrangement with a particularly high integration density. Refinements of the memory cell also apply to the memory cell arrangement.
  • the method according to the invention for producing a memory cell is described below. Refinements of the memory cell also apply to the method for producing the memory cell.
  • the vertical switching transistor and the memory capacitor are at least partially formed in and / or on a substrate.
  • the nanostructure can be formed essentially orthogonal to the surface of the substrate.
  • a first end portion of the nanostructure can be formed inside the substrate and a second end portion of the nanostructure can be formed outside the substrate.
  • the first end section of the nanostructure as the first source / drain region, the second end section of the nanostructure as the second source / drain region and an intermediate region of the nanostructure arranged between the two end sections as the channel Area of the vertical switching transistor designed as a field effect transistor.
  • a dielectric layer can be formed between the first end section of the nanostructure and the substrate, the first end section of the nanostructure as a first electrically conductive capacitor element, the dielectric layer as a capacitor dielectric and the substrate as a second electrically conductive one Capacitor element of the storage capacitor are formed.
  • Catalyst materials are formed to catalyze the formation of the nanostructure.
  • At least part of the intermediate region of the nanostructure can be surrounded by an electrically insulating ring structure which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ' ring structure can be surrounded by a first electrically conductive region which forms the gate electrode of the vertical switching transistor and the word line.
  • the second end section of the nanotube can be surrounded by a second electrically conductive region which forms the bit line.
  • the word line and / or the bit line and / or the gate electrode can be formed by covering an exposed or covered part of the nanostructure with electrically conductive material and at a predeterminable angle with respect to the nanostructure Etching agent for etching the electrically conductive material is directed onto the nanostructure covered with the electrically conductive material, such that . only such sub-areas of the electrically conductive
  • the described method according to the invention has the particular advantage that the number of lithography steps required to form the memory cell is reduced compared to the prior art. This is based, among other things, on the fact that the vertically oriented nanostructure can be used as a shadow mask in the directional etching of various layers, in particular when forming word and bit lines or when forming the electrically insulating ring structure as a gate-insulating layer.
  • a DRAM memory cell can be obtained which is a on a substrate
  • the described DRAM / FRAM concept of the invention has the advantages that self-adjusting stack formation of the vertical switching transistor on the storage capacitor enables the storage cell to be formed on a substrate that is not necessarily crystalline silicon that the memory cell arrangement of the invention can be stacked on one another in three dimensions, that required for a memory cell Space requirement on the surface of a substrate is reduced to 4F 2 , that it is possible to produce the memory cell according to the invention with a single lithographic process step (see description below), that a transistor architecture with an annular gate insulating region is possible, with all gate Electrodes are automatically coupled to form a self-adjusting word line.
  • a basic idea of the invention is that the growing up of the
  • Nanostructure in an etched trench, which serves as a template for the growth, is possible using the CVD process ("chemical vapor deposition"), wherein a germ site for the growth of nanotubes can be spatially defined by means of targeted application of catalyst material.
  • CVD process chemical vapor deposition
  • Another aspect of the invention can be seen in the fact that a nanostructure is used as an electrically conductive element of an integrated capacitor.
  • Another aspect is the use of a vertical transistor with a nanostructure.
  • Another aspect is the growth of a nanostructure with a high aspect ratio and the use thereof as a shadow mask (illustratively as an auxiliary structure) for forming the ring-like transistor gate (gate insulating layer and gate electrode) and for forming word and bit - Cables.
  • a vertically aligned nanostructure can be used for the self-aligned, stack-like formation of integrated components, for example a memory capacitor and a vertical switching transistor in a DRAM or FRAM memory cell.
  • FIG. IN shows a cross section, taken along a section line A-A from FIG. IM, a layer sequence at a further point in time during the method for producing a memory cell according to the first exemplary embodiment of the invention
  • FIG. 10 shows a cross-sectional view, taken along the section line A-A from FIG. IM, a memory cell according to a preferred exemplary embodiment of the invention
  • FIG. 2A shows a cross-sectional view of a layer sequence according to an alternative embodiment of the method according to the invention for producing a memory cell
  • FIG. 2B shows a cross-sectional view of a structuring arrangement according to a preferred exemplary embodiment of the invention
  • FIG. 2C shows a cross-sectional view of a layer sequence, taken along a section line B-B from FIG. 2B to explain the functionality of the structuring arrangement shown in FIG. 2B,
  • FIGS. 3A to 3F cross-sectional views of layer sequences at different times during a method for producing a memory cell according to a second exemplary embodiment of the invention
  • Figure 4 is a cross-sectional view of a memory cell according to another embodiment of the invention. A method for producing a memory cell according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A to 10.
  • a silicon nitride hard mask 102 is deposited on a doped silicon substrate 101, and a photoresist layer 103 is deposited on the silicon nitride hard mask 102 and using one lithography and one Structured etching process, so that a structuring window 104 is formed on the surface of the layer sequence 100.
  • an additional silicon dioxide layer could be deposited between the doped silicon substrate 101 and the silicon nitride hard mask 102, for example in order to separate the upper side of a capacitor to be formed later and the transistor to be formed later.
  • the doped silicon substrate 101 is optionally made of crystalline or polycrystalline silicon material.
  • the part of the silicon nitride hard mask 102 that is exposed in the structuring window 104 is removed using an anisotropic etching method.
  • the structuring window 104 has a lateral width F, where F represents the minimum structural dimension that can be achieved with a respective technology generation.
  • structuring window constriction regions 109 are introduced into the structuring window 104.
  • the lateral width of the exposed surface of the doped silicon substrate 101 is reduced to the width d, which is chosen such that the exposed surface area of the doped silicon substrate 101 has a suitable area in order to introduce a nanostructure therein. In other words, the requirement of the
  • Structuring window narrowing region 109 is only given if the value F with an available lithography resolution is significantly larger than a suitable lateral width of a trench, into which a nanostructure is to be introduced in a later method step.
  • Typical nanostructure diameters are in the range from approximately lnm to lOnm. Therefore, a significantly larger structuring width F which can be achieved minimally should be scaled down to a smaller value using the structuring window constriction regions 109 in order to obtain a suitably dimensioned trench in a further method step.
  • dimension d is on the order of a few tens of nm.
  • a is used using a suitable etching method
  • Trench 111 etched into the doped silicon substrate 101 The lateral extent of the trench is defined by means of the structuring window constriction regions 109 or by means of the structuring window 104.
  • the structuring window constriction regions 109 or by means of the structuring window 104.
  • Dopant concentration in the doped silicon substrate 101 can be further increased, for example using an ion implantation method or a diffusion method by introducing further doping atoms into the (pre-) doped silicon substrate 101, in order to increase the capacitance of a capacitor to be formed in subsequent method steps ,
  • the silicon nitride hard mask 102 and the structuring window constriction regions 109 are formed using a suitable etching method Embodiment are also made of silicon nitride material) removed. Furthermore, a dielectric layer 114 as a capacitor dielectric is deposited conformally on the surface of the layer sequence using a CVD process (“chemical vapor deposition”) or using an ALD process (“atomic layer deposition”). In a scenario in which the manufactured memory cell is to be used as an FRAM memory cell, a ferroelectric layer is deposited instead of a dielectric layer 114.
  • the thickness of the dielectric layer 114 is preferably set to approximately 10 nm, so that the lateral width of the trench 111 has an extent 1 of approximately 10 nm after the formation of the dielectric layer 114.
  • the depth t of the trench 111 is set in such a way that the capacitance of the DRAM memory capacitor to be subsequently formed does not fall below a value of approximately 20fF.
  • the dependence of the capacitance of the storage capacitor on the depth t is clearly attributable to the fact that the capacitance proportional to the capacitor plate area is greater, the longer the region of the dielectric layer between the doped silicon substrate 101 and one later in the trench 111 nanostructure to be introduced, that is, the larger t is.
  • a value in the range of I ⁇ is typically chosen for t.
  • the trench 111 can be partially filled with doped polysilicon after the formation of the dielectric layer 114 in order to achieve a particularly high capacitance of the storage capacitor.
  • iron material 117 is formed as a catalyst material for catalyzing the formation of carbon nanotubes on part of the dielectric layer 114.
  • an angle-selective etching Process iron material 117 removed from the surface of layer sequence 116 except for the area contained in trench 111.
  • a carbon nanotube 120 is grown orthogonal to the surface of the doped silicon substrate 101 such that a first end portion 120a inside the doped silicon substrate 101 and that a second end portion 120b of the carbon nanotube 120 outside the doped silicon substrate 101 101 is arranged.
  • the carbon nanotube 120 is grown using a CVD process by introducing acetylene or methane into the process chamber.
  • carbon and nitrogen or carbon, nitrogen and boron nanotubes can also be used as carbon nanotubes 120.
  • Doped nanotubes can also be used, or it can
  • Nanotubes can be doped in an additional process step.
  • the length of the carbon nanotube 120 can be controlled by dividing the process parameters. In particular, it is possible to form a plurality of carbon nanotubes in different
  • the growth of the carbon nanotube 120 takes place selectively on the iron material 117, the trench 111 serving as a template or as a guide for the growth. This ensures that vertical carbon nanotubes 120 are formed.
  • the aspect ratio can be adjusted by dividing the length of the carbon nanotube 120 in the vertical direction according to FIG. Alternatively, the length of the
  • Carbon nanotube 120 are controlled by applying a silicon dioxide layer, the thickness of which corresponds to the desired thickness of the carbon nanotube area outside of the substrate 101, to the layer sequence 119 with the already formed carbon nanotube and using a CMP process ("chemical mechanical polishing") ) is planarized, and by using a subsequent selective etching process, the silicon dioxide layer is removed. Furthermore, this time of the method is suitable for optionally doping the carbon nanotube in order to adjust the transistor and / or the capacitor properties.
  • a silicon dioxide layer the thickness of which corresponds to the desired thickness of the carbon nanotube area outside of the substrate 101
  • an intermediate region 120c of the carbon nanotube 120 and a second end section 120b of the carbon nanotube 120 as well as the partial region of the dielectric layer 114 arranged on the surface of the layer sequence 119 are covered with a first silicon dioxide Layer 123 covers which first silicon dioxide layer 123 later forms the gate insulating layer of the vertical switching transistor to be formed.
  • This deposition is carried out using a CVD process or an ALD process.
  • the thickness s of the conformally deposited first silicon dioxide layer 123 is approximately 5 nm.
  • an electrically conductive first titanium nitride layer 124 is deposited conformally on the surface of the layer sequence using an ALD method in a thickness u between approximately 10 nm and 30 nm.
  • tungsten can also be used as the material for this layer, which can be deposited using an ALD or a CVD method.
  • PVD metals can also be used, provided they can be deposited in a conformal manner.
  • the first titanium nitride layer 124 is processed in further method steps in such a way that a word line is formed for a DRAM memory cell.
  • the first titanium nitride layer 124 is partially removed from the surface of the layer sequence 122, the portion of the first titanium nitride layer 124 which is removed in this method step being determined in that an etchant for selectively etching titanium nitride material at such an angle on the layer sequence 122 is directed that only a desired partial area of the first titanium nitride layer 124 is covered by the etchant, whereas another partial area of the first titanium nitride layer 124 is protected from etching, since the carbon nanotube 120 (or more, in FIG. II Vertical carbon nanotubes (not shown) on adjacent surface areas of the substrate 101) shade surface areas of the substrate 101 from the etchant.
  • FIG. II The area of the surface of the layer sequence which is captured by the etchant is shown in FIG.
  • the later word line or the later gate electrode of the vertical switching transistor is formed by the part of the carbon nanotube 120 covered with the silicon dioxide layer 123 being covered with the first titanium nitride layer 124 and under one Predeterminable angle with respect to the carbon nanotube 120, an etchant for etching the first titanium nitride layer 124 is directed onto the carbon nanotube 120 covered with the first titanium nitride layer 124, in such a way that only such partial regions of the first titanium nitride layer 124 are protected against removal as a result of etching , Which
  • the carbon nanotube 120 which is covered with the silicon dioxide layer 123 and the first titanium nitride layer 124, clearly serves as a shadow mask for forming the word lines. Due to the spatial expansion of the conformally deposited first titanium nitride layer 124 on the
  • Carbon nanotube 120 ensures that the word line has a larger spatial extension than that Carbon nanotube 120 and the dielectric silicon dioxide layer 123, wherein all gate electrodes of memory cells on a substrate are coupled to one another by means of the word line. Furthermore, a ring-like structure can be formed as a gate electrode around the carbon nanotube 120.
  • a second silicon dioxide layer 131 is applied to the layer sequence 126 using a sputtering method.
  • the second silicon dioxide layer 131 can be applied using the spin-on-glass method.
  • the second silicon dioxide layer 131 is partially removed or etched back using a conformal etching method.
  • the thickness of the second silicon dioxide layer 131 in FIG. 1K is less than in FIG. 1J, and that after the method step, the side walls of the vertical arrangement composed of carbon nanotube 120, first silicon dioxide layer 123 and the first Titanium nitride layer 124 are free from covering with the second silicon dioxide layer 131.
  • the first titanium nitride layer 124 and the first silicon dioxide layer 123 are etched back using a selective etching method such that the second end section 120b of the carbon nanotube 120 is exposed. In this method step, a partial area of the second silicon dioxide layer 131 is also removed.
  • Silicon dioxide layer 138 as an intermetallic dielectric, directed and partially deposited on the layer sequence 135 selectively etched back to clean carbon nanotube 120. Furthermore, a second titanium nitride layer 139 is deposited conformally on the surface of the layer sequence obtained in this way, a bit line being formed from the second titanium nitride layer 139 in a later method step.
  • a directional, angle-selective etching method using an etching agent for etching the second titanium nitride layer 139 is used, similarly to the method step in the transition from FIG. 1H to FIG. II ,
  • etching agent is directed laterally at a predeterminable angle to the carbon nanotube 120 onto the layer sequence 137 in the direction 143 shown in FIG. IN, the area 142 covered by the etching agent being such that only a subarea of the second titanium nitride layer 139 is removed from the surface of the layer sequence 137.
  • This process step is clearly similar to the process step carried out in the transition from FIG. 1H to FIG. II, in which the word lines have been formed, but the structuring arrangement for executing this process step is oriented differently with respect to the layer sequence.
  • a fourth silicon dioxide layer 146 is applied as a cover layer to the layer sequence 141, for example using a CVD method.
  • the functionality of the memory cell 145 shown in FIG. 10 is described below in accordance with a preferred exemplary embodiment of the invention.
  • the memory cell 145 has a vertical switching transistor and a storage capacitor, the vertical switching transistor having the semiconducting carbon nanotube 120, which has been grown on part of the storage capacitor.
  • Storage capacitors are partly arranged in and partly on the doped silicon substrate 101.
  • the first end portion 120a of the carbon nanotube 120 is arranged inside the doped silicon substrate 101, and the second end portion 120b of the carbon nanotube 120 is arranged outside the substrate 101.
  • the vertical switching transistor is designed as a " field-effect transistor, the first source / drain region of the vertical transistor designed as a field-effect transistor being the first end section 120a of the carbon nanotube 120, the second end section 120b of the carbon nanotube being the second
  • the source / drain region of the vertical switching transistor forms, and the intermediate region 120c of the carbon nanotube 120 arranged between the two end sections 120a, 120b forms the channel region of the vertical switching transistor 120c of the carbon nanotube 120 is surrounded by an electrically insulating ring structure formed by the first silicon dioxide layer 123, which forms the gate-insulating layer of the vertical switching transistor, and that region of the first silicon dioxide layer 123 which has the electrically insulating ring structure is surrounded by the first titanium nitrid
  • the second end section 120b of the carbon nanotube 120 is partially surrounded by the electrically conductive second titanium nitride layer 139, which forms the bit line of the memory cell.
  • the memory- The capacitor of the memory cell 145 is formed by two electrically conductive capacitor elements (which in the integrated stacked capacitor represent the analogue to the capacitor plates of a conventional capacitor) and by a dielectric layer as
  • Capacitor dielectric between the two electrically conductive capacitor elements The first end section 120a of the carbon nanotube 120 forms the first electrically conductive capacitor element, the doped silicon substrate 101 forms the second electrically conductive capacitor element and that portion of the dielectric layer 114 by means of which the first end section 120a of the carbon nanotube 120 is separated from the doped silicon substrate 101, forms the capacitor dielectric.
  • the conductivity of the carbon nanotube 120, in particular in the intermediate region 120c is influenced characteristically as a result of the field effect, so that by applying a suitable voltage to the first titanium nitride layer 124 the memory cell 145 shown in FIG. 10 of a memory cell arrangement with a plurality of memory cells can be selected.
  • a suitable voltage to the first titanium nitride layer 124 the memory cell 145 shown in FIG. 10 of a memory cell arrangement with a plurality of memory cells can be selected.
  • the ring-like structure of the gate electrode and gate insulating layer particularly good controllability is made possible according to the invention.
  • electrical charge is programmed into the stack capacitor via the second titanium nitride layer 139, which is designed as a bit line.
  • the presence of electrical charge in the storage capacitor can be interpreted as a state with a logic value "1", whereas a state in which no electrical charge is stored in the storage capacitor is interpreted as a logical value "0". If the information stored in the memory cell 145 is to be read out, the vertical switching transistor is brought into a conductive state by applying a suitable voltage to the word line 124, so that charge carriers stored in the memory capacitor may be placed on the bit line 139 flow where a corresponding electrical signal can be detected. This signal is characteristic of the information stored in the storage capacitor.
  • the storage capacitor can be formed by inserting the layer sequence 106 into the doped silicon substrate 101 a trench is first etched by lining this trench with a silicon dioxide dielectric 201 by means of thermal oxidation of the doped silicon substrate 101 or by depositing silicon dioxide material on the walls of the trench, and by the resulting trench being doped with doped polycrystalline silicon material 202 is filled.
  • the layer sequence 200 shown in FIG. 2A is thereby obtained.
  • the memory capacitor of the memory cell according to the invention is formed by the doped silicon substrate 101 and the doped polysilicon material 202 as the first and second electrically conductive capacitor elements and by the silicon dioxide dielectric 201 as a capacitor dielectric.
  • a carbon nanotube to be applied further only fulfills the functionality of the switching transistor of the memory cell.
  • Method steps for forming the memory cell take place starting from the layer sequence 200 analogous to that described in FIG. IC to FIG. 10.
  • FIGS. 2B, 2C A preferred exemplary embodiment of the structuring arrangement according to the invention is described below with reference to FIGS. 2B, 2C.
  • the structuring arrangement 210 extends essentially orthogonally to the surface of a substrate 211
  • the structuring arrangement has material 214 to be structured on the part of the carbon nanotubes 212, 213 arranged outside the substrate 211. Furthermore, the
  • 15 structuring arrangement 210 have further layers 215, 216, 217, of which the first and second
  • Carbon nanotubes 212, 213 can be partially surrounded.
  • the structuring arrangement 210 has an etchant supply device 218, which is set up in this way
  • 25 partial areas of the material 214 to be structured are protected against removal due to etching, which are shaded from the carbon nanotubes 212, 213 with respect to the etchant.
  • the carbon nanotubes 212, 213 clearly serve as
  • Mask by means of which mask is determined which areas are to be removed from the material 214 to be structured. On the basis of the geometric relationships shown in FIG. 2B, the area 219 covered by the etching agent is predetermined
  • the etching medium direction 220 determines the carbon nanotubes 212, 213.
  • the distance between adjacent carbon nanotubes 212, 213 from one another by dividing the height of that area of the carbon nanotubes 212, 213 that protrudes from the substrate 211, and by selecting the arrangement and angle of incidence of the etchant supply device 218, which areas of the material 214 to be structured 214 are to be removed can be selected.
  • FIG. 2B only regions of material 214 to be structured on the upper and right edge regions of the carbon nanotubes 212, 213 according to FIG. 2B are removed.
  • the third further layer which partially covers the carbon nanotubes 212, 213, is protected against removal due to etching.
  • FIG. 2C A cross-sectional view 230 of the structuring arrangement 210 shown in FIG. 2B, taken along the section line B-B shown in FIG. 2B, is described below with reference to FIG. 2C.
  • the material 214 to be structured is structured on the surface of the substrate 211 as a result of the directional, angle-dependent etching into parallel paths, which can be used, for example, as a bit or word line.
  • FIGS. 3A to 3F A method for producing a memory cell according to a second preferred exemplary embodiment of the invention is described below with reference to FIGS. 3A to 3F.
  • carbon nanotubes 303 are grown in an aluminum oxide substrate 301 with pores 302 incorporated therein according to the method described in [3], [4].
  • the pores 302 in the aluminum oxide substrate 301 preferably form a square arrangement.
  • a lower region of the aluminum oxide substrate 301 according to FIG. 3B is removed using a suitable etching method, so that a first end section 303a of the carbon nanotubes 303 is exposed.
  • a dielectric layer 321 is deposited using the CVD or the ALD method on the lower main surface of the aluminum oxide substrate 301 as shown in FIG. 3C and on that portion of the carbon nanotubes 303 that exposed outside of the alumina substrate 301.
  • a poly-silicon layer 331 is deposited on the lower surface of the layer sequence 320 according to FIG. 3D, as a result of which one of the two electrically conductive elements of the later storage capacitor is formed.
  • a metal or a metal nitride for example titanium nitride
  • a metal nitride for example titanium nitride
  • the layer sequence 340 is attached to a substrate 341, for example by means of wafer bonding.
  • the remaining region of the aluminum oxide substrate 301 is removed from the layer using a suitable etching method Surface of the layer sequence 340 removed. This results in a layer sequence 350 which is similar to the layer sequence 119 from FIG. IG.
  • the further processing for forming a memory cell according to the invention based on FIG. 3F can be carried out using method steps as described starting from FIG. IG up to FIG. 10.
  • a memory cell 400 according to another exemplary embodiment of the invention is described below with reference to FIG.
  • the memory cell 400 has a polycrystalline silicon substrate 401 on which a first silicon dioxide layer 402 is formed.
  • a thin first titanium nitride layer 403 is applied to the first silicon dioxide layer 402.
  • a second silicon dioxide layer 404 is applied to the first titanium nitride layer 403.
  • the layers 402 to 404 and a surface area of the silicon substrate 401 are subjected to a suitable etching method, so that a through hole is etched through the layers 404 to 402, which through hole extends into a surface area of the silicon substrate 401.
  • An electrically insulating third silicon dioxide layer 405 is formed along the inner wall of the hole.
  • a carbon nanotube 406 is grown in the hole.
  • a second titanium nitride layer 407 is applied to the layer sequence thus obtained.
  • a region of the silicon substrate 401 is the first to be electrically conductive
  • Capacitor element a region of the third silicon dioxide layer 405 as a capacitor dielectric and a region of the carbon nanotube 406 as a second electrically conductive capacitor element a storage capacitor.
  • a switching field effect transistor is formed from a central region of the carbon nanotube 406 as a channel region, a lower section according to FIG. 4 of the carbon nanotube 406 as the first source / drain region, a boundary section between the carbon nanotube 406 and the second titanium nitride layer 407 as the second source / drain region and the first titanium nitride layer 403 as an annular gate - electrode.
  • Carbon nanotube surrounding first titanium nitride layer 403 in a ring-like manner can be controlled particularly precisely.

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Abstract

L'invention concerne une cellule de mémoire, un ensemble de cellules de mémoire, un ensemble de structuration et un procédé de fabrication d'une cellule de mémoire. Cette cellule de mémoire présente un transistor de commutation vertical et un condensateur de mémorisation, lequel transistor de commutation vertical présente une nanostructure semiconductrice formée par croissance sur au moins une partie dudit condensateur de mémorisation.
EP03778241A 2002-10-31 2003-10-29 Cellule de memoire, ensemble de cellules de memoire, ensemble de structuration et procede de fabrication d'une cellule de memoire Withdrawn EP1556893A2 (fr)

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DE10250834 2002-10-31
DE10250834A DE10250834A1 (de) 2002-10-31 2002-10-31 Speicherzelle, Speicherzellen-Anordnung, Strukturier-Anordnung und Verfahren zum Herstellen einer Speicherzelle
PCT/DE2003/003589 WO2004040644A2 (fr) 2002-10-31 2003-10-29 Cellule de memoire, ensemble de cellules de memoire, ensemble de structuration et procede de fabrication d'une cellule de memoire

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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7316061B2 (en) 2003-02-03 2008-01-08 Intel Corporation Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface
DE10331528A1 (de) * 2003-07-11 2005-02-03 Infineon Technologies Ag DRAM-Halbleiterspeicherzelle sowie Verfahren zu deren Herstellung
WO2007022359A2 (fr) * 2005-08-16 2007-02-22 The Regents Of The University Of California Transistors a effet de champ a nanofils en silicium integres verticaux et procedes de fabrication
US7608877B2 (en) * 2005-12-06 2009-10-27 Canon Kabushiki Kaisha Circuit device having capacitor and field effect transistor, and display apparatus therewith
US7365018B2 (en) * 2005-12-28 2008-04-29 Sandisk Corporation Fabrication of semiconductor device for flash memory with increased select gate width
FR2897204B1 (fr) * 2006-02-07 2008-05-30 Ecole Polytechnique Etablissem Structure de transistor vertical et procede de fabrication
DE102006009721B4 (de) * 2006-03-02 2011-08-18 Qimonda AG, 81739 Nanodraht (Nanowire)-Speicherzelle und Verfahren zu deren Herstellung
DE102006013245A1 (de) * 2006-03-22 2007-10-04 Infineon Technologies Ag Verfahren zur Ausbildung von Öffnungen in einer Matrizenschicht und zur Herstellung von Kondensatoren
GB0611557D0 (en) * 2006-06-12 2006-07-19 Univ Belfast Nanostructured systems and a method of manufacture of the same
US7667260B2 (en) * 2006-08-09 2010-02-23 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US7795671B2 (en) * 2007-01-04 2010-09-14 Fairchild Semiconductor Corporation PN junction and MOS capacitor hybrid RESURF transistor
US7858506B2 (en) 2008-06-18 2010-12-28 Micron Technology, Inc. Diodes, and methods of forming diodes
US9099537B2 (en) * 2009-08-28 2015-08-04 International Business Machines Corporation Selective nanotube growth inside vias using an ion beam
US8436447B2 (en) * 2010-04-23 2013-05-07 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US8871576B2 (en) 2011-02-28 2014-10-28 International Business Machines Corporation Silicon nanotube MOSFET
KR102295966B1 (ko) * 2014-08-27 2021-09-01 삼성전자주식회사 나노와이어를 이용한 반도체 소자 형성 방법
CN105810750B (zh) * 2014-12-29 2019-02-01 中芯国际集成电路制造(上海)有限公司 一种碳纳米管神经元器件及其制作方法
US9923140B2 (en) * 2016-04-20 2018-03-20 Sandisk Technologies Llc Low power barrier modulated cell for storage class memory
WO2019130127A1 (fr) * 2017-12-26 2019-07-04 King Abdullah University Of Science And Technology Nanotube de silicium, transistor à capacité négative à couche ferroélectrique et méthode de fabrication

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256588A (en) * 1992-03-23 1993-10-26 Motorola, Inc. Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
US5610441A (en) * 1995-05-19 1997-03-11 International Business Machines Corporation Angle defined trench conductor for a semiconductor device
KR100223807B1 (ko) * 1997-06-04 1999-10-15 구본준 반도체 소자의 제조방법
US6228706B1 (en) * 1999-08-26 2001-05-08 International Business Machines Corporation Vertical DRAM cell with TFT over trench capacitor
WO2001057917A2 (fr) * 2000-02-07 2001-08-09 Xidex Corporation Systeme et procede de fabrication de dispositifs logiques comportant des transistors a nanotubes de carbone
KR100360476B1 (ko) * 2000-06-27 2002-11-08 삼성전자 주식회사 탄소나노튜브를 이용한 나노 크기 수직 트랜지스터 및 그제조방법
DE10036897C1 (de) * 2000-07-28 2002-01-03 Infineon Technologies Ag Feldeffekttransistor, Schaltungsanordnung und Verfahren zum Herstellen eines Feldeffekttransistors
DE10118405A1 (de) * 2001-04-12 2002-10-24 Infineon Technologies Ag Heterostruktur-Bauelement
CN1615537A (zh) * 2001-12-12 2005-05-11 宾夕法尼亚州立大学 化学反应器模板:牺牲层的制备和模板的应用

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004040644A3 *

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