EP1556893A2

EP1556893A2 - Memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell

Info

Publication number: EP1556893A2
Application number: EP03778241A
Authority: EP
Inventors: Andrew Graham; Franz Hofmann; Wolfgang HÖNLEIN; Johannes Kretz; Franz Kreupl; Erhard Landgraf; Richard Johannes Luyken; Wolfgang RÖSNER; Thomas Schulz; Michael Specht
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2002-10-31
Filing date: 2003-10-29
Publication date: 2005-07-27
Also published as: WO2004040644A3; US20050276093A1; WO2004040644A2; DE10250834A1

Abstract

The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

Description

description

Memory cell, memory cell arrangement, structuring arrangement and method for producing a memory cell

The invention relates to a memory cell, a memory cell arrangement, a structuring arrangement and a method for producing a memory cell.

Due to the rapid development in computer technology, there is a need to store ever larger amounts of data. For silicon microtechnology, this means that progressive miniaturization while increasing the integration density of a semiconductor memory in a semiconductor substrate is sought.

An important concept in the development of semiconductor memories is the concept of the DRAM memory cell ("dynamic random access memory"). A DRAM memory is a dynamic semiconductor memory in whose memory matrix there is a capacitor per bit as the memory cell. Binary information is stored by charging this capacity. A memory cell is addressed via a switching transistor, via which the capacitance is coupled to a bit line. In order to read out or program the memory cell, the word line is brought to a sufficiently high electrical potential so that the switching transistor becomes conductive and the memory cell is coupled to the bit line. Depending on the storage information to be stored (logical value "0" or "1"), the capacity is loaded or unloaded during programming. When the information is read out, a voltage change is generated on the bit line due to the stored charge, which is detectable and which is a characteristic measure of the information stored in the memory cell. Due to the small capacitance of the memory transistor of a memory cell and due to unavoidable leakage currents, the charge content of the capacitor must be periodically refreshed.

A DRAM memory cell is usually designed as an integrated semiconductor circuit. When developing a DRAM memory device with increasingly small dimensions, i.e. with increasingly high memory densities, the problem arises that the expansion of each component of a DRAM memory cell in each dimension has at least the size F, where F is that in a respective

Technology generation is the minimum attainable structural dimension. In addition, the storage capacitor is difficult to scale. This limits the miniaturizability of DRAM memory cells.

Another important concept in semiconductor memories is the so-called FRAM concept ("ferroelectric random access memory").

According to one implementation, a FRAM memory cell is a MOS field-effect transistor, in which a ferroelectric layer is provided instead of the gate insulating layer. A preferred direction of the permanent ferroelectric dipole moments in the ferroelectric layer, ie the programming of the FRAM memory cell, is carried out by means of a suitably selected gate voltage. Depending on the fact that the preferred direction of the ferroelectric dipoles in the ferroelectric layer has been set as a result of a programming which has been carried out beforehand by applying a suitable gate voltage, the electrical conductivity of the channel region adjoining the ferroelectric layer is characteristically influenced. In other words, the strength of the electrical current depends between the two source / drain regions, between which the channel region is arranged, depends on the state in which the ferroelectric dipoles of the ferroelectric layer are as a result of a programming event which has taken place previously.

According to an alternative concept for a FRAM memory cell, a structure is used as in the DRAM memory cell described above, with the difference that a ferroelectric (for example lead zirconate titanate, Pb (Zrι_ _x Ti _x )) is used between the capacitor electrodes instead of a dielectric. 0 ₃ , PZT) is used. From the hysteresis curve of a ferroelectric can be concluded that ^'having the ferroelectric a positive or a negative permanent polarization, depending on whether when programming a positive or negative field strength (or voltage) is applied. Reading is done by applying a positive voltage to the bit line. If a negative polarization is contained in the ferroelectric, U polarization takes place, so that a charge packet flows to the bit line. With positive permanent polarization, the polarization changes only slightly, so that almost no charge flows to the bit line.

Even when forming a FRAM memory cell, the problem described above with reference to the DRAM memory cell arises that the minimally achievable structural dimension is limited by the one-dimensional structural resolution F which can be minimally achieved within the framework of a respective semiconductor technology generation.

Furthermore, in the case of a conventional semiconductor memory cell based on a MOSFET, with increasing miniaturization, the problem arises that the length of the conductive channel in particular decreases, which has disruptive short-channel effects. Conventional concepts for an integrated memory cell are therefore increasingly encountering fundamental physical problems. Nanotubes, in particular carbon nanotubes, are regarded as a possible successor to conventional semiconductor electronics. An overview of this technology is given, for example, [1].

A carbon nanotube is a single-walled or walled tube-like carbon compound. In the case of a multi-walled nanotube, at least one inner nanotube is coaxially surrounded by an outer nanotube. Single-walled nanotubes typically have diameters of approximately 1 nm, and the length of a nanotube can be several 100 nm. The ends of a nanotube are often terminated with half a fullerene molecule. Nanotubes often have good electrical conductivity, which is why nanotubes are suitable for the construction of circuits with dimensions in the nanometer range. Because of the electrical conductivity of nanotubes and because of the adjustability of this conductivity (for example by applying an external electric field or by doping the nanotube with boron nitride), nanotubes are suitable for a large number of applications, for example for electrical coupling technology in integrated circuits, for components in microelectronics and as an electron emitter.

In addition to carbon nanotubes, nanotubes made from other materials, for example on tungsten sulfide and other chalcogenides, are also known.

In addition to nanotubes are nanorods ("nanorods") as

Known nano structures. The nanorods also have a diameter in the nanometer range and can be several micrometers long. Typical materials for nanorods are the semiconductors silicon, germanium, indium phosphide and gallium arsenide. Both nanotubes and nanorods can be separated from the gas phase using catalytic processes. For example, an overview of the technology of nanostructures is given [2].

It is known from [3], [4] that highly ordered, two-dimensional structures of carbon anotubes can be grown in an aluminum oxide template. For this purpose, a substrate made of aluminum oxide with a two-dimensional arrangement of hexagonal pores is used, which pores serve as a template for the growth of carbon nanotubes. According to the process described in [3], [4], cobalt is deposited as a catalyst for growing nanotubes on the bottom layer in the pores. By introducing acetylene, carbon nanotubes are subsequently grown in the pores, with both aluminum and cobalt catalytically supporting the growth.

It is known from [5] to make a through hole in a thick gate electrode layer and to grow a vertical nano-element in it. A vertical field effect transistor with the nanoelement as the channel region is thereby obtained, the electrical conductivity of the channel region being controllable by means of the gate electrode region surrounding the nanoelement along almost its entire longitudinal extent.

[6] discloses a method of manufacturing a semiconductor device in which a triple copolymer block is formed with a first copolymer as an inner column, a second copolymer as an outer column and a third copolymer surrounding the second copolymer.

[7] discloses a field effect transistor, a

Circuit arrangement and a method for producing a Field effect transistor, wherein a vertical nano-element forms a channel of the field effect transistor.

The invention is based on the problem of creating a memory cell with a memory capacitor, which

Memory cell can be produced in a miniaturized manner, and in which memory cell short-channel effects are avoided with a field effect transistor contained in the memory cell.

The problem is solved by a memory cell, a

Memory cell arrangement, a structuring arrangement and a method for producing a memory cell with the features according to the independent claims.

According to the invention, a memory cell with a vertical switching transistor and a storage capacitor is provided, the vertical switching transistor having a semiconducting nanostructure which has been grown on at least part of the storage capacitor.

Furthermore, a memory cell arrangement with a plurality of memory cells with the above-mentioned features is created according to the invention.

It is also a method of making one

Memory cell provided, in which a vertical switching transistor and a storage capacitor are formed, a semiconducting nanostructure of the vertical switching transistor being formed, which is grown on at least part of the storage capacitor.

A structuring arrangement is also created, with a nanostructure which extends essentially orthogonally to the surface of a substrate and which is at least partially arranged outside the substrate, with material to be structured on the part of the nanostructure arranged outside the substrate, with an etchant. Feeding device which is set up in such a way that it can be used to etch the material to be structured at a predeterminable angle to the nanostructure onto the nanostructure covered with the material to be structured in such a way that only those partial areas of the material to be structured can be removed before being removed as a result of etching are protected, which are shaded by the nanostructure with respect to the etchant.

The memory cell according to the invention can clearly be used as a DRAM memory cell or as a FRAM memory cell. A memory cell of the invention can be selected in a memory cell arrangement by means of the vertical switching transistor, so that the information stored in the memory capacitor can be read out or programmed. The vertical switching transistor has a semiconducting nanostructure, for example a carbon nanotube, a carbon-nitrogen nanotube, or a carbon-boron-nitrogen nanotube. The memory cell according to the invention can be miniaturized by using a nanostructure in the vertical switching transistor. For example, a vertical carbon nanotube, which can be used as a nanostructure, has a dimension of one or a few nanometers in cross section, so that in principle one

Memory cell with a space requirement of this magnitude can be designed according to the invention. By designing the switching transistor with the semiconducting nanostructure as a vertical transistor, miniaturization is simultaneously possible while avoiding short-channel effects. In the

Design as a carbon nanotube, the nanostructure can have an extent of hundreds of nanometers or even a μ in the vertical direction and therefore the channel region can be made sufficiently long as part of the nanostructure so that disruptive short-channel effects are avoided. The vertical switching transistor and the storage capacitor are preferably formed at least partially in and / or at least partially on a substrate.

The substrate is preferably a semiconductor substrate and in particular a silicon substrate.

The nanostructure can extend substantially orthogonally to the surface of the substrate. A first end section of the nanostructure is preferably arranged inside the substrate and a second end section of the nanostructure is arranged outside the substrate.

By forming a partial region of the nanostructure outside the substrate in the vertical direction, this part can serve as a “template” for the formation and in particular for the selective removal of material on the nanostructure and / or on the substrate. For example, an etchant can be directed onto the nanostructure and the substrate at a predetermined angle, the area on the nanotube or on the substrate which is shaded by the nanotube with respect to the etchant being protected from etching. With this idea according to the invention, it is possible to form a variety of semiconductor technology structures.

The vertical switching transistor is preferably a field effect transistor. In this case, the first section of the nanostructure can have a first source / drain region, the second end section of the nanostructure can have a second source / drain region and an intermediate region of the nanostructure arranged between the two end sections can have a channel Form the area of the vertical switching transistor.

Furthermore, a dielectric layer can be located between the first end section of the nanostructure and the substrate be formed, the first end portion of the nanostructure forming a first electrically conductive capacitor element, the dielectric layer forming a capacitor dielectric and the substrate forming a second electrically conductive capacitor element of the storage capacitor.

According to this concept, the nanostructure fulfills both the functionality as a component of the vertical switching transistor and the functionality as the first conductive one

Capacitor element of the storage capacitor. The first electrically conductive capacitor element of the storage capacitor configured as an integrated component is the analogue to a capacitor plate of a conventional capacitor. By making the nanostructure a

Serves double function as a component of the vertical switching transistor and the capacitor element, the electrical contacting is simplified and a separate element is saved, so that the memory cell according to the invention can be produced with little effort. - ...

Instead of the dielectric layer, a layer made of a ferroelectric material can be provided. According to this embodiment, the memory cell according to the invention can be used as an FRAM memory cell with the functionality described above.

Catalyst material for catalyzing the formation of the nanostructure can be arranged between at least part of the dielectric layer and the nanostructure.

The spatial growth of the nano structures can be predetermined by means of the catalyst material. Therefore, it is by providing an orderly arrangement of not necessarily contiguous areas of

Catalyst material enables orderly growth of the nanostructure. It should be noted that In particular, if the nanostructure is designed as a carbon nanotube, iron, cobalt or nickel is a good choice as the catalyst material.

Furthermore, at least part of the intermediate region of the nanostructure can be surrounded by an electrically insulating ring structure, which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ring structure can be surrounded by a first electrically conductive region, which forms the gate electrode of the vertical switching transistor and the word line.

By separating the semiconducting nanostructure in the vicinity of its intermediate region from an electrically insulating one

Surrounded ring structure, a gate insulating layer is provided, which is surrounded by the first electrically conductive region functioning as a gate electrode. By applying a suitable voltage to the electrically conductive area, the conductivity of the nanostructure can be influenced in the intermediate area of the nanostructure, functioning as a channel area, so that the nanostructure together with the electrically insulating ring structure and the first electrically conductive area Functionality of a

Field effect transistor met. By using an annular gate electrode, the amplitude of an electric field generated by applying an electrical voltage to the gate electrode near the nanostructure can be made particularly large due to an electrostatic peak effect, so that particularly precise control of the electrical conductivity of the channel region is made possible is.

It should be noted that the vertically grown one

Nanostructure can also act as a shadow mask for the formation of the first electrically conductive region. Therefore the components mentioned are formed by means of a self-adjusting method, which enables a less complex formation of these components.

The second end section of the nanotube is preferably surrounded by a second electrically conductive region which forms the bit line. The nanostructure also functions as a shadow mask when the bit line is formed, as described in detail below.

The semiconducting nanostructure can have a semiconducting nanotube, a bundle of semiconducting nanotubes, or a semiconducting nanorod. A semiconducting nanostructure designed as a nanorod can have silicon germanium, indium phosphide and / or gallium arsenide. If the nanostructure is designed as a semiconducting nanotube, this can be a semiconducting carbon nanotube, a semiconducting carbon-boron nanotube or a semiconducting carbon-nitrogen nanotube.

The memory cell can be formed exclusively from dielectric material, metallic material and the material of the nanostructure. The substrate can consist of polycrystalline or amorphous material.

In other words, the memory cell according to the invention can only consist of electrically conductive material, dielectric material and material of the nanostructure (preferably a carbon nanotube). In this case, the memory cell can be manufactured without expensive semiconductor technology processes. Another important advantage in this connection is that a polycrystalline or amorphous material, that is to say a non-single-crystalline material, can be used as the substrate in order to produce the memory cell. An expensive, single-crystalline substrate (for example a silicon wafer) is thus avoided in the production of the memory cell. It can in principle, any starting substrate can be used according to the invention.

The memory cell arrangement according to the invention, which has a plurality of memory cells according to the invention, preferably in an essentially matrix-like arrangement, is a memory cell arrangement with a particularly high integration density. Refinements of the memory cell also apply to the memory cell arrangement.

The method according to the invention for producing a memory cell is described below. Refinements of the memory cell also apply to the method for producing the memory cell.

According to a development of the method according to the invention for producing a memory cell, the vertical switching transistor and the memory capacitor are at least partially formed in and / or on a substrate.

The nanostructure can be formed essentially orthogonal to the surface of the substrate.

A first end portion of the nanostructure can be formed inside the substrate and a second end portion of the nanostructure can be formed outside the substrate.

Preferably, the first end section of the nanostructure as the first source / drain region, the second end section of the nanostructure as the second source / drain region and an intermediate region of the nanostructure arranged between the two end sections as the channel Area of the vertical switching transistor designed as a field effect transistor. A dielectric layer can be formed between the first end section of the nanostructure and the substrate, the first end section of the nanostructure as a first electrically conductive capacitor element, the dielectric layer as a capacitor dielectric and the substrate as a second electrically conductive one Capacitor element of the storage capacitor are formed.

In the method, there can be between at least part of the dielectric layer and the nanostructure

Catalyst materials are formed to catalyze the formation of the nanostructure.

Furthermore, at least part of the intermediate region of the nanostructure can be surrounded by an electrically insulating ring structure which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ^' ring structure can be surrounded by a first electrically conductive region which forms the gate electrode of the vertical switching transistor and the word line.

The second end section of the nanotube can be surrounded by a second electrically conductive region which forms the bit line.

In particular, the word line and / or the bit line and / or the gate electrode can be formed by covering an exposed or covered part of the nanostructure with electrically conductive material and at a predeterminable angle with respect to the nanostructure Etching agent for etching the electrically conductive material is directed onto the nanostructure covered with the electrically conductive material, such that _. only such sub-areas of the electrically conductive

Protect material from removal due to etching, which parts of the nanostructure with respect to the Etchant are shadowed.

The described method according to the invention has the particular advantage that the number of lithography steps required to form the memory cell is reduced compared to the prior art. This is based, among other things, on the fact that the vertically oriented nanostructure can be used as a shadow mask in the directional etching of various layers, in particular when forming word and bit lines or when forming the electrically insulating ring structure as a gate-insulating layer.

In the manner described, a DRAM memory cell can be obtained which is a on a substrate

Space requirement of only 4F ² , where F is the minimum structural dimension that can be achieved with a technology generation. This increases the integration density compared to the prior art. Furthermore, because of the vertical arrangement of the memory cell according to the invention, it is possible to stack several layers of memory cells on top of one another, and thus to obtain a three-dimensional integration of memory cells, which further increases the integration density. It should be noted in particular that the concept according to the invention can also be used to form an FRAM memory cell. For this purpose, the dielectric layer of the capacitor dielectric must be formed from a ferroelectric material.

The described DRAM / FRAM concept of the invention has the advantages that self-adjusting stack formation of the vertical switching transistor on the storage capacitor enables the storage cell to be formed on a substrate that is not necessarily crystalline silicon that the memory cell arrangement of the invention can be stacked on one another in three dimensions, that required for a memory cell Space requirement on the surface of a substrate is reduced to 4F ² , that it is possible to produce the memory cell according to the invention with a single lithographic process step (see description below), that a transistor architecture with an annular gate insulating region is possible, with all gate Electrodes are automatically coupled to form a self-adjusting word line.

A basic idea of the invention is that the growing up of the

Nanostructure in an etched trench, which serves as a template for the growth, is possible using the CVD process ("chemical vapor deposition"), wherein a germ site for the growth of nanotubes can be spatially defined by means of targeted application of catalyst material. Another aspect of the invention can be seen in the fact that a nanostructure is used as an electrically conductive element of an integrated capacitor. Another aspect is the use of a vertical transistor with a nanostructure. Another aspect is the growth of a nanostructure with a high aspect ratio and the use thereof as a shadow mask (illustratively as an auxiliary structure) for forming the ring-like transistor gate (gate insulating layer and gate electrode) and for forming word and bit - Cables. Furthermore, one aspect of the invention is to be seen in the fact that a vertically aligned nanostructure can be used for the self-aligned, stack-like formation of integrated components, for example a memory capacitor and a vertical switching transistor in a DRAM or FRAM memory cell.

Exemplary embodiments are shown in the figures and are explained in more detail below.

Show it: 1A to IM show cross-sectional views of layer sequences at different times during a method for producing a memory cell according to a first exemplary embodiment of the invention,

FIG. IN shows a cross section, taken along a section line A-A from FIG. IM, a layer sequence at a further point in time during the method for producing a memory cell according to the first exemplary embodiment of the invention,

FIG. 10 shows a cross-sectional view, taken along the section line A-A from FIG. IM, a memory cell according to a preferred exemplary embodiment of the invention,

2A shows a cross-sectional view of a layer sequence according to an alternative embodiment of the method according to the invention for producing a memory cell,

FIG. 2B shows a cross-sectional view of a structuring arrangement according to a preferred exemplary embodiment of the invention,

FIG. 2C shows a cross-sectional view of a layer sequence, taken along a section line B-B from FIG. 2B to explain the functionality of the structuring arrangement shown in FIG. 2B,

FIGS. 3A to 3F cross-sectional views of layer sequences at different times during a method for producing a memory cell according to a second exemplary embodiment of the invention,

Figure 4 is a cross-sectional view of a memory cell according to another embodiment of the invention. A method for producing a memory cell according to a first exemplary embodiment of the invention is described below with reference to FIGS. 1A to 10.

In order to obtain the layer sequence 100 shown in FIG. 1A, a silicon nitride hard mask 102 is deposited on a doped silicon substrate 101, and a photoresist layer 103 is deposited on the silicon nitride hard mask 102 and using one lithography and one Structured etching process, so that a structuring window 104 is formed on the surface of the layer sequence 100. As an alternative to the exemplary embodiment described, an additional silicon dioxide layer (not shown in the figures) could be deposited between the doped silicon substrate 101 and the silicon nitride hard mask 102, for example in order to separate the upper side of a capacitor to be formed later and the transistor to be formed later. The doped silicon substrate 101 is optionally made of crystalline or polycrystalline silicon material.

In order to obtain the layer sequence 106 shown in FIG. 1B, the part of the silicon nitride hard mask 102 that is exposed in the structuring window 104 is removed using an anisotropic etching method. As shown in FIG. 1A, FIG. IB, the structuring window 104 has a lateral width F, where F represents the minimum structural dimension that can be achieved with a respective technology generation.

In order to obtain the layer sequence 108 shown in FIG. IC, structuring window constriction regions 109 are introduced into the structuring window 104. As a result, the lateral width of the exposed surface of the doped silicon substrate 101 is reduced to the width d, which is chosen such that the exposed surface area of the doped silicon substrate 101 has a suitable area in order to introduce a nanostructure therein. In other words, the requirement of the

Structuring window narrowing region 109 is only given if the value F with an available lithography resolution is significantly larger than a suitable lateral width of a trench, into which a nanostructure is to be introduced in a later method step. Typical nanostructure diameters (for example for carbon nanotubes) are in the range from approximately lnm to lOnm. Therefore, a significantly larger structuring width F which can be achieved minimally should be scaled down to a smaller value using the structuring window constriction regions 109 in order to obtain a suitably dimensioned trench in a further method step. Typically, dimension d is on the order of a few tens of nm.

In order to obtain the layer sequence 110 shown in FIG. 1D, a is used using a suitable etching method

Trench 111 etched into the doped silicon substrate 101. The lateral extent of the trench is defined by means of the structuring window constriction regions 109 or by means of the structuring window 104. In a further optional process step, the

Dopant concentration in the doped silicon substrate 101 can be further increased, for example using an ion implantation method or a diffusion method by introducing further doping atoms into the (pre-) doped silicon substrate 101, in order to increase the capacitance of a capacitor to be formed in subsequent method steps ,

In order to obtain the layer sequence 113 shown in FIG. 1E, the silicon nitride hard mask 102 and the structuring window constriction regions 109 (those according to that described) are formed using a suitable etching method Embodiment are also made of silicon nitride material) removed. Furthermore, a dielectric layer 114 as a capacitor dielectric is deposited conformally on the surface of the layer sequence using a CVD process (“chemical vapor deposition”) or using an ALD process (“atomic layer deposition”). In a scenario in which the manufactured memory cell is to be used as an FRAM memory cell, a ferroelectric layer is deposited instead of a dielectric layer 114. The thickness of the dielectric layer 114 is preferably set to approximately 10 nm, so that the lateral width of the trench 111 has an extent 1 of approximately 10 nm after the formation of the dielectric layer 114. It should also be noted that the depth t of the trench 111 is set in such a way that the capacitance of the DRAM memory capacitor to be subsequently formed does not fall below a value of approximately 20fF. The dependence of the capacitance of the storage capacitor on the depth t is clearly attributable to the fact that the capacitance proportional to the capacitor plate area is greater, the longer the region of the dielectric layer between the doped silicon substrate 101 and one later in the trench 111 nanostructure to be introduced, that is, the larger t is. A value in the range of Iμ is typically chosen for t. It should also be noted that the trench 111 can be partially filled with doped polysilicon after the formation of the dielectric layer 114 in order to achieve a particularly high capacitance of the storage capacitor.

In order to obtain the layer sequence 116 shown in FIG. 1F, iron material 117 is formed as a catalyst material for catalyzing the formation of carbon nanotubes on part of the dielectric layer 114.

In order to obtain the layer sequence 119 shown in FIG. IG, an angle-selective etching Process iron material 117 removed from the surface of layer sequence 116 except for the area contained in trench 111. Then, a carbon nanotube 120 is grown orthogonal to the surface of the doped silicon substrate 101 such that a first end portion 120a inside the doped silicon substrate 101 and that a second end portion 120b of the carbon nanotube 120 outside the doped silicon substrate 101 101 is arranged. The carbon nanotube 120 is grown using a CVD process by introducing acetylene or methane into the process chamber. Alternatively, carbon and nitrogen or carbon, nitrogen and boron nanotubes can also be used as carbon nanotubes 120. Doped nanotubes can also be used, or it can

Nanotubes can be doped in an additional process step. The length of the carbon nanotube 120 can be controlled by dividing the process parameters. In particular, it is possible to form a plurality of carbon nanotubes in different

Surface areas of a layer sequence to make the growth length of the nanotubes uniform. It should also be noted that the growth of the carbon nanotube 120 takes place selectively on the iron material 117, the trench 111 serving as a template or as a guide for the growth. This ensures that vertical carbon nanotubes 120 are formed. The aspect ratio can be adjusted by dividing the length of the carbon nanotube 120 in the vertical direction according to FIG. Alternatively, the length of the

Carbon nanotube 120 are controlled by applying a silicon dioxide layer, the thickness of which corresponds to the desired thickness of the carbon nanotube area outside of the substrate 101, to the layer sequence 119 with the already formed carbon nanotube and using a CMP process ("chemical mechanical polishing") ) is planarized, and by using a subsequent selective etching process, the silicon dioxide layer is removed. Furthermore, this time of the method is suitable for optionally doping the carbon nanotube in order to adjust the transistor and / or the capacitor properties.

In order to obtain the layer sequence 122 shown in FIG. 1H, an intermediate region 120c of the carbon nanotube 120 and a second end section 120b of the carbon nanotube 120 as well as the partial region of the dielectric layer 114 arranged on the surface of the layer sequence 119 are covered with a first silicon dioxide Layer 123 covers which first silicon dioxide layer 123 later forms the gate insulating layer of the vertical switching transistor to be formed. This deposition is carried out using a CVD process or an ALD process. The thickness s of the conformally deposited first silicon dioxide layer 123 is approximately 5 nm. Furthermore, an electrically conductive first titanium nitride layer 124 is deposited conformally on the surface of the layer sequence using an ALD method in a thickness u between approximately 10 nm and 30 nm. Alternatively, instead of titanium nitride, tungsten can also be used as the material for this layer, which can be deposited using an ALD or a CVD method. PVD metals can also be used, provided they can be deposited in a conformal manner. The first titanium nitride layer 124 is processed in further method steps in such a way that a word line is formed for a DRAM memory cell.

In order to obtain the layer sequence 126 shown in FIG. II, the first titanium nitride layer 124 is partially removed from the surface of the layer sequence 122, the portion of the first titanium nitride layer 124 which is removed in this method step being determined in that an etchant for selectively etching titanium nitride material at such an angle on the layer sequence 122 is directed that only a desired partial area of the first titanium nitride layer 124 is covered by the etchant, whereas another partial area of the first titanium nitride layer 124 is protected from etching, since the carbon nanotube 120 (or more, in FIG. II Vertical carbon nanotubes (not shown) on adjacent surface areas of the substrate 101) shade surface areas of the substrate 101 from the etchant. The area of the surface of the layer sequence which is captured by the etchant is shown in FIG

Reference number 127 marked. Furthermore, the direction in which the etchant for selective ion etching of the first titanium nitride layer 124 is directed onto the layer sequence 122 is shown in FIG. II as arrow 128. As a result of the method step described, the later word line or the later gate electrode of the vertical switching transistor is formed by the part of the carbon nanotube 120 covered with the silicon dioxide layer 123 being covered with the first titanium nitride layer 124 and under one Predeterminable angle with respect to the carbon nanotube 120, an etchant for etching the first titanium nitride layer 124 is directed onto the carbon nanotube 120 covered with the first titanium nitride layer 124, in such a way that only such partial regions of the first titanium nitride layer 124 are protected against removal as a result of etching , Which

Portions of the carbon nanotube 120 are shaded with respect to the etchant. It should be noted that this method step can be carried out using the structuring arrangement according to the invention, which is described below with reference to FIGS. 2B, 2C.

The carbon nanotube 120, which is covered with the silicon dioxide layer 123 and the first titanium nitride layer 124, clearly serves as a shadow mask for forming the word lines. Due to the spatial expansion of the conformally deposited first titanium nitride layer 124 on the

Carbon nanotube 120 ensures that the word line has a larger spatial extension than that Carbon nanotube 120 and the dielectric silicon dioxide layer 123, wherein all gate electrodes of memory cells on a substrate are coupled to one another by means of the word line. Furthermore, a ring-like structure can be formed as a gate electrode around the carbon nanotube 120.

In order to obtain the layer sequence 130 shown in FIG. 1J, a second silicon dioxide layer 131 is applied to the layer sequence 126 using a sputtering method. Alternatively, the second silicon dioxide layer 131 can be applied using the spin-on-glass method.

In order to obtain the layer sequence 133 shown in FIG. 1K, the second silicon dioxide layer 131 is partially removed or etched back using a conformal etching method. As a result, the thickness of the second silicon dioxide layer 131 in FIG. 1K is less than in FIG. 1J, and that after the method step, the side walls of the vertical arrangement composed of carbon nanotube 120, first silicon dioxide layer 123 and the first Titanium nitride layer 124 are free from covering with the second silicon dioxide layer 131.

In order to obtain the layer sequence 135 shown in FIG. 1, the first titanium nitride layer 124 and the first silicon dioxide layer 123 are etched back using a selective etching method such that the second end section 120b of the carbon nanotube 120 is exposed. In this method step, a partial area of the second silicon dioxide layer 131 is also removed.

In order to obtain the layer sequence 137 shown in FIG. IM, a third is used using a sputtering method

Silicon dioxide layer 138 as an intermetallic dielectric, directed and partially deposited on the layer sequence 135 selectively etched back to clean carbon nanotube 120. Furthermore, a second titanium nitride layer 139 is deposited conformally on the surface of the layer sequence obtained in this way, a bit line being formed from the second titanium nitride layer 139 in a later method step.

The further method steps for forming the memory cell according to the invention are described with reference to FIG. IN, FIG. 10. The ones shown there

Cross-sectional views of the layer sequence are taken along the section line A-A shown in FIG. IM.

In order to obtain the layer sequence 141 shown in FIG. IN, a directional, angle-selective etching method using an etching agent for etching the second titanium nitride layer 139 is used, similarly to the method step in the transition from FIG. 1H to FIG. II , For this purpose, etching agent is directed laterally at a predeterminable angle to the carbon nanotube 120 onto the layer sequence 137 in the direction 143 shown in FIG. IN, the area 142 covered by the etching agent being such that only a subarea of the second titanium nitride layer 139 is removed from the surface of the layer sequence 137. This creates coherent bit lines. This process step is clearly similar to the process step carried out in the transition from FIG. 1H to FIG. II, in which the word lines have been formed, but the structuring arrangement for executing this process step is oriented differently with respect to the layer sequence.

In order to obtain the memory cell 145 shown in FIG. 10, a fourth silicon dioxide layer 146 is applied as a cover layer to the layer sequence 141, for example using a CVD method. The functionality of the memory cell 145 shown in FIG. 10 is described below in accordance with a preferred exemplary embodiment of the invention.

The memory cell 145 has a vertical switching transistor and a storage capacitor, the vertical switching transistor having the semiconducting carbon nanotube 120, which has been grown on part of the storage capacitor. The vertical switching transistor and the

Storage capacitors are partly arranged in and partly on the doped silicon substrate 101. The first end portion 120a of the carbon nanotube 120 is arranged inside the doped silicon substrate 101, and the second end portion 120b of the carbon nanotube 120 is arranged outside the substrate 101. The vertical switching transistor is designed as a ^" field-effect transistor, the first source / drain region of the vertical transistor designed as a field-effect transistor being the first end section 120a of the carbon nanotube 120, the second end section 120b of the carbon nanotube being the second The source / drain region of the vertical switching transistor forms, and the intermediate region 120c of the carbon nanotube 120 arranged between the two end sections 120a, 120b forms the channel region of the vertical switching transistor 120c of the carbon nanotube 120 is surrounded by an electrically insulating ring structure formed by the first silicon dioxide layer 123, which forms the gate-insulating layer of the vertical switching transistor, and that region of the first silicon dioxide layer 123 which has the electrically insulating ring structure is surrounded by the first titanium nitride layer 124, which de s vertical switching transistor and the word line forms. The second end section 120b of the carbon nanotube 120 is partially surrounded by the electrically conductive second titanium nitride layer 139, which forms the bit line of the memory cell. The memory- The capacitor of the memory cell 145 is formed by two electrically conductive capacitor elements (which in the integrated stacked capacitor represent the analogue to the capacitor plates of a conventional capacitor) and by a dielectric layer as

Capacitor dielectric between the two electrically conductive capacitor elements. The first end section 120a of the carbon nanotube 120 forms the first electrically conductive capacitor element, the doped silicon substrate 101 forms the second electrically conductive capacitor element and that portion of the dielectric layer 114 by means of which the first end section 120a of the carbon nanotube 120 is separated from the doped silicon substrate 101, forms the capacitor dielectric.

By applying a suitable voltage to the first titanium nitride layer 124 functioning as a word line, the conductivity of the carbon nanotube 120, in particular in the intermediate region 120c, is influenced characteristically as a result of the field effect, so that by applying a suitable voltage to the first titanium nitride layer 124 the memory cell 145 shown in FIG. 10 of a memory cell arrangement with a plurality of memory cells can be selected. As a result of the ring-like structure of the gate electrode and gate insulating layer, particularly good controllability is made possible according to the invention. In order to program the memory cell 145, when the vertical switching transistor is in a conductive state, electrical charge is programmed into the stack capacitor via the second titanium nitride layer 139, which is designed as a bit line.

The presence of electrical charge in the storage capacitor can be interpreted as a state with a logic value "1", whereas a state in which no electrical charge is stored in the storage capacitor is interpreted as a logical value "0". If the information stored in the memory cell 145 is to be read out, the vertical switching transistor is brought into a conductive state by applying a suitable voltage to the word line 124, so that charge carriers stored in the memory capacitor may be placed on the bit line 139 flow where a corresponding electrical signal can be detected. This signal is characteristic of the information stored in the storage capacitor.

An alternative embodiment of the method according to the invention for producing a memory cell is described below with reference to FIG. 2A.

Starting from the layer sequence 106 from FIG. 1B (or alternatively from the layer sequence 108 from FIG. IC), as shown in FIG. 2A, the storage capacitor can be formed by inserting the layer sequence 106 into the doped silicon substrate 101 a trench is first etched by lining this trench with a silicon dioxide dielectric 201 by means of thermal oxidation of the doped silicon substrate 101 or by depositing silicon dioxide material on the walls of the trench, and by the resulting trench being doped with doped polycrystalline silicon material 202 is filled. The layer sequence 200 shown in FIG. 2A is thereby obtained. According to this scenario, the memory capacitor of the memory cell according to the invention is formed by the doped silicon substrate 101 and the doped polysilicon material 202 as the first and second electrically conductive capacitor elements and by the silicon dioxide dielectric 201 as a capacitor dielectric. In this case, a carbon nanotube to be applied further only fulfills the functionality of the switching transistor of the memory cell. The others

Method steps for forming the memory cell take place starting from the layer sequence 200 analogous to that described in FIG. IC to FIG. 10.

A preferred exemplary embodiment of the structuring arrangement according to the invention is described below with reference to FIGS. 2B, 2C.

The structuring arrangement 210 extends essentially orthogonally to the surface of a substrate 211

10 first and second carbon nanotubes 212, 213, which are partially arranged outside the substrate 211. Furthermore, the structuring arrangement has material 214 to be structured on the part of the carbon nanotubes 212, 213 arranged outside the substrate 211. Furthermore, the

15 structuring arrangement 210 have further layers 215, 216, 217, of which the first and second

Carbon nanotubes 212, 213 can be partially surrounded. In addition, the structuring arrangement 210 has an etchant supply device 218, which is set up in this way

20 is that it can be used to etch material 214 to be structured at a predeterminable angle .alpha. To carbon nanotube 212 or 213 onto the carbon nanotubes 21, 213 covered with material 214 to be structured, such that only such

25 partial areas of the material 214 to be structured are protected against removal due to etching, which are shaded from the carbon nanotubes 212, 213 with respect to the etchant.

30. The carbon nanotubes 212, 213 clearly serve as

Mask, by means of which mask is determined which areas are to be removed from the material 214 to be structured. On the basis of the geometric relationships shown in FIG. 2B, the area 219 covered by the etching agent is predetermined

35 of the etching medium direction 220 and determined by arranging the carbon nanotubes 212, 213. By adjusting the distance between adjacent carbon nanotubes 212, 213 from one another, by dividing the height of that area of the carbon nanotubes 212, 213 that protrudes from the substrate 211, and by selecting the arrangement and angle of incidence of the etchant supply device 218, which areas of the material 214 to be structured 214 are to be removed can be selected. According to the scenario shown in FIG. 2B, only regions of material 214 to be structured on the upper and right edge regions of the carbon nanotubes 212, 213 according to FIG. 2B are removed. It should also be noted that, due to the selectivity of the etching process (ie the etching agent), in particular the third further layer, which partially covers the carbon nanotubes 212, 213, is protected against removal due to etching.

A cross-sectional view 230 of the structuring arrangement 210 shown in FIG. 2B, taken along the section line B-B shown in FIG. 2B, is described below with reference to FIG. 2C. It should be noted that only two carbon nanotubes 212, 213 are shown in FIG. 2B, whereas the carbon nanotubes 231, 232 additionally shown in FIG. 2C are covered in FIG. 2B. The third carbon nanotube 231 and the fourth carbon nanotube 232 are also surrounded by a further layer 233. As can be seen from FIG. 2C, the material 214 to be structured is structured on the surface of the substrate 211 as a result of the directional, angle-dependent etching into parallel paths, which can be used, for example, as a bit or word line.

A method for producing a memory cell according to a second preferred exemplary embodiment of the invention is described below with reference to FIGS. 3A to 3F. In order to obtain the layer sequence 300 shown in FIG. 3A, carbon nanotubes 303 are grown in an aluminum oxide substrate 301 with pores 302 incorporated therein according to the method described in [3], [4]. The pores 302 in the aluminum oxide substrate 301 preferably form a square arrangement.

In order to obtain the layer sequence 310 shown in FIG. 3B, a lower region of the aluminum oxide substrate 301 according to FIG. 3B is removed using a suitable etching method, so that a first end section 303a of the carbon nanotubes 303 is exposed.

In order to obtain the layer sequence 320 shown in FIG. 3C, a dielectric layer 321 is deposited using the CVD or the ALD method on the lower main surface of the aluminum oxide substrate 301 as shown in FIG. 3C and on that portion of the carbon nanotubes 303 that exposed outside of the alumina substrate 301.

In order to obtain the layer sequence 330 shown in FIG. 3D, a poly-silicon layer 331 is deposited on the lower surface of the layer sequence 320 according to FIG. 3D, as a result of which one of the two electrically conductive elements of the later storage capacitor is formed. As an alternative to poly-silicon material, a metal or a metal nitride (for example titanium nitride) can also be used for the layer 331.

In order to obtain the layer sequence 340 shown in FIG. 3E, the layer sequence 340 is attached to a substrate 341, for example by means of wafer bonding.

In order to obtain the layer sequence 350 shown in FIG. 3F, the remaining region of the aluminum oxide substrate 301 is removed from the layer using a suitable etching method Surface of the layer sequence 340 removed. This results in a layer sequence 350 which is similar to the layer sequence 119 from FIG. IG. The further processing for forming a memory cell according to the invention based on FIG. 3F can be carried out using method steps as described starting from FIG. IG up to FIG. 10.

A memory cell 400 according to another exemplary embodiment of the invention is described below with reference to FIG.

The memory cell 400 has a polycrystalline silicon substrate 401 on which a first silicon dioxide layer 402 is formed. A thin first titanium nitride layer 403 is applied to the first silicon dioxide layer 402. A second silicon dioxide layer 404 is applied to the first titanium nitride layer 403. The layers 402 to 404 and a surface area of the silicon substrate 401 are subjected to a suitable etching method, so that a through hole is etched through the layers 404 to 402, which through hole extends into a surface area of the silicon substrate 401. An electrically insulating third silicon dioxide layer 405 is formed along the inner wall of the hole. A carbon nanotube 406 is grown in the hole. A second titanium nitride layer 407 is applied to the layer sequence thus obtained.

In the memory cell 400, a region of the silicon substrate 401 is the first to be electrically conductive

Capacitor element, a region of the third silicon dioxide layer 405 as a capacitor dielectric and a region of the carbon nanotube 406 as a second electrically conductive capacitor element a storage capacitor.

Furthermore, a switching field effect transistor is formed from a central region of the carbon nanotube 406 as a channel region, a lower section according to FIG. 4 of the carbon nanotube 406 as the first source / drain region, a boundary section between the carbon nanotube 406 and the second titanium nitride layer 407 as the second source / drain region and the first titanium nitride layer 403 as an annular gate - electrode. By means of an electrical peak effect, the electrical conductivity of the carbon nanotube 406 in a surrounding area is thin and that

Carbon nanotube surrounding first titanium nitride layer 403 in a ring-like manner can be controlled particularly precisely.

The following publications are cited in this document:

[1] Harris, PJF (1999) "Carbon Nanotubes and Related

Structures - New Materials for the Twenty-First Century. ", Cambridge University Press, Cambridge. S.

1 to 15, 111 to 155

[2] Roth, S (2001) "Light-emitting diodes made of nanorods",

Physical Sheets 57 (3): 17-18

[3] Suh, JS, Lee, JS (1999) "Highly ordered two-dimensional carbon nanotube arrays" Applied Physical Letters

75 (14).-2047-2049

[4] Lee, JS, Gu, GH, Kim, H, Jeong, KS, Bae, J, Suh, JS

(2001) "Growth of Carbon Nanotubes on Anodic Aluminum Oxide Templates: Fabrication of a Tube-in-Tube and Linearly Joint Tube" Chem. Mater. 13 (7): 2387-2388

[5] DE 100 36 897 Cl

[6] DE 198 05 076 AI

[7] DE 100 36 897 Cl

100 layer sequence

101 doped silicon substrate

102 silicon nitride hard mask

103 photoresist layer

104 structuring window 106 layer sequence

108 sequence of layers

109 Structuring window constriction areas

110 sequence of layers

111 trench

113 sequence of layers

114 dielectric layer

116 layer sequence

117 iron material 119 layer sequence

120 carbon nanotube 120a first section 120b second end section 120c intermediate section

122 layer sequence

123 first silicon dioxide layer

124 first titanium nitride layer

126 sequence of layers

127 area covered by etchant

128 direction of etchant

130 layer sequence

131 second silicon dioxide layer 133 layer sequence

135 layer sequence 137 layer sequence

138 third silicon dioxide layer 139 second titanium nitride layer

141 layer sequence

142 area covered by etchant 143 direction of etchant

145 memory cell

146 fourth silicon dioxide layer 200 layer sequence

201 silicon dioxide dielectric

202 doped poly-silicon material

210 structuring arrangement

211 substrate

212 first carbon nanotube

213 second carbon nanotube

214 material to be structured

215 first additional layer

216 second additional layer

217 third additional shift

218 etchant feeder

219 area covered by caustic

220 direction of etchant

230 cross-sectional view

231 third carbon nanotube

232 fourth carbon nanotube

233 fourth additional shift 300 shift sequence

301 alumina substrate

302 pores

303 carbon nanotubes 303a first end section 310 layer sequence

320 layer sequence

321 dielectric layer 330 layer sequence

331 poly silicon layer

340 layer sequence

341 substrate

350 layer sequence 400 memory cell 401 silicon substrate

402 first silicon dioxide layer

403 first titanium nitride layer

404 second silicon dioxide layer

405 third silicon dioxide layer

406 carbon nanotube

407 second titanium nitride layer

Claims

claims:

1. memory cell

• with a vertical switching transistor and a storage capacitor;

• The vertical switching transistor has a semiconducting nanostructure that has been grown on at least part of the storage capacitor.

2. Memory cell according to claim 1, wherein the vertical switching transistor and the storage capacitor are at least partially formed in and / or at least partially on a substrate.

3. The memory cell of claim 2, wherein the nanostructure extends substantially orthogonally to the surface of the substrate.

4. The memory cell as claimed in claim 3, in which a first end section of the nanostructure is arranged inside the substrate and in which a second end section of the nanostructure is arranged outside the substrate.

5. Memory cell according to one of claims 1 to 4, wherein the vertical switching transistor

Field effect transistor is.

6. The memory cell according to claim 5, in which • the first end section of the nanostructure is a first

Source / drain region

The second end section of the nanostructure has a second source / drain region

An intermediate region of the nanostructure arranged between the two end sections forms a channel region of the vertical switching transistor.

7. Memory cell according to one of claims 4 to 6, in which a dielectric layer is formed between the first end section of the nanostructure and the substrate, wherein • the first end section of the nanostructure is a first electrically conductive capacitor element

• the dielectric layer is a capacitor dielectric

• The substrate form a second electrically conductive capacitor element of the storage capacitor.

8. The memory cell according to claim 7, in which a ferroelectric layer is formed instead of the dielectric layer.

9. The memory cell as claimed in claim 7 or 8, in which catalyst material for catalyzing the formation of the nanostructure is arranged between at least part of the dielectric layer and the nanostructure,

10. Memory cell according to one of claims 6 to 9, in which

• At least part of the intermediate region of the nanostructure is surrounded by an electrically insulating ring structure which surrounds the gate

Insulation layer of the vertical switching transistor forms;

• At least part of the electrically insulating ring structure is surrounded by a first electrically conductive area, which is the gate electrode of the

Vertical switching transistor and the word line forms.

11. Memory cell according to one of claims 4 to 10, wherein the second end section of the nanostructure is surrounded by a second electrically conductive region which forms the bit line.

12. Memory cell according to one of claims 1 to 11, wherein the semiconducting nanostructure

• a semiconducting nanotube

• has a bundle of semiconducting nanotubes or • has a semiconducting nanorod.

13. The memory cell according to claim 12, wherein the nanorod • silicon

• Germanium

• indium phosphide and / or

• Has gallium arsenide.

14. The memory cell of claim 13, wherein the semiconducting nanotube

• a semiconducting carbon nanotube

• a semiconducting carbon-boron nanotube or • a semiconducting carbon-nitrogen nanotube

• is.

15. The memory cell according to claim 12 or 14, in which the nanostructure is a carbon nanotube and in which the catalyst material

• iron

• cobalt and / or

• Has nickel.

16. Memory cell according to one of claims 1 to 15, which is formed exclusively from dielectric material, metallic material and the material of the nanostructure.

17. Memory cell according to one of claims 2 to 16, wherein the substrate consists of polycrystalline or amorphous material or of crystalline material.

18th Memory cell arrangement with a plurality of memory cells according to one of Claims 1 to 17.

19. A method of manufacturing a memory cell in which

• a vertical switching transistor and a storage capacitor are formed; Wherein a semiconducting nanostructure of the vertical switching transistor is formed, which is grown on at least part of the storage capacitor.

20. The method of claim 19, wherein the vertical switching transistor and the storage capacitor are at least partially formed in and / or at least partially on a substrate.

21. The method according to claim 20, wherein the nanostructure is formed substantially orthogonally to the surface of the substrate.

22. The method of claim 20, wherein a first end portion of the nanostructure is formed within the substrate and a second end portion of the nanostructure is formed outside of the substrate.

23. The method according to claim 22, in which • the first end section of the nanostructure is the first source / drain region

• The second end section of the nanostructure as the second source / drain region

An intermediate region of the nanostructure arranged between the two end sections is designed as a channel region of the vertical switching transistor designed as a field effect transistor.

24. The method of claim 22 or 23, wherein a dielectric layer is formed between the first end portion of the nanostructure and the substrate, wherein

The first end section of the nanostructure as a first electrically conductive capacitor element

• the dielectric layer as a capacitor dielectric

• The substrate is designed as a second electrically conductive capacitor element of the storage capacitor.

25. The method of claim 24, wherein between at least a portion of the dielectric layer and the nanostructure catalyst material

Catalyzing the formation of the nanostructure is formed.

26. The method according to any one of claims 23 to 25, in which

• At least part of the intermediate region of the nanostructure is surrounded by an electrically insulating ring structure which forms the gate insulation layer of the vertical switching transistor;

• At least part of the electrically insulating ring structure is surrounded by a first electrically conductive area, which forms the gate electrode of the vertical switching transistor and the word line.

27. The method according to any one of claims 23 to 26, wherein the second end section of the nanostructure is surrounded by a second electrically conductive region which forms the bit line.

28. The method of claim 26 or 27, wherein the word line and / or the bit line and / or the gate electrode can be formed by

• an exposed or covered part of the nanostructure is covered with electrically conductive material; and • at a predeterminable angle with respect to the

Nanostructure an etchant for etching the electrically conductive material is directed onto the nanostructure covered with the electrically conductive material, such that only those partial areas of the electrically conductive material are protected against removal due to etching, which partial areas are shadowed by the nanostructure with respect to the etchant.

29. Structuring arrangement

With a nanostructure which extends essentially orthogonally to the surface of a substrate and which is at least partially arranged outside the substrate; With material to be structured on the part of the nanostructure arranged outside the substrate;

With an etchant supply device, which is set up in such a way that it can be used to etch material to be structured at a predeterminable angle to the nanostructure onto the nanostructure covered with material in such a way that only such partial areas of the material to be structured can be directed are protected against removal due to etching, which are shadowed by the nanostructure with respect to the etchant.