EP1186035A1 - Composant electronique a structures de contact souples et procede de fabrication d'un tel composant - Google Patents

Composant electronique a structures de contact souples et procede de fabrication d'un tel composant

Info

Publication number
EP1186035A1
EP1186035A1 EP00934894A EP00934894A EP1186035A1 EP 1186035 A1 EP1186035 A1 EP 1186035A1 EP 00934894 A EP00934894 A EP 00934894A EP 00934894 A EP00934894 A EP 00934894A EP 1186035 A1 EP1186035 A1 EP 1186035A1
Authority
EP
European Patent Office
Prior art keywords
electronic component
flexible
elevation
insulating layer
flexible elevation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00934894A
Other languages
German (de)
English (en)
Inventor
Harry Hedler
Alfred Haimerl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1186035A1 publication Critical patent/EP1186035A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to an electronic component with an electronic circuit and electrical contacts at least on a first surface of the electronic component, which are used for contacting the electronic circuit.
  • the object of the present invention is therefore to provide an electronic component which is less sensitive to mechanical stresses in the area of the electrical contacts. Furthermore, a method for producing such a component is to be specified. This object is achieved by the features of claims 1 and 2. The manufacturing method according to the invention is specified with the features of claim 7.
  • At least one flexible elevation made of an insulating material is provided on the first surface of the electronic component on which the electrical contacts of the component are arranged, at least one electrical contact being arranged on the at least one flexible elevation.
  • This arrangement according to the invention is of particular importance in the case of electronic components whose size largely corresponds to the size of the electronic circuit or the circuit chip of the component, that is to say in the case of so-called chip-size components. Since here, in addition to the electronic circuit or the circuit chip, there are practically no further housing elements which can absorb voltages on the electronic component, there is a particularly high risk of damage or destruction of the electrical contacts in such components. In such a case in particular, the occurrence of excessive mechanical stresses can be avoided by a flexible elevation, as proposed according to the invention, and the operational reliability of the component can thus be guaranteed.
  • the electrical contacts of the electronic component are thus arranged on a flexible elevation, which balancing mechanical stresses.
  • a conduction path is arranged on the surface of the flexible elevation between the electrical contact and the electronic circuit.
  • the electronic circuit can, for example, directly adjoin the flexible elevation, but it can also be provided that additional conductor tracks are arranged between the flexible elevation and the electronic circuit so that the flexible elevation can be arranged at a distance from the electronic circuit.
  • a line path can also be arranged inside the flexible elevation between the electrical contact and the electronic circuit. Starting from the electrical contact on the flexible elevation, the conductive connection is thus guided through the flexible elevation and towards the electronic circuit.
  • the entire flexible elevation can also be made from a flexible and electrically conductive material, so that the conductive connection is not made from another material through a separate conduction path, but rather through the flexible material itself.
  • this requires very specific materials that restrict the selection of flexible materials and their composition.
  • such materials are generally more high-resistance than a pure line material that forms a line path.
  • conductor lines can be placed on an insulating layer that at least partially covers the Covered first surface of the electronic component, be arranged, wherein the insulating layer is adjacent to the flexible elevation.
  • the electronic component can basically be designed in any suitable, usable form.
  • the component can be a semiconductor component or a polymer component.
  • the electrical contact on the flexible elevation can also be of any design and adapted to the particular use of the electronic component.
  • the electrical contact can be formed by a conductive layer, a conductive pin or a conductive ball.
  • the flexible survey is applied to the electronic component in one possible method by means of a printing process which can be carried out simply and inexpensively.
  • the requirements for the strengthening tolerances for such surveys are met by the printing processes that are technically possible today.
  • the flexible survey was carried out by injection molding or injection stamping.
  • a thermoplastic or a duroplastic is then preferably used as the material.
  • plastics could also be used on ABS (acrylonitride butadene styrene), PC (polycarbonate), PA (polyamide) or PPO (polyphenylene oxide).
  • the insulating layer can also be applied by a printing process.
  • the conductive material for producing the conductor lines or the line paths and the electrical contacts can be applied to the flexible elevation or to the insulating by conventional methods, such as sputter metallization or chemical metallization Layer can be applied. Special processes for this are described in WO 98/55 669 and WO 99/05 895, with nucleation first taking place in an insulating layer and then a metallization of these areas.
  • this surface is roughened by laser treatment of the surface of the flexible elevation and, if appropriate, also of the flexible layer, or by another suitable method offers better liability.
  • metal nuclei or other suitable nuclei which can consist of any suitable material, for example palladium, are applied to the rough surface before the metallization and after the surface roughening.
  • Figure 1 Semiconductor chip after printing an insulating layer.
  • Figure 2 Semiconductor chip according to Figure 1 after printing a flexible survey.
  • FIG. 3 semiconductor chip according to FIG. 2 after application of a first metallization.
  • FIG. 4 semiconductor chip according to FIG. 3 after application of a second metallization.
  • FIG. 5 Semiconductor chip according to Figure 4 after applying a solder ball on the contact point.
  • FIG. 6 overall view of a component according to FIG. 5.
  • Figure 7 Alternative embodiment of the conductive connection to Figures 3 and 4.
  • Figure 8 Semiconductor chip after the pointed stamping of a semi-elastic, flexible elevation and an insulating layer.
  • FIG. 9 semiconductor chip according to FIG. 8 after application of a metallization.
  • FIG. 10 semiconductor chip after the spitting of an elastic, flexible elevation.
  • FIG. 11 semiconductor chip according to FIG. 10 after application of a semi-elastic insulating layer.
  • FIG. 12 semiconductor chip according to FIG. 11 after application of a metallization.
  • FIGS. 1 to 5 The manufacture of an electronic component which has a flexible elevation according to the invention is explained by way of example in FIGS. 1 to 5.
  • an insulating layer 7 is first applied to a semiconductor chip 6, which is shown in detail in FIG. 1, which at least partially covers a first surface 2 of the semiconductor chip 6.
  • the application and structuring of this insulating layer 7 can be done by conventional means
  • a flexible elevation 3 is then placed on the semiconductor chip 6 in the region of its first surface 2 applied, the flexible elevation 3 may be arranged on or next to the insulating layer.
  • the surface of the flexible elevation 3 and the insulating layer 7 can now be roughened with the aid of a laser in those areas in which line paths 8 and conductor lines 4 are to be formed in a later step. This is indicated by the vertical arrows m Figure 2.
  • the rough surface ensures in particular better adhesion of the conductive material of the conductor paths 8 and conductor runs 4 to the respective surfaces.
  • a metallization is then applied to the surface of the flexible elevation 3 and to the surface of the insulating layer 7.
  • This metallization can, for example, as shown in FIGS. 3 and 4, take place in two steps, a first basic metallization 4a, 8a being generated first, or germs 4a, 8a being deposited on the surface, which in each case are used to form conductors on the surface insulating layer and a conduction path on the flexible elevation.
  • the seeds can be made of any suitable material such as palladium.
  • a final metallization 4b, 8b then takes place for the final production of the conductor runs and conductor paths.
  • This metallization already forms an electrical contact 1 on the flexible elevation, via which the electronic component can be contacted.
  • FIG. 5 shows, however, it can be provided as an alternative that an additional solder ball 5 is attached to the flexible elevation 3, which then forms the electrical contact 1.
  • FIG. 6 schematically shows an overall cross section of the electronic component, in which case the flexible elevations 3 at the edge of the electronic component are shown and the conductor tracks 4 lead to the corresponding connections of an electronic circuit (not shown) in the semiconductor chip 6.
  • the surveys 3 can, however can also be arranged in a suitable manner over the entire first surface 2.
  • FIG. 7 shows an alternative to the line paths of FIGS. 3 and 4, a line path 9 leading through the flexible elevation 3 here.
  • Such an arrangement can be produced, for example, by first applying an insulating layer 7 to the semiconductor chip 6, as in FIG. 1. This is followed by metallization for the production of conductor tracks 4 on the insulating layer 7. Only then is the flexible elevation 3 applied, for example by a printing process. Finally, a line path 9 is formed in the interior of the flexible elevation 3, for example by laser structuring starting from the surface of the flexible elevation 3 and a subsequent metallization.
  • FIGS. 8 and 9 the production of an electronic component in which the flexible elevation according to the invention is produced by means of injection stamping is now explained by way of example.
  • FIG. 8 shows a semiconductor chip 6, which is shown in detail.
  • An insulating layer 7 and a flexible elevation 3 are applied to this.
  • Spray stamping now advantageously enables the flexible layer 7 and the flexible elevation 3 m to be applied in a single operation.
  • a correspondingly shaped tool is provided, in which a plastic, for example a thermoplastic or a thermoset, is introduced.
  • the insulating layer 7 and the flexible elevation 3 are preformed in the tool.
  • the tool is placed on the first surface 2 of the semiconductor chip 6 and the plastic, for example a semi-elastic material (insulating layer 7, flexible elevation 3), is connected to the semiconductor chip 6.
  • the process control can be carried out in a simplified manner. In contrast to a printing process, much finer structures can be applied to the semiconductor chip.
  • a flexible elevation made from a semi-elastic plastic material has the properties that it is flexible and compressible.
  • the flexible elevation does not act like a spring.
  • the elasticity of the flexible elevation 3 is achieved exclusively via the geometrical configuration of the elevation.
  • the flexible elevation 3 is relatively narrow in relation to its height.
  • a spring action can be achieved in the directions that are parallel to the first surface of the semiconductor chip 6.
  • a spring action orthogonal to the first surface of the semiconductor chip 6 is not possible.
  • the entire first surface of the semiconductor chip 6 can be covered with the plastic, i.e. to be provided with insulating layers 7 and flexible elevations 3.
  • the areas that will later be provided with conductor tracks can be activated by a laser, i.e. to be roughened. These activated conductor lines are then germinated, as a result of which the metallizations of the conductor lines applied therein only adhere at these points.
  • the entire insulating layer 7 to be e.g. by means of a laser, whereby the insulating layer 7 is only applied at the locations on the first surface of the semiconductor chip 6 at which the conductor lines are later provided. The activation and germination also takes place with this procedure.
  • Spray stamping offers the advantage that the flexible elevation 3 and the insulating layer 7 can be applied to the first surface of the semiconductor chip 6 in one operation. However, this is not absolutely necessary. It is it is also conceivable to apply the isolated layers 7 and the flexible elevations 3 m to the semiconductor chip 6 in two separate stamping processes.
  • FIG. 9 shows the semiconductor chip according to the invention after the metallization 8 has been applied.
  • the metallization of the conductor lines only takes place at the points at which the plastic has been activated and germinated.
  • the metallization 8 is applied in cross section to the entire surface of the flexible elevation 3. This procedure is particularly advantageous if a test of the semiconductor chip is to be carried out before a solder connection is made between the semiconductor chip and a printed circuit board.
  • a temporary electrical connection between the electrical contact 1 and a recessed rewiring level, the electrical contact 1 and a recessed rewiring level of the printed circuit board can be established, the electrical connection between the electrical contact 1 and the recess being via the lateral conductor lines of the flexible survey 3 is produced.
  • the electrical contacts 1 are therefore introduced into the recesses of the rewiring level.
  • the semiconductor chip and the printed circuit board with the rewiring plane are moved parallel to the first surface 2 of the semiconductor chip 6, whereby the spring action of the flexible elevations 3 is used to establish a contact between each individual electrical contact 1 and the side borrowed with conductors provided recess of the rewiring level.
  • the flexible elevation 3 consists of an elastic and a semi-elastic element.
  • the elastic bump 3 can be applied either in a Sp ⁇ tzprage or in an injection molding process.
  • the flexible elevation 3 is made of an elastic material, e.g. Silicon or polyurethane, applied to the first surface 2 of the semiconductor chip 6.
  • the material properties of elastic plastics are generally such that they cannot be metallized. For this reason, it is necessary that an insulating and semi-elastic layer 7 is applied to the elastic element.
  • the insulating, semi-elastic layer 7 is applied both to parts of the first surface of the semiconductor chip 6 and to the surface of the flexible elevation 3.
  • one side surface of the flexible elevation 3 is left out of the insulating, semi-elastic layer 7. This procedure is advantageous in order to support the spring action of the elastic element 3 of the flexible elevation 3. If this side surface was also covered with the insulating layer 7, the layer 7 could possibly tear under unfavorable circumstances.
  • the material properties of the insulating, semi-elastic layer 7 are now such that it can be activated and germinated by a laser. This means that dd a metallization are applied to those areas of the insulating and elastic layer 7 that were previously activated.
  • the metallization of the conductor tracks is preferably carried out without current, ie in a chemical manner.
  • An embodiment of the semiconductor component according to the procedure just described requires a two-part stamping or injection molding process.
  • the metallizations 8 of the flexible elevations in FIGS. 9 and 12 already form an electrical contact 1, via which the electronic component can be contacted.
  • a solder ball can also be attached to the flexible elevation, which then forms the electrical contact 1. This is not shown in the figures.
  • the method according to the invention for producing a semiconductor component with flexible contacts thus essentially comprises three successive individual process steps.
  • a plastic in particular a polymer
  • a plastic chip which may already be structured.
  • (heavy metal) germs contained in the plastic are activated, for example by the use of UV light, the use of suitable chemical substances or the use of a-core activated material.
  • a chemical, ie currentless, metallization of the conductor tracks can then be carried out.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Composant électronique doté d'un circuit électronique ainsi que de contacts électriques (1) situés au moins sur une première surface (2) du composant électronique pour la mise en contact du circuit électronique. Au moins une éminence (3) souple constituée d'une matière isolante est formée sur la première surface (2) et au moins un contact électrique (1) est placé sur l'éminence souple (3). Un chemin conducteur (8) est disposé sur la surface ou à l'intérieur de l'éminence souple (3) entre le contact électrique (1) et le circuit électronique.
EP00934894A 1999-06-17 2000-04-11 Composant electronique a structures de contact souples et procede de fabrication d'un tel composant Withdrawn EP1186035A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19927750 1999-06-17
DE19927750 1999-06-17
PCT/DE2000/001123 WO2000079589A1 (fr) 1999-06-17 2000-04-11 Composant electronique a structures de contact souples et procede de fabrication d'un tel composant

Publications (1)

Publication Number Publication Date
EP1186035A1 true EP1186035A1 (fr) 2002-03-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP00934894A Withdrawn EP1186035A1 (fr) 1999-06-17 2000-04-11 Composant electronique a structures de contact souples et procede de fabrication d'un tel composant

Country Status (5)

Country Link
US (2) US6956287B2 (fr)
EP (1) EP1186035A1 (fr)
JP (2) JP2003502866A (fr)
KR (1) KR20020011440A (fr)
WO (1) WO2000079589A1 (fr)

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US6956287B2 (en) 2005-10-18
US7820482B2 (en) 2010-10-26
WO2000079589A1 (fr) 2000-12-28
JP4226589B2 (ja) 2009-02-18
JP2006108705A (ja) 2006-04-20
US20050208703A1 (en) 2005-09-22
US20020089058A1 (en) 2002-07-11
JP2003502866A (ja) 2003-01-21
KR20020011440A (ko) 2002-02-08

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