WO2003100854A2 - Module a composant electronique et procede de fabrication dudit module - Google Patents

Module a composant electronique et procede de fabrication dudit module Download PDF

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Publication number
WO2003100854A2
WO2003100854A2 PCT/DE2003/001612 DE0301612W WO03100854A2 WO 2003100854 A2 WO2003100854 A2 WO 2003100854A2 DE 0301612 W DE0301612 W DE 0301612W WO 03100854 A2 WO03100854 A2 WO 03100854A2
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WO
WIPO (PCT)
Prior art keywords
substrate
holes
bumps
substrate body
contacts
Prior art date
Application number
PCT/DE2003/001612
Other languages
German (de)
English (en)
Other versions
WO2003100854A3 (fr
Inventor
Marcel Heerman
Jozef Van Puymbroeck
Eric Beyne
Bart Vandevelde
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to AU2003232635A priority Critical patent/AU2003232635A1/en
Publication of WO2003100854A2 publication Critical patent/WO2003100854A2/fr
Publication of WO2003100854A3 publication Critical patent/WO2003100854A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
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    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
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    • H05K2201/09036—Recesses or grooves in insulating substrate
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
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    • H05K2201/091—Locally and permanently deformed areas including dielectric material
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    • H05K2201/09118—Moulded substrate
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material

Definitions

  • the invention relates to an electronic component module with a connection substrate and at least one electronic component and a method for its production.
  • EP 0782765 B1 describes a connection substrate with a semiconductor chip, a so-called PSGA (polymer stud grid array), the injection-molded substrate having molded polymer bumps with a solderable end surface.
  • PSGA polymer stud grid array
  • the polymer bumps not only have the advantage that they can be formed with the base body in one operation, but they can also absorb and compensate for stresses, for example due to thermal expansion, due to their elasticity.
  • the latter are adapted in their distribution and arrangement to the conventional grid of other connection elements, in particular the solder balls in the so-called BGA technology.
  • the grid spacing cannot be further reduced due to the properties and processing form of the solder balls.
  • the aim of the present invention is therefore to provide a connection substrate for at least one electronic component, in particular a semiconductor component, and to provide a method for its production which enables the components to be connected using flip-chip technology with extremely small grid spacings and at the same time a particularly low overall height of the module formed from the component and the connection substrate enables.
  • such a module has the following features:
  • a flat substrate body (1; 21, 22, 23; 31; 41) has on its flat top (la) a contact area with internal contacts (4) for the component (7) and on its underside (lb) external contacts (10);
  • recessed inner contact bumps (3) are formed at a distance from the connections of the component by partial removal (2) or deformation of the substrate material; an inner contact (4) is formed on the inner contact bumps (3) by metallization and provided with a solder layer; on the internal contacts, the component (7) is contacted using flip-chip technology and
  • conductor tracks (6, 12, 13, 14, 33, 34, 43, 44) extend through passage holes (5; 42) to the outer contacts (10) on the underside of the substrate body (1; 21, 22, 23; 31; 41).
  • the contacting according to the invention enables with recessed polymer bumps, flip-chip contacting down to about 100 ⁇ m.
  • the reason for this is that the solder balls in the BGA technique are pressed together for contacting during melting and thereby increase their diameter compared to their original ball diameter (about 1.3 times), while those formed on the bumps when invented Solder layer does not increase its diameter during melting, so that the contact point does not reach a larger diameter than the connection (pad) of the component itself.
  • recessed external contact bumps are also formed on the underside of the substrate body by partial removal or deformation, which are arranged in the grid of printed circuit board connections and carry the external contacts of the substrate. Depending on the arrangement and the manufacturing process of the bumps, they can be on the top or on the
  • the underside of the substrate body can be formed by annular or approximately grid-shaped notches. It is also conceivable for the surface of the With the exception of the then remaining bumps, remove the substrate body or deform it by hot stamping, so that only an edge region and possibly intermediate webs remain in the original surface plane together with the contact bumps.
  • the ring-shaped indentations can be partially metallized, in particular on their inner sides, while another part, preferably at least part of the outer regions of the indentation, are kept free from the metallization in order to form insulation paths , This can advantageously be effected on the sloping walls of the notch by laser radiation.
  • the conductor tracks on the top side and on the bottom side of the substrate body can each run in groove-shaped longitudinal trenches which are incorporated into the surface of the substrate body.
  • the through holes can be provided with a round or rectangular cross section either from the top surface to the bottom surface, or they can advantageously be produced in the area of a, for example annular, notch directly next to a hump or else in the area of a trench guiding conductor tracks. In the latter case, it is particularly advantageous to use a rectangular one To provide through hole, wherein two opposite side walls are metallized, while the intermediate side walls form insulation sections. As a result, two separate conductor tracks can be produced in a rectangular through hole, which can each be connected separately to the two conductor tracks of a groove-shaped trench.
  • Such rectangular through holes can be produced in a simple manner, for example when the substrate body is hot stamped, it being possible for oblique side walls to be machined with a laser beam in order to produce the insulation sections.
  • the substrate body can be produced from a single film, for example.
  • a base substrate on the top and / or bottom of which a backing layer is laminated, the inside contact bumps or the outside contact bumps being formed in the respective bump layer.
  • the bump layers can each be made of a different material than the base substrate. So it is possible to provide the bump layer with the inner contact bumps made of a material that is adapted in terms of its thermal expansion properties to the material of the component to be applied, preferably a semiconductor material, while a material can be used for the outer contact bumps that is adapted to a printed circuit board with regard to its thermal expansion properties.
  • a method according to the invention for producing a connection substrate has the following steps:
  • step a) external contact bumps are preferably also formed on the underside of the substrate body by deformation or partial removal, for example by circular notching, and the external contacts are produced on them in step c).
  • connection substrate according to the invention with the recessed contact bumps in a known manner by injection molding.
  • the production of the bumps according to the invention the production of the through-holes and possibly the production of grooves for guiding conductor tracks are preferably carried out using a hot stamping process or a structuring of the Substrate body with a laser beam into consideration.
  • a hot stamping process or a structuring of the Substrate body with a laser beam into consideration.
  • a structuring the metallization Structuring by means of a laser beam is preferably used to form the conductive layer.
  • an etching resist layer with a laser beam and then to remove the exposed structures in an etching process.
  • the metal layer can also be structured directly with the laser beam.
  • connection bumps with a diameter of approximately 50 to 250 ⁇ m with a grid spacing of approximately 200 ⁇ m, the height of the bumps being greater than the diameter is and can preferably be more than 1.3 times the diameter of the solder connection. This results in a good elasticity of the individual connections in a very small space.
  • FIG. 1 shows a detail from a connection substrate according to the invention for a module according to the invention
  • Figure 2 is a schematic view of the structure of internal contact bumps in connection with through holes in section
  • Figure 3 is a sectional view of a module with bumps on the top and bottom of the connection substrate
  • Figure 4 is a sectional view of a substrate with an additional bump layer on the top .
  • FIG. 5 shows a sectional view of a substrate with additional bump layers on the top and bottom
  • FIG. 6 shows a schematic detailed illustration of grooves with conductor tracks
  • FIG. 7 shows a schematic illustration of a rectangular through hole
  • FIG. 8 shows a schematic view of a conductor track structure on the upper side of a connection substrate
  • FIG. 9 shows a schematic representation of a conductor track structure on the underside of a connection substrate, Höcker
  • FIG. 11 shows an embodiment of a substrate body that is further modified compared to FIG. 10 to show the solder application and
  • Figure 12 is a schematic sectional view of a module according to the invention in a further modification.
  • connection substrate essentially consists of a substrate body 1 made of insulating material, for example LCP or another, preferably thermoplastic.
  • annular notches 2 are made, for example by means of an embossing stamp or also by removal with a laser beam.
  • This ring-shaped against notches 2 the depth of which can be, for example, 50 to 200 ⁇ m, internal contact bumps 3 are formed, the grid spacings of which correspond to the contact spacings of a semiconductor component, so that flip-chip contacting is possible directly on the upper side of the connection substrate is.
  • internal contacts in the form of a metal layer are applied to the top of the bumps 3.
  • through holes 5 are produced between the upper side la and the lower side lb of the substrate body, in which case the through holes 5 each open into a notch 2.
  • a direct conductive connection is thus produced from the inner contacts 4 via the through holes 5 to the underside 1b of the substrate body.
  • FIG. 2 shows a section of the structure of internal contact bumps 3.
  • the substrate body is coated with a metallization layer, which is partially removed again in a structuring process , so that a metal layer 6, preferably a copper layer, remains on the circumference of the inner contact bumps 3, while the outer walls of the notches 2 are freed from the metallization and thus act as insulation sections.
  • Metallization is also applied to the tip of the bumps 3 to form the internal contacts 4. In addition there is a solder layer, which is not shown here.
  • the through holes 5 are made during the metallization process. was also lined with a metal layer. The holes themselves can then be closed either with metal or with a plastic compound.
  • FIG. 3 in turn shows a section through a schematically illustrated connection substrate 1, with internal contact bumps 3 with internal contacts 4 for flip-chip contacting with connections 17 of a semiconductor chip 7 or another component being formed on the upper side.
  • external contact bumps 9 are formed in the same way by ring-shaped notches 8, which are also recessed into the surface of the substrate and each carry an external contact 10 on their tip. These external contact bumps 9 are in their size and in their grid spacing at the connections of a printed circuit board
  • connection between the inner contacts 4 and the outer contacts 10 takes place via the metallized through holes 5 and a corresponding conductor track structure
  • the metallization and structuring of the conductor layers on the top and the bottom of the substrate body can be carried out in one process step.
  • Figure 4 shows a modification to Figure 3.
  • the substrate body consists of a base substrate 21, on the underside of which the external contact bumps 9 are arranged as in the previous example.
  • a first bump layer 22 is laminated onto the top of this base substrate 21, in which the internal contact bumps 3 are shaped as in the previous examples.
  • the bump layer 22 can better match the properties, in particular the thermal expansion properties, of a can be adapted to the component, for example to the properties of a semiconductor material.
  • FIG. 5 shows a further modification, in which case the base substrate 21 carries not only a first bump layer 22 on the top but also a second bump layer 23 on the bottom.
  • the bump layers 22 and 23 can thus be selected in different ways in each case to match their contact partners, that is to say the first bump layer 22 can be matched to a component material and the second bump layer 23 can be matched to the properties of a printed circuit board material.
  • FIG. 5 also shows the possibility of applying and structuring conductor tracks on the top and the bottom of the base substrate 21 before the bump layers 22 and 23 are laminated on.
  • the through holes 5 each penetrate only the base substrate 21 and are connected on the upper side to upper-side conductor tracks 24 and on the underside to lower-side conductor tracks 25, which in turn are connected to metallizations 6 in the notches 2 and 8, respectively.
  • conductor tracks can be arranged on the underside or on the top of a substrate body 31 in groove-shaped trenches 32, which are shown only schematically in FIG. 6 as short sections.
  • Such trenches can also be shaped during the manufacture of the substrate, ie during the formation of the notches 2 by hot stamping or by laser structuring.
  • the inclined side walls 33 and 34 are preferably metallized in these trenches 32, while the bottom surfaces 35 and the upper edge regions 36 are not metallized and serve as insulating sections. In this way, two can each in a trench 32 Conductor tracks are created on opposite walls.
  • the depths of the trenches can also be approximately 50 ⁇ m in this example.
  • FIG. 7 also schematically shows the design of a rectangular through hole that narrows on one side
  • a rectangular through hole 42 is formed in a substrate body 41, which is only indicated, for example by hot stamping the substrate.
  • inclined side walls 43, 44, 45 and 46 are produced in that the side lengths cl and dl on the upper side are greater than the side lengths c2 and d2 on the underside.
  • the top and bottom sides of the substrate body can also be interchanged, so that, for example, the larger hole width can optionally be provided on the chip side of the connection substrate or on the circuit board side.
  • Feedthroughs of this type can be provided in the substrate body where it is cheapest.
  • Such a through hole in the region of a trench 32 according to FIG. 6 is advantageous, for example.
  • a conductor track 33 from FIG. 6 could be connected to a feed-through conductor track 43 and a conductor track 34 to a feed-through conductor track 44.
  • FIGS. 8 and 9 each schematically show possible configurations of the top side of a connection substrate (FIG. 8) and the bottom side (FIG. 9).
  • FIGS. 8 and 9 are not correlated with one another, they are merely basic arrangement options for the respective connection elements of the substrate.
  • FIGS. 1 to 5 show a series of internal contact bumps 3, as shown in FIGS. 1 to 5. These each have an internal contact 4. From these internal contact bumps, conductor tracks 13 partially depart, which, with a corresponding design, can also be arranged in trenches like the conductor tracks 33 and 34 (FIG. 6). Two of these conductor tracks 13 lead to a rectangular through hole 42 according to FIG. 7 with through conductor tracks 43 and 44.
  • FIG. 8 Further internal contact bumps 3 in FIG. 8 with internal contacts 4 are each connected to round through holes 5 as in FIGS. 1 to 4. These through holes can be located directly next to the bumps 3 in the area of the ring-shaped notches 2 may be arranged. Others in turn are connected to a remote through hole 5 via additional conductor tracks 14.
  • FIG. 9 shows a possible arrangement of a printed circuit board
  • FIG. 9 shows how these two conductor tracks 33, 34 are connected to the two conductive side walls 43 and 44 of a through hole.
  • FIGS. 10 to 12 schematically show further modifications of the connection substrate or the module according to the invention.
  • FIG. 10 schematically shows a substrate body 51, on the upper side of which internal connection bumps 53 are produced in comparison to FIG. 2 not by ring-shaped notches but by large-area removal or deformation of the areas 52 below the surface plane 55.
  • the inner contact bumps 53 in addition to the inner contact bumps 53, only edge regions 56 and an intermediate web 57 remain in the original height.
  • the inner contact bumps 53 are then - after a previous basic metallization - with a solder layer 54
  • solderable internal contacts formed. Before the solder layer 54 is applied, the areas around the internal contact bumps 53 are expediently covered with a solder resist 58 (FIG. 11) in order to ensure the necessary insulation distance between the individual bumps.
  • This solder resist is produced and structured, for example, by spraying with subsequent laser structuring or by applying a light-sensitive layer with subsequent exposure. Known methods, such as screen printing, are suitable for applying the solder coating 54.
  • FIG. 12 once again shows a section of a module according to the invention, the upper side being removed or deformed on a substrate body 61 to form internal contact bumps 63, so that only edge regions 66 remain.
  • a semiconductor chip 7 is contacted via its connections 17 in a narrow grid spacing.
  • the underside of the substrate body 61 is largely removed in the same way to form external contact bumps 68 between the edge regions 67.
  • the external contact bumps 68 have a larger grid spacing than the internal contact bumps 63 in adaptation to the printed circuit board connections, further intermediate webs 69 can remain on the underside of the substrate body 61, on which, for example
  • Conductor tracks or the like can be arranged. It should be pointed out that the design of the depressions between the individual bumps on the top or bottom of the substrate body can be as desired, depending on the deformation method used. In any case, the bumps are sunk below the original surface level of the substrate body, that is, below the upper surface level 65 and below the underside surface level 70 of the substrate body.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un substrat de connexion pour au moins un composant électronique. Ce substrat présente un corps de substrat plat pourvu d'une surface plane, dans laquelle des bosses de contact intérieur (3) permettant la mise en contact par puce retournée d'un composant ou éventuellement des bosses de contact extérieur (9) permettant la connexion à une carte de circuits imprimés sont formées par ablation partielle ou déformation (2 ; 8) de façon à être en retrait. La formation de ces bosses de contact selon le procédé d'estampage à chaud ou par ablation laser permet d'obtenir des bosses de très petite taille avec une densité supérieure à celle des connexions de puce actuelles.
PCT/DE2003/001612 2002-05-24 2003-05-19 Module a composant electronique et procede de fabrication dudit module WO2003100854A2 (fr)

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AU2003232635A AU2003232635A1 (en) 2002-05-24 2003-05-19 Electronic component module and method for the production thereof

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DE10223203A DE10223203B4 (de) 2002-05-24 2002-05-24 Elektronisches Bauelement-Modul und Verfahren zu dessen Herstellung
DE10223203.2 2002-05-24

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WO2003100854A3 WO2003100854A3 (fr) 2005-01-06

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WO2008088725A2 (fr) * 2007-01-11 2008-07-24 Molex Incorporated Tracé à courant élevé sur un dispositif d'interconnexion moulé plaqué
WO2013144375A1 (fr) 2012-03-30 2013-10-03 Msg Lithoglas Gmbh Dispositif à semi-conducteur et procédé de production d'une couche vitreuse
WO2014043390A1 (fr) * 2012-09-13 2014-03-20 Invensas Corporation Interposeur composite accordable

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KR100555706B1 (ko) * 2003-12-18 2006-03-03 삼성전자주식회사 미세 솔더볼 구현을 위한 ｕｂｍ 및 이를 이용한 플립칩패키지 방법
US8829663B2 (en) 2007-07-02 2014-09-09 Infineon Technologies Ag Stackable semiconductor package with encapsulant and electrically conductive feed-through

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WO2008088725A2 (fr) * 2007-01-11 2008-07-24 Molex Incorporated Tracé à courant élevé sur un dispositif d'interconnexion moulé plaqué
WO2008088725A3 (fr) * 2007-01-11 2008-09-12 Molex Inc Tracé à courant élevé sur un dispositif d'interconnexion moulé plaqué
WO2013144375A1 (fr) 2012-03-30 2013-10-03 Msg Lithoglas Gmbh Dispositif à semi-conducteur et procédé de production d'une couche vitreuse
WO2014043390A1 (fr) * 2012-09-13 2014-03-20 Invensas Corporation Interposeur composite accordable
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US9362204B2 (en) 2012-09-13 2016-06-07 Invensas Corporation Tunable composite interposer
US9780042B2 (en) 2012-09-13 2017-10-03 Invensas Corporation Tunable composite interposer

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DE10223203A1 (de) 2003-12-04
DE10223203B4 (de) 2004-04-01
WO2003100854A3 (fr) 2005-01-06
AU2003232635A1 (en) 2003-12-12

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