WO1999026287A1 - Film de silicium servant de substrat de circuits semiconducteurs faisant partie de cartes - Google Patents

Film de silicium servant de substrat de circuits semiconducteurs faisant partie de cartes Download PDF

Info

Publication number
WO1999026287A1
WO1999026287A1 PCT/DE1998/003228 DE9803228W WO9926287A1 WO 1999026287 A1 WO1999026287 A1 WO 1999026287A1 DE 9803228 W DE9803228 W DE 9803228W WO 9926287 A1 WO9926287 A1 WO 9926287A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
semiconductor
semiconductor wafer
wafer
passive side
Prior art date
Application number
PCT/DE1998/003228
Other languages
German (de)
English (en)
Inventor
Jörg BORCHERT
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1999026287A1 publication Critical patent/WO1999026287A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Silicon foil as a carrier of semiconductor circuits as part of cards
  • the invention relates to a method for producing a chip card and a semiconductor chip which is intended in particular for use in a chip card.
  • chip cards which have a chip made of silicon.
  • a disadvantage of the chip cards known in the prior art is that the complexity of the electrical circuit accommodated on the chip is limited because the maximum size of the chip is limited to approximately 25 mm 2 .
  • chip cards can be provided with semiconductor chips of particularly large area, wherein extensive circuit structures and even large-area memory arrangements can be provided on the semiconductor chip.
  • Detaching the connection between the handling chip and the semiconductor chip by passivating the adhesive layer, applying the semiconductor chip to a chip card carrier, in such a way that the passive side faces the chip card carrier, can also be carried out simultaneously or in the reverse order, to ensure flexible and accurate manufacturing.
  • Chip cards are namely in Operation frequently exposed to bending loads that are transferred to the chip embedded in the chip card.
  • tensile stresses which lead to crack formation in the chip can occur when the card is bent, particularly in the surface regions of the chip. If the chip is designed with a lower thickness, the tensile stresses in the surface areas of the chip are lower with an otherwise identical deflection of the chip card, so that the risk of cracking is reduced.
  • chips with a thickness of significantly less than 100 micrometers can be produced, which allows large chip dimensions.
  • the passive side of the semiconductor chip can be removed easily and conveniently.
  • the semiconductor chip can be removed on the passive side to a thickness of 20 micrometers to 50 micrometers. As a result, a film-like semiconductor chip can even be produced.
  • the semiconductor wafer thinned out in this way can then be divided into individual semiconductor chips on the semiconductor wafer, which chips are inserted onto a chip card carrier or directly into a chip card, the passive side facing one side of the chip card carrier.
  • the connection between the handling chip and the semiconductor chip is preferably released by passivating the adhesive layer before the semiconductor chip is introduced onto a chip card carrier.
  • the chip card can be finished by overmolding the semiconductor chip or by lamination processes. Due to the favorable mechanical properties, the semiconductor chip can use almost the entire surface of the chip card.
  • the passive side of the semiconductor wafer can be removed at least partially by means of chemical and / or mechanical thin grinding.
  • the removal can also take place in at least a wet chemical manner.
  • a basic idea essential to the invention is to reduce the semiconductor wafer to film thickness by back etching, so that silicon as the base material loses its brittle material properties.
  • This backside etching to a few micrometers allows the production of silicon foils, which are then used as component foils, for example, in card production.
  • the film is then part of the chip card.
  • the chip card takes over the task of the housing, so that chip sizes are possible that theoretically can go up to the card size.
  • the film is then connected to the outside world by only form-fitting electrical contacts.
  • the contacts can be printed on, implemented with a BGA technique or provided as a module. The electrical contacts then only have the function of connections and no longer a mechanical protective function, as in the modules used today.
  • the invention also includes a semiconductor chip, in particular for use in a chip card, which has a thickness of less than approximately 100 micrometers, the semiconductor chip being produced by a method according to the invention, which in particular has the following steps: Providing a semiconductor wafer with a large active side,
  • the semiconductor wafer according to the invention can subsequently be divided into at least one semiconductor chip, in particular by a mechanical method such as sawing and / or by a thermal method such as laser cutting, the handling wafer preferably not being destroyed in the process.
  • the step of removing the passive side of the semiconductor chip down to a thickness of 100 micrometers the step of removing the passive side from a thickness of 20 micrometers to 50 micrometers can be provided, the removal being carried out at least partially by means of chemical and / or mechanical thin grinding or at least partially in a wet chemical manner.
  • the semiconductor chip according to the invention is characterized by high mechanical flexibility.
  • FIG. 1 shows a chip card according to the invention in cross section
  • Figure 2 shows another chip card according to the invention in
  • FIG. 3 shows a cross section through a semiconductor chip according to the invention.
  • FIG. 1 shows a cross section through a chip card 1 according to the invention, which is divided into a card body 2, a chip film 3 and a contact area 4.
  • the chip film 3 is extrusion-coated with plastic in a casting technique.
  • the card body 2 is made in one piece, so that the chip film 3 is essentially completely enveloped by the card body.
  • the contact area 4 is provided in a form-fitting manner in the card body 2 and represents the connection between the chip film 3 and the outside world.
  • electrical contacts 5, which are inserted in a module 6, take over the electrical connection. Due to the thin design of the chip film 3, the chip card 1 is highly flexible and can be bent to a large extent without the chip film 3 showing cracks in one of its surface areas.
  • FIG. 2 shows a further chip card 10 according to the invention, which corresponds in its essential parts to the chip card 1 from FIG. 1. The same components are therefore given the same reference numbers. Deviating from FIG. 1, the chip film 3 has been finished in a laminating technique.
  • chip card 10 has a card body 11 which is constructed in multiple layers.
  • the card body 11 has a base layer 12 on the underside of the card body and a cover layer 13 on the top of the card body 11.
  • the chip film 3 is arranged between the support layer 12 and the cover layer 13, with laminating films 14 being provided as connection areas in edge regions of the card body 11 in order to make the card body 11 completely closed.
  • the passive side of the chip film 3 is attached to the base layer 12.
  • the laminating foils 14 and finally the cover layer 13 are then applied to the chip foil 3 and the support layer 12.
  • the contact area 4 is inserted into the cover layer 13.
  • FIG. 3 shows a semiconductor chip 20 according to the invention, which is attached to a semiconductor chip 22 via an adhesive layer 21.
  • An active side of the semiconductor chip 20 faces the semiconductor chip 22, while a passive side of the semiconductor chip 20 points away from the semiconductor chip 22.
  • An electrically active structure is provided in the active side of the semiconductor chip 20, which is indicated by a thin dash line.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

Une puce semiconductrice (3) s'utilisant dans une carte à puce (1) présente une épaisseur inférieure à environ 100 mu m. Grâce au procédé décrit, des cartes à puce (1) sont équipées de puces semiconductrices (3) de surface particulièrement grande, des structures de circuit importantes et même des mémoires de grande surface pouvant être disposées sur cette puce semiconductrice (3).
PCT/DE1998/003228 1997-11-13 1998-11-05 Film de silicium servant de substrat de circuits semiconducteurs faisant partie de cartes WO1999026287A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19750316.0 1997-11-13
DE1997150316 DE19750316A1 (de) 1997-11-13 1997-11-13 Siliziumfolie als Träger von Halbleiterschaltungen als Teil von Karten

Publications (1)

Publication Number Publication Date
WO1999026287A1 true WO1999026287A1 (fr) 1999-05-27

Family

ID=7848626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1998/003228 WO1999026287A1 (fr) 1997-11-13 1998-11-05 Film de silicium servant de substrat de circuits semiconducteurs faisant partie de cartes

Country Status (2)

Country Link
DE (1) DE19750316A1 (fr)
WO (1) WO1999026287A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10113769A1 (de) * 2001-03-21 2002-10-02 Infineon Technologies Ag Halbleiterchip
DE10106492B4 (de) * 2000-02-14 2007-06-14 Sharp K.K. Verbiegefähige Halbleitervorrichtung und Verfahren zu deren Herstellung
US7692312B2 (en) 2000-02-14 2010-04-06 Sharp Kabushiki Kaisha Semiconductor device having reinforcement member and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19931240C2 (de) * 1999-07-07 2001-08-02 Infineon Technologies Ag Chipkarte
DE10232914B4 (de) * 2002-07-19 2004-11-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Wiederverwendbarer Trägerwafer und Verfahren zur Herstellung desselben

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155068A (en) * 1989-08-31 1992-10-13 Sharp Kabushiki Kaisha Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
EP0637841A2 (fr) * 1993-08-04 1995-02-08 Hitachi, Ltd. Dispositif semiconducteur à couche mince et procédé de fabrication
US5703755A (en) * 1995-04-03 1997-12-30 Aptek Industries, Inc. Flexible electronic card and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4433845A1 (de) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155068A (en) * 1989-08-31 1992-10-13 Sharp Kabushiki Kaisha Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
EP0637841A2 (fr) * 1993-08-04 1995-02-08 Hitachi, Ltd. Dispositif semiconducteur à couche mince et procédé de fabrication
US5703755A (en) * 1995-04-03 1997-12-30 Aptek Industries, Inc. Flexible electronic card and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"DISCLOSED ANONYMOUSLY", RESEARCH DISCLOSURE, no. 348, 1 April 1993 (1993-04-01), pages 280, XP000304243 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10106492B4 (de) * 2000-02-14 2007-06-14 Sharp K.K. Verbiegefähige Halbleitervorrichtung und Verfahren zu deren Herstellung
US7692312B2 (en) 2000-02-14 2010-04-06 Sharp Kabushiki Kaisha Semiconductor device having reinforcement member and method of manufacturing the same
DE10113769A1 (de) * 2001-03-21 2002-10-02 Infineon Technologies Ag Halbleiterchip

Also Published As

Publication number Publication date
DE19750316A1 (de) 1999-05-27

Similar Documents

Publication Publication Date Title
EP0978093B1 (fr) Carte a puce, procede de fabrication d'une carte a puce, et puce de semi-conducteur utilisable dans une carte a puce
DE69434234T2 (de) Chipkarte und Herstellungsmethode
DE69838053T2 (de) Elektronische Schaltung, insbesondere für implantierbare aktive medizinische Vorrichtung, wie ein Herzstimulator oder -defibrillator, und deren Herstellungsmethode
DE10164800B4 (de) Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
DE102004011702B4 (de) Verfahren zur Herstellung eines Kartenkörpers für eine kontaktlose Chipkarte
DE68929367T2 (de) Kartenmodul für integrierte Schaltung
EP1394855B1 (fr) Procédé de fabrication d'un boîtier universel pour dispositif électronique semi-conducteur
WO2005013352A2 (fr) Procede de production d'un composant a semi-conducteur comportant un boitier en matiere plastique et plaque support pour mettre ledit procede en oeuvre
DE102004052921A1 (de) Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen
EP1186035A1 (fr) Composant electronique a structures de contact souples et procede de fabrication d'un tel composant
DE19757269B4 (de) Verfahren zur Herstellung eines Silicium-Auf-Isolator-Halbleitersubstrats
WO2000021028A1 (fr) Procede pour produire un microtranspondeur
DE102006037532A1 (de) Verfahren zur Erzeugung einer elektrischen Funktionsschicht auf einer Oberfläche eines Substrats
EP0865081B1 (fr) Procédé de fabrication d'éléments électroniques
DE102013202910A1 (de) Optoelektronisches Bauelement und Verfahren zu seiner Herstellung
DE3881360T2 (de) Verfahren zum anbringen eines elektronischen bauelementes auf einem substrat.
DE69316159T2 (de) Verfahren zum Aufbringen von Kontakthöckern auf einer Halbleitervorrichtung sowie zum Verbinden dieser Vorrichtung mit einer Leiterplatte
WO1999026287A1 (fr) Film de silicium servant de substrat de circuits semiconducteurs faisant partie de cartes
DE102010039156A1 (de) Verfahren zum Herstellen einer elektrischen Schaltung und elektrische Schaltung
DE102006027283A1 (de) Verfahren zur Herstellung eines Halbleiterbauteils
DE60002328T2 (de) Vorrichtung und hestellungsverfahren von vorrichtungen mit zumindest einer ic au
EP0852774B1 (fr) Module de puce
DE10304777B4 (de) Verfahren zur Herstellung eines Chipnutzens mittels eines Hitze- und Druckprozesses unter Verwendung eines thermoplastischen Materials und Vorrichtung zur Durchführung des Verfahrens
DE102005057256A1 (de) Verfahren zum Herstellen eines Moduls mit einer integrierten Schaltung auf einem Substrat und ein dadurch hergestelltes Modul
DE10106492B4 (de) Verbiegefähige Halbleitervorrichtung und Verfahren zu deren Herstellung

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): BR CN JP KR MX RU UA US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase