JP5149876B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5149876B2 JP5149876B2 JP2009172477A JP2009172477A JP5149876B2 JP 5149876 B2 JP5149876 B2 JP 5149876B2 JP 2009172477 A JP2009172477 A JP 2009172477A JP 2009172477 A JP2009172477 A JP 2009172477A JP 5149876 B2 JP5149876 B2 JP 5149876B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 238000000465 moulding Methods 0.000 claims description 47
- 229920005989 resin Polymers 0.000 claims description 40
- 239000011347 resin Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 39
- 230000001681 protective effect Effects 0.000 claims description 24
- 238000003825 pressing Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 125000003903 2-propenyl group Chemical group [H]C([*])([H])C([H])=C([H])[H] 0.000 claims description 2
- 229920003180 amino resin Polymers 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 150000003949 imides Chemical class 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000005011 phenolic resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 229920002050 silicone resin Polymers 0.000 claims description 2
- 229920006337 unsaturated polyester resin Polymers 0.000 claims description 2
- 239000012808 vapor phase Substances 0.000 claims description 2
- 238000001723 curing Methods 0.000 claims 2
- 238000000016 photochemical curing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001179 sorption measurement Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
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Description
前記保護絶縁膜上に選択的に硬化型の樹脂層を形成することにより、前記複数の外部接続端子それぞれのコアとなる複数の凸部を形成する工程と、
前記凸部を硬化させる前に、表面が平坦である成型用治具を前記複数の凸部の上面に押し付けることにより、複数の前記上面それぞれに平坦部を形成する工程と、
前記複数の凸部を硬化させる工程と、
前記複数の凸部、前記保護絶縁膜、及び前記複数の電極パッド上に導電膜を選択的に形成することにより、前記複数の外部接続端子、及び前記複数の外部接続端子それぞれをいずれかの前記電極パッドに接続する複数の配線を形成する工程と、
を備える半導体装置の製造方法が提供される。
前記保護絶縁膜に形成された複数の開口と、
前記複数の開口それぞれに位置する複数の電極パッドと、
前記保護絶縁膜上に形成された複数の外部接続端子と、
前記複数の外部接続端子それぞれをいずれかの前記電極パッドに接続する複数の配線と、
を備え、
前記外部接続端子は、
樹脂からなる凸部と、
前記凸部上に形成され、前記配線につながる導電膜と、
を備え、
前記複数の外部接続端子それぞれの前記凸部は、上面が平坦であり、かつ同一平面を形成している半導体装置が提供される。
前記半導体基板を挟んで前記ステージに対向して配置され、前記ステージに対向している対向面が平坦である成型用治具と、
前記ステージ及び前記成型用治具の少なくとも一方を他方に向けて移動させる移動機構と、
を備える半導体製造装置が提供される。
12 吸着機構
14 加熱部
20 成型用治具
22 対向面
30 移動機構
40 制御部
50 光源
100 半導体基板
110 多層配線層
120 保護絶縁膜
122 開口
130 電極パッド
200 外部接続端子
202 凸部
204 導電膜
206 導電膜
210 配線
300 実装基板
310 電極
Claims (7)
- 保護絶縁膜、前記保護絶縁膜に形成された複数の開口、及び前記複数の開口それぞれから露出している複数の電極パッドを有する半導体基板に複数の外部接続端子を形成する工程を有する半導体装置の製造方法であって、
(a)前記保護絶縁膜上に選択的に硬化型の樹脂層を形成することにより、前記複数の外部接続端子それぞれのコアとなる複数の凸部を形成する工程と、
(b)前記凸部を硬化させる前に、平坦面を有する成型用治具を前記半導体基板に対向させ、前記平坦面と前記半導体基板を平行に保ち、前記複数の凸部の上面に前記平坦面を押し付けることにより、前記複数の凸部の上面の各々が同一平面を成す平坦部を形成する工程と、
(c)前記複数の凸部の上面と前記平坦面が接触し、前記複数の凸部の上面が同一平面を保った状態で、前記凸部を硬化させる工程と、
(d)前記(c)の後、前記複数の凸部の上面から前記平坦面を引き離す工程と、
(e)前記(d)の後、前記複数の凸部、前記保護絶縁膜、及び前記複数の電極パッド上に導電膜を選択的に形成することにより、前記複数の外部接続端子、及び前記複数の外部接続端子それぞれをいずれかの前記電極パッドに接続する複数の配線を形成する工程と、
を備える半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)において、前記樹脂層は熱硬化性の樹脂により形成され、前記凸部を加熱することにより、前記凸部を硬化する半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記熱硬化性の樹脂は、フェノール樹脂、エポキシ樹脂、ポリイミド樹脂、アミノ樹脂、不飽和ポリエステル樹脂、ケイ素樹脂、又はアリル樹脂である半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(c)において、前記樹脂層は光硬化性の樹脂により形成され、前記成型用治具の表面を前記複数の凸部の上面に押し付けた後、前記成型用治具の前記平坦面を前記複数の凸部の上面と接触した状態で前記凸部に光を照射することにより、前記凸部を硬化する半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記樹脂層は光硬化性の樹脂により形成され、前記成型用治具は光透過性の材料により形成されており、
前記成型用治具の前記平坦面を前記複数の凸部の上面に押し付けつつ、前記成型用治具を介して前記凸部に光を照射することにより、前記凸部を硬化する半導体装置の製造方法。 - 請求項4又は5に記載の半導体装置の製造方法において、
前記光硬化性の樹脂は、シリコーン系樹脂又はイミド系樹脂である半導体装置の製造方法。 - 請求項1〜6のいずれか一つに記載の半導体装置の製造方法において、
前記(e)において、前記複数の外部接続端子及び前記複数の配線を形成する工程は、
(e−1)前記複数の凸部、前記保護絶縁膜、及び前記複数の電極パッド上に前記導電膜を気相法により形成する工程と、
(e−2)前記導電膜を選択的に除去する工程と、
を備える半導体装置の製造方法。
Priority Applications (3)
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JP2009172477A JP5149876B2 (ja) | 2009-07-23 | 2009-07-23 | 半導体装置の製造方法 |
US12/801,367 US8541300B2 (en) | 2009-07-23 | 2010-06-04 | Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus |
CN2010102211901A CN101964308B (zh) | 2009-07-23 | 2010-06-30 | 制造半导体器件的方法、半导体器件以及半导体制造设备 |
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JP2009172477A JP5149876B2 (ja) | 2009-07-23 | 2009-07-23 | 半導体装置の製造方法 |
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JP5149876B2 true JP5149876B2 (ja) | 2013-02-20 |
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US6080605A (en) * | 1998-10-06 | 2000-06-27 | Tessera, Inc. | Methods of encapsulating a semiconductor chip using a settable encapsulant |
JP2003502866A (ja) * | 1999-06-17 | 2003-01-21 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | 軟質ボンディング部を有する電子部品およびこのような部品を製造するための方法 |
JP2005223250A (ja) * | 2004-02-09 | 2005-08-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法と検査方法 |
US7597814B2 (en) * | 2004-03-23 | 2009-10-06 | Hewlett Packard Development Company, L.P. | Structure formed with template having nanoscale features |
JP4207004B2 (ja) * | 2005-01-12 | 2009-01-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2007048971A (ja) * | 2005-08-10 | 2007-02-22 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2007317857A (ja) * | 2006-05-25 | 2007-12-06 | Fujikura Ltd | 半導体装置及びその製造方法 |
JP2008109024A (ja) * | 2006-10-27 | 2008-05-08 | Seiko Epson Corp | 半導体装置及び電子デバイス、並びに、電子デバイスの製造方法 |
JP2008306146A (ja) * | 2007-06-11 | 2008-12-18 | Toyota Industries Corp | 電極ポスト平坦化装置およびウェハレベルパッケージ製造方法 |
JP5169071B2 (ja) | 2007-08-21 | 2013-03-27 | セイコーエプソン株式会社 | 電子部品、電子装置、電子部品の実装構造体及び電子部品の実装構造体の製造方法 |
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US8541300B2 (en) | 2013-09-24 |
CN101964308B (zh) | 2013-05-29 |
JP2011029342A (ja) | 2011-02-10 |
US20110018137A1 (en) | 2011-01-27 |
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