WO2024079183A1 - Procédé de fabrication d'un composant et composant - Google Patents

Procédé de fabrication d'un composant et composant Download PDF

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Publication number
WO2024079183A1
WO2024079183A1 PCT/EP2023/078179 EP2023078179W WO2024079183A1 WO 2024079183 A1 WO2024079183 A1 WO 2024079183A1 EP 2023078179 W EP2023078179 W EP 2023078179W WO 2024079183 A1 WO2024079183 A1 WO 2024079183A1
Authority
WO
WIPO (PCT)
Prior art keywords
carrier
semiconductor chip
electrically conductive
conductive connection
region
Prior art date
Application number
PCT/EP2023/078179
Other languages
German (de)
English (en)
Inventor
Thomas Schwarz
Bernd Barchmann
Sebastian Wittmann
I-Hsin LIN-LEFEBVRE
Original Assignee
Ams-Osram Inernational Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams-Osram Inernational Gmbh filed Critical Ams-Osram Inernational Gmbh
Publication of WO2024079183A1 publication Critical patent/WO2024079183A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present invention relates to a method for producing a component and to a component.
  • a semiconductor chip for example an optoelectronic semiconductor chip
  • a carrier is conductively connected to electrical line regions of the carrier. This can be done, for example, by means of a solder, a conductive adhesive, a conductive glue, sintering pastes and other conductive connections.
  • An object of the present invention is to provide an improved method for producing the component, in which an electrical connection of the semiconductor chip can be easily created.
  • a further object of the present invention is to provide such a component.
  • a first aspect of the invention relates to a method for producing a component, in which the following steps are carried out.
  • a carrier is provided, wherein the carrier has an electrically non-conductive carrier material.
  • the carrier can optionally have conductive areas, for example in the form of metal coatings.
  • the carrier can be a printed circuit board (PCB).
  • an adhesive layer is applied to the carrier.
  • a semiconductor chip is then applied to the adhesive layer.
  • the semiconductor chip has a contact region that faces the carrier.
  • a surface of the carrier is activated before the semiconductor chip is applied.
  • An electrically conductive connection is then produced between the contact region of the semiconductor chip and the carrier by means of a metal coating in such a way that the electrically conductive connection at least partially adjoins the carrier.
  • the metal coating therefore has direct contact with the carrier in at least one area.
  • the carrier and the metal coating therefore touch each other in at least one area, without any further elements or layers being arranged in between. If the carrier has the optional conductive areas, it can be provided that an electrically conductive connection is made between the conductive area and the contact area using the metal coating. If the carrier has no conductive areas, it can be provided that conductive areas of the carrier, which can be used for further contacting of the semiconductor chip, are made using the metal coating. This method is easy to carry out, so that an uncomplicated method for producing a component is possible.
  • the semiconductor chip can in particular contain an integrated circuit and be arranged in a chip housing. Alternatively, it can be provided that the semiconductor chip is applied without a housing.
  • the adhesive can have an adhesive or consist of an adhesive.
  • the adhesive can be based on a polymer, based on a metal paste, have a B-stage material or consist of a B-stage material, have a sticky thermoplastic and/or a sticky duroplastic or consist of a sticky thermoplastic or a sticky duroplastic.
  • the adhesive can in particular be designed to be electrically insulating.
  • a position of the semiconductor chip is determined and the metal coating is adapted to the position. In this way, a tolerance of the position can be taken into account and improved contacting of the semiconductor chip can be achieved.
  • a surface of the carrier and optionally a surface of the semiconductor chip is activated.
  • This can mean, for example, that the surface of the carrier and/or the surface of the semiconductor chip is at least 20% rougher in activated areas than in areas that have not been activated. This can have the advantage that a static electrical charge is created on the rougher surfaces, which makes it easier to apply the metal coating.
  • the surface of the carrier and/or the semiconductor chip is activated by means of laser radiation.
  • laser radiation This allows simple activation.
  • the position of the semiconductor chip has also been determined, the shape or arrangement of the activated region can be changed by adjusting the impact of the laser radiation, thus taking the position of the semiconductor chip into account.
  • a laser for generating the laser radiation has an output of approximately one watt.
  • the laser can, for example, be operated in pulsed mode with a pulse length of 10 to 20, in particular 10 to 15, and for example with a pulse length of 12 picoseconds.
  • the wavelength of the laser can be in the range 1000 to 1100 nanometers and can be, for example, 1064 nanometers.
  • the laser can in particular be an infrared laser.
  • the laser radiation can be used to roughen the surface of the carrier and/or the surface of the semiconductor chip by at least 20%.
  • the surface of the carrier and/or the surface of the semiconductor chip is chemically activated.
  • the chemical activation can be carried out, for example, by applying substances and/or elements, whereby the applied substances and/or elements can result in an improved application of the metal coating. It can be provided that both the chemical activation and the activation already described are carried out by means of a laser.
  • the surface of the carrier and/or the surface of the semiconductor chip is chemically activated using palladium.
  • Palladium is an element that is well suited for chemical activation.
  • the semiconductor chip has a further contact region that faces away from the carrier.
  • the surface of the semiconductor chip is activated after the semiconductor chip has been applied.
  • a further electrically conductive connection is produced between the further contact region of the semiconductor chip and the carrier by means of a further metal coating in such a way that the further electrically conductive connection at least partially adjoins the carrier. This allows the further contact region to be contacted on an upper side of the semiconductor chip.
  • the semiconductor chip has both a contact area facing away from the carrier and a contact area facing the carrier.
  • the surface of the carrier can be activated first, then the semiconductor chip can be applied and then the surface of the semiconductor chip can be activated, in which case an additional surface of the carrier can be activated.
  • an additional surface of the carrier can be activated.
  • the carrier has an electrically conductive region.
  • the electrically conductive connection is established between the contact region of the semiconductor chip and the electrically conductive region.
  • the electrically conductive connection is produced by metallization from an aqueous solution.
  • Metal atoms, which later form the metallization are dissolved in a solution, for example in the form of a salt.
  • a solution for example in the form of a salt.
  • the metallization is carried out in the form of a galvanic deposition.
  • the metallization can be carried out in the form of an electroless galvanic deposition. This can, for example, lead to a further improvement in the deposition.
  • a conductive layer is produced on the carrier during application of the metal coating. This makes it possible to initially design the carrier without conductive layers and to accomplish the contacting of the semiconductor chip and the production of the conductive layers in one work step.
  • the electrically conductive connection is applied as a metal layer.
  • the metal layer can in particular contain copper or consist entirely of copper.
  • the metal layer may also contain or consist of nickel, gold, palladium, silver or tin.
  • an electrical test voltage is applied to the semiconductor chip. If a fault in the semiconductor chip and/or the electrically conductive connection is detected, the electrically conductive connection is interrupted, a further adhesive layer is applied to the carrier, a further semiconductor chip is applied to the further adhesive layer, and a further electrically conductive connection is established between at least one further contact region of the further semiconductor chip and the carrier by means of a further metal coating. In this way, faulty semiconductor chips can be replaced.
  • the electrically conductive connection is interrupted by means of a laser. This enables the method to be implemented easily.
  • the semiconductor chip is an optoelectronic semiconductor chip, in particular a mini-LED or a micro-LED.
  • the component can then be referred to as an optoelectronic component.
  • the optoelectronic semiconductor chip can also be arranged in a housing or applied without a housing.
  • the optoelectronic semiconductor chip i.e. possibly the mini-LED or the micro-LED, has a conversion element.
  • a surface of the conversion element is activated. This activation can be designed as described above for the carrier or the semiconductor chip and can use the same methods.
  • a conductive area of the carrier is covered with an insulating layer. When the electrically conductive connection is made, a conductive bridge is also created over the insulating layer. If necessary, the insulating layer can also be activated here using the methods described above.
  • the invention comprises a component with a carrier, a semiconductor chip and an electrically conductive connection.
  • An adhesive layer is arranged between the carrier and the semiconductor chip.
  • the electrically conductive connection is established between the carrier and at least one contact region of the semiconductor chip facing the carrier.
  • the electrically conductive connection has a metal coating and is at least partially adjacent to an activated surface of the carrier.
  • the semiconductor chip can in particular contain an integrated circuit and be arranged in a chip housing. Alternatively, it can be provided that the semiconductor chip is designed without a housing.
  • the semiconductor chip can also be an optoelectronic semiconductor chip, in particular a mini-LED or a micro-LED.
  • the component can then be referred to as an optoelectronic component.
  • the optoelectronic semiconductor chip can also be arranged in a housing or be designed without a housing.
  • the carrier has a first region adjacent to the metal coating and a second region outside the metal coating.
  • a carrier surface of the carrier is rougher in the first region than in the second region.
  • the rough carrier surface can be produced in particular by means of the activations described above.
  • a roughness can be increased by at least 20 percent, for example.
  • no conductive region is arranged between the semiconductor chip and the carrier.
  • the carrier surface under the semiconductor chip is at least partially rougher than in areas that are not covered by the semiconductor chip.
  • Fig. 1 shows cross sections through various intermediate steps during a process for producing a component
  • Fig. 2 Top views of the intermediate steps of Fig. 1;
  • FIG. 3 shows cross sections through various intermediate steps during a further process for producing a component
  • Fig. 4 Top views of the intermediate steps of Fig. 3;
  • Fig. 5 shows cross sections through various intermediate steps during a further process for producing a component
  • Fig. 6 Top views of the intermediate steps of Fig. 5;
  • Fig. 7 shows cross sections through various intermediate steps during a further process for producing a component
  • Fig. 8 Top views of the intermediate steps of Fig. 7; Fig. 9 Cross sections through various intermediate steps during a further process for producing a component;
  • Fig. 10 shows plan views of various intermediate steps during a further method for producing a component
  • FIG. 11 Cross sections through various intermediate steps during a further process for producing a component
  • Fig. 12 is a side view of a component
  • FIG. 13 Top views of various intermediate steps during a further method for producing a component.
  • Fig. 1 shows cross sections through various intermediate steps during a method for producing a component 100.
  • a carrier 110 is provided which has an electrically non-conductive carrier material 111.
  • the carrier material 111 is therefore designed to be electrically insulating.
  • the carrier 110 also has optional conductive regions 112.
  • the conductive regions 112 can be designed as conductor tracks, for example.
  • an adhesive layer 120 is applied to the carrier 110.
  • the adhesive layer 120 is arranged between the conductive regions 112, but can also be provided at a different location on the carrier 110.
  • a semiconductor chip 130 is applied to the adhesive layer 120.
  • the semiconductor chip 130 has two contact areas 131 with which the semiconductor chip 130 can be electrically contacted.
  • more than two contact areas 131 can also be provided.
  • the contact areas 131 face the conductive areas 112.
  • the semiconductor chip 130 covers the conductive areas 112 at least partially.
  • an electrically conductive connection 150 is produced between the contact areas 131 of the semiconductor chip 130 and the carrier 110 by means of a metal coating 151.
  • the electrically conductive connection 150 is produced in such a way that the electrically conductive connection 150 at least partially adjoins the carrier 110, here by adjoining the conductive areas 112 of the carrier 110. Because the semiconductor chip 130 at least partially covers the conductive areas 112, the metal coating 151 only has to fill a small gap between the contact areas 131 and the conductive areas 112. This ultimately results in a component 100 with a carrier 110, a semiconductor chip
  • an adhesive layer 120 is arranged between the carrier 110 and the semiconductor chip 130 and the electrically conductive connection 150 between the carrier 110 and at least one contact region 131 of the semiconductor chip 130 is produced by means of a metal coating 151 and in which the electrically conductive connection 150 at least partially adjoins the carrier 110.
  • the semiconductor chip 130 can be connected to the carrier 110 by means of the electrically conductive connection 150.
  • the semiconductor chip 130 can comprise, for example, an integrated circuit. In particular, in this case, more than two contact areas 131 can be provided. Alternatively, the semiconductor chip 130 can also be an optoelectronic semiconductor chip 130.
  • the metal coating 151 can in particular comprise the metals copper, nickel, gold, silver, palladium or tin or consist entirely of one of these metals.
  • the carrier material 111 can in particular be a glass, ceramic, metal or a thermoplastic material. or a thermosetting plastic, as well as a composite material consisting of several of the materials mentioned.
  • the adhesive layer 120 can be applied, for example, in the form of adhesive dots or in the form of adhesive strips.
  • the adhesive of the adhesive layer 120 can be based on a polymer, based on a metal paste, have a B-stage material or consist of a B-stage material, have a sticky thermoplastic and/or a sticky duroplastic or consist of a sticky thermoplastic or a sticky duroplastic.
  • the adhesive can in particular be designed to be electrically insulating.
  • Fig. 2 shows the intermediate steps of Fig. 1 in a plan view.
  • the adhesive layer 120 is designed as an adhesive point 121.
  • the electrically conductive connection 150 is produced by means of metallization from an aqueous solution. This represents a simple way of producing the electrically conductive connection 150. In particular, in this embodiment, it is not necessary to produce a sintered connection and/or a soldered connection.
  • the metal coating 151 can be applied directly. This means that the use of silver as a sintered material and/or soldering material can be dispensed with. This reduces or completely eliminates silver corrosion or migration of silver atoms.
  • the metallization is carried out in the form of a galvanic deposition.
  • the metallization can be carried out in the form of an electroless galvanic deposition. This also enables a simple manufacturing process.
  • Fig. 3 shows cross sections through various intermediate steps during another process for producing a Component 100, the method being analogous to the method described in connection with FIGS. 1 and 2, unless differences are described below.
  • an activated region 140 is created, the activated region 140 being created by means of laser radiation 141.
  • the activated region 140 is created on a surface 113 of the carrier 110.
  • the activated region 140 can, for example, have increased roughness and can, for example, be at least 20 percent rougher than non-activated regions of the carrier 110.
  • the activated region 140 makes it easier to coat with the metal coating 151.
  • the laser radiation 141 can be infrared laser radiation.
  • a laser for generating the laser radiation 141 has an output of approximately one watt.
  • the laser can be operated in pulsed mode, for example, with a pulse length of 10 to 20, in particular 10 to 15, and for example with a pulse length of 12 picoseconds.
  • the wavelength of the laser can be in the range 1000 to 1100 nanometers and can be, for example, 1064 nanometers.
  • the activated region 141 can also be used to produce the activated region 141.
  • chemical activation is possible. This can be done, for example, by means of a selective application of palladium.
  • it can be provided to produce the activated region 140 both by the laser radiation 141 and by chemical activation. The production of the activated region 140 can be referred to as activating the corresponding surface 113.
  • Fig. 3 it is shown that the creation of the activated region 140 takes place after the application of the adhesive layer 120. However, it is also conceivable to first create the activated region 140 and only then apply the adhesive layer 120.
  • Fig. 4 shows top views of the various process steps of the process explained in connection with Fig. 3. In particular, it is visible that the activated regions 140 extend between the conductive regions 112 and the adhesive layer 120. The activated regions 140 also enclose the conductive regions 112, whereby this configuration is optional and, if necessary, only a lateral contact between the activated regions 140 and the conductive regions 112 can be provided.
  • Fig. 4 shows that the adhesive layer 120 is arranged perpendicular to the semiconductor chip 130 and forms a line. This can, for example, achieve improved electrical insulation, since the metal coating 151 may only adhere to the carrier 110 outside the adhesive layer 120.
  • the design shown here in Fig. 4 can also be provided in the other exemplary embodiments.
  • an adhesive point can alternatively also be provided in Figs. 3 and 4, as explained in connection with Figs. 1 and 2.
  • Fig. 5 shows cross sections through various intermediate steps during a further method for producing a component 100, the method being analogous to the method described in connection with Figs. 3 and 4, unless differences are described below.
  • the carrier 110 in Figs. 3 and 4 the carrier 110 has no conductive regions 112.
  • the conductive regions 112 are only created by the application of the metal coating 151. This makes the method very flexible, since the guidance of the conductive regions 112 can be influenced by the irradiation with the laser radiation 141. This enables a further simplification of the manufacturing method.
  • Fig. 6 shows top views of the intermediate steps of the method of Fig. 5.
  • the activated areas 140 have a projection 142, so that the activated areas 140, in contrast to Fig. 4, extend laterally over the semiconductor chip 130. This makes it possible to provide an improved electrically conductive connection 150.
  • Such projections are also possible in the area of the conductive regions 112 in Figs. 3 and 4.
  • the metal coating can be designed such that the metal coatings 151 form a grid on the carrier 110 or that the metal coatings 151 form conductor tracks on the carrier 110.
  • the semiconductor chip 130 has at least one contact region 131 that faces the carrier 110.
  • the semiconductor chip 130 has at least two such contact regions 131.
  • the surface 113 of the carrier 110 is activated before the semiconductor chip 130 is applied.
  • the laser radiation 141 for forming the activated regions 140 can also be aligned with the shape and position of the adhesive layer 120. This makes it possible, for example, to compensate for positioning errors in the adhesive layer 120.
  • Fig. 7 shows cross sections through various intermediate steps during a further method for producing a component 100, the method being analogous to the method described in connection with Figs. 3 and 4, unless differences are described below.
  • the adhesive layer 120 is applied as a flat layer.
  • the semiconductor chip 130 is first applied, in this case the contact areas 131 of the semiconductor chip 130 facing away from the carrier 110. Furthermore, the adhesive layer 120 is partially removed so that the adhesive layer 120 is arranged exclusively below the semiconductor chip 130.
  • a Surface 132 of the semiconductor chip 130 is activated so that the activated region 140 extends from the carrier 110 to the semiconductor chip 130.
  • the activated regions 140 can be produced using the methods already described.
  • the electrically conductive connection 150 is subsequently produced in the form of a metal coating 151.
  • Fig. 8 shows top views of the intermediate steps of Fig. 7.
  • the activated regions 140 are formed both on the surface 113 of the carrier 110 and on the surface 132 of the semiconductor chip 130.
  • the activated regions 140 do not have a projection 142, but one can also be provided.
  • a conductive region 112 is again arranged on the carrier 110. However, this can also be produced as a metal coating 151, analogous to Figs. 5 and 6.
  • a position of the semiconductor chip 130 is determined and the metal coating 151 is adapted to the position. This can be done in particular by adapting the activated region 140.
  • Fig. 9 shows cross sections through various intermediate steps during a further method for producing a component 100, the method being analogous to the method described in connection with Figs. 3 and 4, unless differences are described below.
  • the semiconductor chip 130 has a contact region 131 facing the carrier 110 and a contact region 131 facing away from the carrier 110. For this reason, an activated region 140 is created analogously to Figs. 3 and 4 before the semiconductor chip 130 is applied and an activated region 140 after the semiconductor chip 130 is applied, the latter activated region again extending analogously to Fig. 7 onto a surface 132 of the semiconductor chip 130.
  • optional designs are again possible, such as projections 142 or the omission of the guide regions 112 on the carrier 110 or the creation of the guide regions 112 during the application of the metal coating 151.
  • Fig. 10 shows plan views of various intermediate steps during a further method for producing a component 100.
  • the component 100 is initially produced as explained in connection with Figs. 7 and 8, whereby the methodology described below can also be applied analogously to the other embodiments of the method.
  • an electrical test voltage is applied to the semiconductor chip 130, for example via the metal coating 151.
  • the electrically conductive connection 150 is interrupted. This is shown in Fig. 10 as a separation 152.
  • a further adhesive layer 122 is then applied to the carrier 110.
  • a further semiconductor chip 133 is applied to the further adhesive layer 122.
  • a further electrically conductive connection 153 is then produced between at least one further contact region 134 of the further semiconductor chip 133 and the carrier 110 by means of a further metal coating 154.
  • this is done by forming a further activated region 143 on the surface 113 of the carrier 110 and a surface 132 of the further semiconductor chip 133 and then applying the metal coating 151.
  • the further activated region 143 can be produced using the methods already described. It can be provided that the severing 152 takes place using laser radiation.
  • a component 100 with a further semiconductor chip 133 is produced, which may not have any defects.
  • Fig. 11 shows cross sections through various intermediate steps during a further method for producing a component 100, which corresponds to the method of Figs.
  • the semiconductor chip 130 in this case is an optoelectronic semiconductor chip 130, for example a miniLED or a micro-LED.
  • the optoelectronic semiconductor chip 130 has a conversion element 135.
  • the activated region 140 is also formed on a surface 136 of the conversion element 135. This is particularly useful when the optoelectronic semiconductor chip 130 has contact regions 131 that face away from the carrier 110 and/or the conversion element 135 is arranged between the optoelectronic semiconductor chip 130 and the carrier 110.
  • the laser radiation 141 can also be aligned to form the activated regions 140 at a position of the semiconductor chip 130. This makes it possible, for example, to compensate for position errors of the semiconductor chip 130.
  • Fig. 12 shows a side view of a component 100 that can correspond to the component 100 shown in Fig. 11.
  • the metal coating 151 is also arranged on the side of the optoelectronic semiconductor chip 130. This can enable improved contacting.
  • An analogous design can also be provided for the component 100 of Fig. 8 if the conversion element 135 is omitted and a semiconductor chip 130 is generally used.
  • Fig. 13 shows plan views of various intermediate steps during a further method for producing a component 100.
  • the component 100 is initially produced as explained in connection with Figs. 1 to 4, but can also be produced using the methods explained in connection with Figs. 5 to 11.
  • a conductive region 112 of the carrier 110 is covered with an insulation layer 123.
  • a conductor bridge 155 is additionally created over the insulation layer 123.
  • an activated region 140 is optionally guided over the insulation layer 123.
  • the insulation layer 123 can be an adhesive layer.
  • the steps used to produce the component 100 can also be used to produce cross-routed lines on the carrier 110.
  • the invention has been illustrated and described in more detail using the preferred embodiments. However, the invention is not limited to the disclosed examples. Rather, other variations can be derived by the person skilled in the art from the described embodiments without departing from the scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un composant, selon lequel les étapes suivantes sont exécutées. Dans un premier temps, un support est fourni, ledit support comportant un matériau support électriquement non conducteur. Une couche d'adhésif est ensuite appliquée sur le support. Une puce semi-conductrice est ensuite mise en place sur la couche d'adhésif, la puce semi-conductrice présentant une zone de contact qui est tournée vers le support. Une surface du support est activée avant la mise en place de la puce semi-conductrice. Une liaison électroconductrice est ensuite réalisée, entre la zone de contact de la puce semi-conductrice et le support, au moyen d'un revêtement métallique de telle sorte que la liaison électroconductrice jouxte au moins en partie le support.
PCT/EP2023/078179 2022-10-11 2023-10-11 Procédé de fabrication d'un composant et composant WO2024079183A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102022126374.6A DE102022126374A1 (de) 2022-10-11 2022-10-11 Verfahren zum herstellen eines bauelements und bauelement
DE102022126374.6 2022-10-11

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WO2024079183A1 true WO2024079183A1 (fr) 2024-04-18

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102022126374A1 (de) 2022-10-11 2024-04-11 Ams-Osram International Gmbh Verfahren zum herstellen eines bauelements und bauelement

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3439049A1 (fr) * 2017-05-30 2019-02-06 LG Innotek Co., Ltd. Boîtier de dispositif électroluminescent et dispositif de source de lumière
WO2022114395A1 (fr) * 2020-11-30 2022-06-02 삼성전자주식회사 Module d'affichage, et son procédé de fabrication
DE102022126374A1 (de) 2022-10-11 2024-04-11 Ams-Osram International Gmbh Verfahren zum herstellen eines bauelements und bauelement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501663B1 (en) 2000-02-28 2002-12-31 Hewlett Packard Company Three-dimensional interconnect system
DE102004044179B4 (de) 2004-06-30 2010-04-22 Osram Opto Semiconductors Gmbh Verfahren zur Montage von Halbleiterchips
US9059083B2 (en) 2007-09-14 2015-06-16 Infineon Technologies Ag Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3439049A1 (fr) * 2017-05-30 2019-02-06 LG Innotek Co., Ltd. Boîtier de dispositif électroluminescent et dispositif de source de lumière
WO2022114395A1 (fr) * 2020-11-30 2022-06-02 삼성전자주식회사 Module d'affichage, et son procédé de fabrication
DE102022126374A1 (de) 2022-10-11 2024-04-11 Ams-Osram International Gmbh Verfahren zum herstellen eines bauelements und bauelement

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