Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
  • B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
  • B29L2031/00—Other particular articles
  • B29L2031/34—Electrical apparatus, e.g. sparking plugs or parts thereof
  • B29L2031/3493—Moulded interconnect devices, i.e. moulded articles provided with integrated circuit traces
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12044—OLED
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09045—Locally raised area or protrusion of insulating substrate
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
  • H05K2201/09845—Stepped hole, via, edge, bump or conductor
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• Integrated circuits are getting more and more connections and are being miniaturized more and more.
• the difficulties with solder paste application and assembly expected from this increasing miniaturization are to be remedied by new housing shapes, with single, Few or multi-chip modules in the Ball Grid Array Package to be emphasized here (DE-Z productronic 5, 1994, pages 54, 55).
• These modules are based on a plated-through substrate on which the chips are contacted, for example, via contact wires or by means of flip chip assembly.
• On the underside of the substrate is the Ball Grid Array (BGA), which is often referred to as a Solder Grid Array or a Solder Bump Array.
• the ball grid array comprises solder bumps arranged flat on the underside of the substrate, which allow surface mounting on the printed circuit boards or assemblies. Due to the flat arrangement of the solder bumps, large numbers of connections can be realized in a coarse grid of, for example, 1.27 mm.
• injection molded parts with integrated conductor tracks are used instead of conventional printed circuits.
• High-quality thermoplastics that are suitable for injection molding three-dimensional substrates are the basis of this technology.
• Thermoplastics of this type are distinguished from conventional substrate materials for printed circuits by better mechanical, chemical, electrical and environmental properties.
• SIL injection molded parts with integrated conductor tracks
• the structuring of a metal layer applied to the injection molded parts takes place by dispensing with the otherwise usual mask technology using a special Target laser structuring process.
• SIL injection molded parts with integrated conductor tracks
• the housing support functions simultaneously perform guides and snap connections, while the metallization layer also serves as an electromagnetic shield in addition to the wiring and connection function and ensures good heat dissipation.
• corresponding via holes are already produced during injection molding.
• the inner walls of these via holes are then also covered with a metal layer when the injection molded parts are metallized. Further details on the production of three-dimensional injection molded parts with integrated conductor tracks can be found, for example, in DE-A-37 32 249 or EP-A-0 361 192.
• a smgle chip module is known from O-A-89/00346, in which the injection-molded, three-dimensional substrate made of an electrically insulating polymer bears molded stools on the underside of the substrate during injection molding, which stools can optionally also be arranged flat.
• An IC chip is arranged on the upper side of this substrate, the connections of which are connected via fine bonding wires to conductor tracks formed on the upper side of the substrate. These conductor tracks are in turn connected via plated-through holes to associated external connections formed on the stools.
• PSGA polymer stud grid array
• O-A-96 096 46 which combines the advantages of a ball grid array (BGA) with the advantages of MID technology.
• BGA ball grid array
• MID advantages of MID technology.
• the designation of the new design as a polymer stud grid array (PSGA) was based on the ball grid array
• an injection-molded, three-dimensional substrate made of an electrically insulating polymer, polymer bumps arranged flat on the underside of the substrate and molded during injection molding,
• the production of the external connections on the polymer bumps can also be carried out with minimal effort together with the production of the conductor tracks which is customary in the MID technology or the SIL technology. Thanks to the laser fine structuring preferred for SIL technology, the external connections on the polymer bumps with high numbers of connections can be realized in a fine grid.
• the temperature expansion of the polymer bumps corresponds to the temperature expansion of the substrate and the wiring that receives the module. As a result, a high reliability of the soldered connection is achieved even with frequent temperature fluctuations.
• the invention specified in claim 1 is based on the problem of ensuring reproducible solder layer thicknesses under the polymer bumps in the case of a substrate with polymer bumps for the solder connection with a wiring.
• the invention is based on the finding that, by means of a geometry of the polymer bump with at least one elevation, the step or steps formed thereby prevent the molten solder from being pulled up. This results in reproducible solder layer thicknesses under the polymer bumps, which in turn ensure high reliability of the soldered connections. A risk of short circuits due to solder being pulled up can also be excluded.
• the embodiment according to claim 2 is particularly suitable for the production of substrates with integral polymer bumps by injection molding.
• the dimensions given in claim 3 for the cylindrical elevations polymer stud grid arrays lead to particularly reliable solder connections.
• Figure 1 shows a broken section through a
• FIG. 2 shows a polymer bump of the substrate according to FIG. 1 with the metallization applied thereon and with a conductor path leading away from the polymer bump,
• FIG. 3 shows the solder connection of the polymer bump shown in FIG. 2 with a wiring
• FIG. 4 shows a first variant with a two-stage polymer bump
• FIG. 5 shows a second variant for the polymer bumps with several elevations and arranged on one step
• Figure 6 shows a third variant for the polymer bumps with an annular elevation.
• FIG. 1 shows a section through a substrate S, on the underside U of which, to form a polymer stud grid array during injection molding of the substrate, molded polymer bumps PS or Polymer studs are arranged.
• the slightly conical polymer stools PS are each provided with cylindrical increases E at their lower ends.
• the diameters of the cylindrical elevations E are dimensioned such that an annular step ST results in each case as a transition to the remaining polymer stool PS.
• a polymer stool PS m has a diameter D of 400 ⁇ m in its sock area, while the height H is the distance between the underside U of the substrate S and the step ST 400 ⁇ m.
• the diameter d of the cylindrical elevation E is 160 ⁇ m, while the height h of the cylindrical elevation E is 50 ⁇ m.
• FIG. 2 shows a polymer stool PS according to FIG. 1 after the laser permanent structuring of a metal layer applied over the entire surface of the substrate S. It can be seen that the polymer stool PS including the cylindrical elevation E is provided with a metallization M and that a conductor path LZ leads away from the polymer stool PS on the underside U of the substrate S.
• FIG. 3 shows the solder connection of the polymer stool PS shown in FIG. 2 with a wiring V which, in the exemplary embodiment shown, is designed as a printed circuit board LP with connection pads AP arranged on the upper side. It can be clearly seen that the entire solder L remains with the reflow soldering in the area between the step ST and the connection pad AP and is not pulled up laterally up to the conductor lines LZ as in polymer stools without gradation.
• the geometry of the graduated polymer stool PS ensures reproducible layer thicknesses of the solder L.
• the polymer stools integrally molded onto a substrate S1 are designated PS.
• PS1 are an annular elevation El and a cylindrical ge increase E10 formed.
• the associated ring-shaped steps are designated ST1 and ST10.
• the polymer bumps integrally molded onto a substrate S2 are designated PS2.
• a stage ST2 designed as a platform a total of four cylindrical ridges E2 arranged at a distance from one another are provided.
• the polymer bumps integrally molded onto a substrate S3 are designated PS3.
• a step ST3 which is also designed as a platform, there is an annular elevation E3.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Electric Connection Of Electric Components To Printed Circuits (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Applications Claiming Priority (3)

Publications (1)

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ID=7908690

Family Applications (1)

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Family Cites Families (8)

• 2000
  • 2000-05-11 WO PCT/DE2000/001497 patent/WO2000072378A1/de not_active Application Discontinuation
  • 2000-05-11 EP EP00938553A patent/EP1186031A1/de not_active Withdrawn
  • 2000-05-11 JP JP2000620676A patent/JP2003500858A/ja not_active Withdrawn
  • 2000-05-11 CN CN00807834A patent/CN1352805A/zh active Pending
  • 2000-05-11 KR KR10-2001-7014793A patent/KR100426044B1/ko not_active IP Right Cessation
  • 2000-05-17 TW TW089109430A patent/TW465263B/zh not_active IP Right Cessation

Non-Patent Citations (1)

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