EP1186031A1 - Substrate with at least two metallized polymer bumps for soldered connection to wiring - Google Patents

Substrate with at least two metallized polymer bumps for soldered connection to wiring

Info

Publication number
EP1186031A1
EP1186031A1 EP00938553A EP00938553A EP1186031A1 EP 1186031 A1 EP1186031 A1 EP 1186031A1 EP 00938553 A EP00938553 A EP 00938553A EP 00938553 A EP00938553 A EP 00938553A EP 1186031 A1 EP1186031 A1 EP 1186031A1
Authority
EP
European Patent Office
Prior art keywords
polymer
substrate
bumps
wiring
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00938553A
Other languages
German (de)
French (fr)
Inventor
Jozef Van Puymbroeck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1186031A1 publication Critical patent/EP1186031A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
    • B29L2031/00—Other particular articles
    • B29L2031/34—Electrical apparatus, e.g. sparking plugs or parts thereof
    • B29L2031/3493—Moulded interconnect devices, i.e. moulded articles provided with integrated circuit traces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Integrated circuits are getting more and more connections and are being miniaturized more and more.
  • the difficulties with solder paste application and assembly expected from this increasing miniaturization are to be remedied by new housing shapes, with single, Few or multi-chip modules in the Ball Grid Array Package to be emphasized here (DE-Z productronic 5, 1994, pages 54, 55).
  • These modules are based on a plated-through substrate on which the chips are contacted, for example, via contact wires or by means of flip chip assembly.
  • On the underside of the substrate is the Ball Grid Array (BGA), which is often referred to as a Solder Grid Array or a Solder Bump Array.
  • the ball grid array comprises solder bumps arranged flat on the underside of the substrate, which allow surface mounting on the printed circuit boards or assemblies. Due to the flat arrangement of the solder bumps, large numbers of connections can be realized in a coarse grid of, for example, 1.27 mm.
  • injection molded parts with integrated conductor tracks are used instead of conventional printed circuits.
  • High-quality thermoplastics that are suitable for injection molding three-dimensional substrates are the basis of this technology.
  • Thermoplastics of this type are distinguished from conventional substrate materials for printed circuits by better mechanical, chemical, electrical and environmental properties.
  • SIL injection molded parts with integrated conductor tracks
  • the structuring of a metal layer applied to the injection molded parts takes place by dispensing with the otherwise usual mask technology using a special Target laser structuring process.
  • SIL injection molded parts with integrated conductor tracks
  • the housing support functions simultaneously perform guides and snap connections, while the metallization layer also serves as an electromagnetic shield in addition to the wiring and connection function and ensures good heat dissipation.
  • corresponding via holes are already produced during injection molding.
  • the inner walls of these via holes are then also covered with a metal layer when the injection molded parts are metallized. Further details on the production of three-dimensional injection molded parts with integrated conductor tracks can be found, for example, in DE-A-37 32 249 or EP-A-0 361 192.
  • a smgle chip module is known from O-A-89/00346, in which the injection-molded, three-dimensional substrate made of an electrically insulating polymer bears molded stools on the underside of the substrate during injection molding, which stools can optionally also be arranged flat.
  • An IC chip is arranged on the upper side of this substrate, the connections of which are connected via fine bonding wires to conductor tracks formed on the upper side of the substrate. These conductor tracks are in turn connected via plated-through holes to associated external connections formed on the stools.
  • PSGA polymer stud grid array
  • O-A-96 096 46 which combines the advantages of a ball grid array (BGA) with the advantages of MID technology.
  • BGA ball grid array
  • MID advantages of MID technology.
  • the designation of the new design as a polymer stud grid array (PSGA) was based on the ball grid array
  • an injection-molded, three-dimensional substrate made of an electrically insulating polymer, polymer bumps arranged flat on the underside of the substrate and molded during injection molding,
  • the production of the external connections on the polymer bumps can also be carried out with minimal effort together with the production of the conductor tracks which is customary in the MID technology or the SIL technology. Thanks to the laser fine structuring preferred for SIL technology, the external connections on the polymer bumps with high numbers of connections can be realized in a fine grid.
  • the temperature expansion of the polymer bumps corresponds to the temperature expansion of the substrate and the wiring that receives the module. As a result, a high reliability of the soldered connection is achieved even with frequent temperature fluctuations.
  • the invention specified in claim 1 is based on the problem of ensuring reproducible solder layer thicknesses under the polymer bumps in the case of a substrate with polymer bumps for the solder connection with a wiring.
  • the invention is based on the finding that, by means of a geometry of the polymer bump with at least one elevation, the step or steps formed thereby prevent the molten solder from being pulled up. This results in reproducible solder layer thicknesses under the polymer bumps, which in turn ensure high reliability of the soldered connections. A risk of short circuits due to solder being pulled up can also be excluded.
  • the embodiment according to claim 2 is particularly suitable for the production of substrates with integral polymer bumps by injection molding.
  • the dimensions given in claim 3 for the cylindrical elevations polymer stud grid arrays lead to particularly reliable solder connections.
  • Figure 1 shows a broken section through a
  • FIG. 2 shows a polymer bump of the substrate according to FIG. 1 with the metallization applied thereon and with a conductor path leading away from the polymer bump,
  • FIG. 3 shows the solder connection of the polymer bump shown in FIG. 2 with a wiring
  • FIG. 4 shows a first variant with a two-stage polymer bump
  • FIG. 5 shows a second variant for the polymer bumps with several elevations and arranged on one step
  • Figure 6 shows a third variant for the polymer bumps with an annular elevation.
  • FIG. 1 shows a section through a substrate S, on the underside U of which, to form a polymer stud grid array during injection molding of the substrate, molded polymer bumps PS or Polymer studs are arranged.
  • the slightly conical polymer stools PS are each provided with cylindrical increases E at their lower ends.
  • the diameters of the cylindrical elevations E are dimensioned such that an annular step ST results in each case as a transition to the remaining polymer stool PS.
  • a polymer stool PS m has a diameter D of 400 ⁇ m in its sock area, while the height H is the distance between the underside U of the substrate S and the step ST 400 ⁇ m.
  • the diameter d of the cylindrical elevation E is 160 ⁇ m, while the height h of the cylindrical elevation E is 50 ⁇ m.
  • FIG. 2 shows a polymer stool PS according to FIG. 1 after the laser permanent structuring of a metal layer applied over the entire surface of the substrate S. It can be seen that the polymer stool PS including the cylindrical elevation E is provided with a metallization M and that a conductor path LZ leads away from the polymer stool PS on the underside U of the substrate S.
  • FIG. 3 shows the solder connection of the polymer stool PS shown in FIG. 2 with a wiring V which, in the exemplary embodiment shown, is designed as a printed circuit board LP with connection pads AP arranged on the upper side. It can be clearly seen that the entire solder L remains with the reflow soldering in the area between the step ST and the connection pad AP and is not pulled up laterally up to the conductor lines LZ as in polymer stools without gradation.
  • the geometry of the graduated polymer stool PS ensures reproducible layer thicknesses of the solder L.
  • the polymer stools integrally molded onto a substrate S1 are designated PS.
  • PS1 are an annular elevation El and a cylindrical ge increase E10 formed.
  • the associated ring-shaped steps are designated ST1 and ST10.
  • the polymer bumps integrally molded onto a substrate S2 are designated PS2.
  • a stage ST2 designed as a platform a total of four cylindrical ridges E2 arranged at a distance from one another are provided.
  • the polymer bumps integrally molded onto a substrate S3 are designated PS3.
  • a step ST3 which is also designed as a platform, there is an annular elevation E3.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A substrate (S) with at least two metallized polymer bumps (PS), especially a polymer stud grid array, is configured in such a way that the polymer bumps (PS) have at least one step (ST) and at least one elevation (E). The geometry of the solder bumps (PS) ensures that the soldered connections to the wiring (V) are secure and guarantees reproducible layer thickness for the solder (L).

Description

Beschreibungdescription
Substrat mit mindestens zwei metallisierten Polymerhöckern für die Lötverbindung mit einer VerdrahtungSubstrate with at least two metallized polymer bumps for the solder connection with a wiring
Integrierte Schaltkreise bekommen immer höhere Anschlußzahlen und werden dabei immer weiter miniaturisiert. Die bei dieser zunehmenden Miniaturisierung erwarteten Schwierigkeiten mit Lotpastenauftrag und Bestückung sollen durch neue Gehäusefor- men behoben werden, wobei hier insbesondere Single-, Few- o- der Multi-Chip-Module im Ball Grid Array Package hervorzuheben sind (DE-Z productronic 5, 1994, Seiten 54, 55) . Diese Module basieren auf einem durchkontaktierten Substrat, auf welchem die Chips beispielsweise über Kontaktierdrähte oder mittels Flipchip-Montage kontaktiert sind. An der Unterseite des Substrats befindet sich das Ball Grid Array (BGA) , das häufig auch als Solder Grid Array oder Solder Bump Array bezeichnet wird. Das Ball Grid Array umfaßt auf der Unterseite des Substrats flächig angeordnete Lothöcker, die eine Ober- flächenmontage auf den Leiterplatten oder Baugruppen ermöglichen. Durch die flächige Anordnung der Lothöcker können hohe Anschlußzahlen in einem groben Raster von beispielsweise 1,27 mm realisiert werden.Integrated circuits are getting more and more connections and are being miniaturized more and more. The difficulties with solder paste application and assembly expected from this increasing miniaturization are to be remedied by new housing shapes, with single, Few or multi-chip modules in the Ball Grid Array Package to be emphasized here (DE-Z productronic 5, 1994, pages 54, 55). These modules are based on a plated-through substrate on which the chips are contacted, for example, via contact wires or by means of flip chip assembly. On the underside of the substrate is the Ball Grid Array (BGA), which is often referred to as a Solder Grid Array or a Solder Bump Array. The ball grid array comprises solder bumps arranged flat on the underside of the substrate, which allow surface mounting on the printed circuit boards or assemblies. Due to the flat arrangement of the solder bumps, large numbers of connections can be realized in a coarse grid of, for example, 1.27 mm.
Bei der sog. MID-Technologie (MID = Moulded InterconnectionWith the so-called MID technology (MID = Molded Interconnection
Devices) werden anstelle konventioneller gedruckter Schaltungen Spritzgießteile mit integrierten Leiterzügen verwendet. Hochwertige Thermoplaste, die sich zum Spritzgießen von dreidimensionalen Substraten eignen, sind die Basis dieser Tech- nologie. Derartige Thermoplaste zeichnen sich gegenüber herkömmlichen Substratmaterialien für gedruckte Schaltungen durch bessere mechanische, chemische, elektrische und umwelttechnische Eigenschaften aus. Bei einer speziellen Richtung MID-Technologie, der sog. SIL-Technik (SIL = Spritzgießteile mit integrierten Leiterzügen) , erfolgt die Strukturierung einer auf die Spritzgießteile aufgebrachten Metallschicht unter Verzicht auf die sonst übliche Maskentechnik durch ein spe- zielles Laserstrukturierungsverfahren. In die dreidimensionalen Spritzgießteile mit strukturierter Metallisierung sind dabei mehrere mechanische und elektrische Funktionen integrierbar. Die Gehausetragerfunktionen übernimmt gleichzeitig Fuhrungen und Schnappverbindungen, wahrend die Metallisie- rungsschicht neben der Verdrahtungs- und Verbindungsfunktion auch als elektromagnetische Abschirmung dient und für eine gute Warmeabfuhr sorgt. Zur Herstellung von elektrisch leitenden Querverbindungen zwischen zwei Verdrahtungsanlagen auf einander gegenüberliegenden Oberflachen der Spritzgußteile werden bereits beim Spritzgießen entsprechende Durchkontak- tierungslocher erzeugt. Die Innenwandungen dieser Durchkon- taktierungslocher werden dann beim Metallisieren der Spritzgießteile ebenfalls mit einer Metallschicht überzogen. Weite- re Einzelheiten zur Herstellung von dreidimensionalen Spπtz- gießteilen mit integrierten Leiterzugen gehen beispielsweise aus der DE-A-37 32 249 oder der EP-A-0 361 192 hervor.Devices), injection molded parts with integrated conductor tracks are used instead of conventional printed circuits. High-quality thermoplastics that are suitable for injection molding three-dimensional substrates are the basis of this technology. Thermoplastics of this type are distinguished from conventional substrate materials for printed circuits by better mechanical, chemical, electrical and environmental properties. In the case of a special direction of MID technology, the so-called SIL technology (SIL = injection molded parts with integrated conductor tracks), the structuring of a metal layer applied to the injection molded parts takes place by dispensing with the otherwise usual mask technology using a special Target laser structuring process. Several mechanical and electrical functions can be integrated into the three-dimensional injection molded parts with structured metallization. The housing support functions simultaneously perform guides and snap connections, while the metallization layer also serves as an electromagnetic shield in addition to the wiring and connection function and ensures good heat dissipation. For the production of electrically conductive cross connections between two wiring systems on opposite surfaces of the injection molded parts, corresponding via holes are already produced during injection molding. The inner walls of these via holes are then also covered with a metal layer when the injection molded parts are metallized. Further details on the production of three-dimensional injection molded parts with integrated conductor tracks can be found, for example, in DE-A-37 32 249 or EP-A-0 361 192.
Aus der O-A-89/00346 ist ein Smgle-Chip-Modul bekannt, bei welchem das spritzgegossene, dreidimensionale Substrat aus einem elektrisch isolierenden Polymer auf der Unterseite des Substrats beim Spritzgießen mitgeformte Hocker tragt, die gegebenenfalls auch flachig angeordnet sein können. Auf der 0- berseite dieses Substrats ist ein IC-Chip angeordnet, dessen Anschlüsse über feine Bonddrahte mit auf der Oberseite des Substrats ausgebildeten Leiterbahnen verbunden sind. Diese Leiterbahnen sind ihrerseits über Durchkontaktierungen mit zugeordneten, auf den Hockern gebildeten Außenanschlussen verbunden.A smgle chip module is known from O-A-89/00346, in which the injection-molded, three-dimensional substrate made of an electrically insulating polymer bears molded stools on the underside of the substrate during injection molding, which stools can optionally also be arranged flat. An IC chip is arranged on the upper side of this substrate, the connections of which are connected via fine bonding wires to conductor tracks formed on the upper side of the substrate. These conductor tracks are in turn connected via plated-through holes to associated external connections formed on the stools.
Aus der O-A-96 096 46 ist ein sog. Polymer Stud Grid Array (PSGA) bekannt, welches die Vorteile eines Ball Grid Arrays (BGA) mit den Vorteilen der MID-Technologie vereinigt. Die Bezeichnung der neuen Bauform als Polymer Stud Grid Array (PSGA) erfolgte dabei m Anlehnung an das Ball Grid ArrayA so-called polymer stud grid array (PSGA) is known from O-A-96 096 46, which combines the advantages of a ball grid array (BGA) with the advantages of MID technology. The designation of the new design as a polymer stud grid array (PSGA) was based on the ball grid array
(BGA) , wobei der Begriff "Polymer Stud" auf beim Spritzgießen des Substrats mitgeformte Polymerhocker hinweisen soll. Die neue für Single-, Few- oder Multi-Chip-Module geeignete Bauform umfaßt(BGA), the term "polymer stud" being used to refer to polymer stools molded during the injection molding of the substrate. The new design suitable for single, Few or multi-chip modules
- ein spritzgegossene, dreidimensionales Substrat aus einem elektrisch isolierenden Polymer, - auf der Unterseite des Substrats flächig angeordnete und beim Spritzgießen mitgeformte Polymerhöcker,an injection-molded, three-dimensional substrate made of an electrically insulating polymer, polymer bumps arranged flat on the underside of the substrate and molded during injection molding,
- auf den Polymerhöckern durch eine lösbare Endoberfläche gebildete Außenanschlüsse,- external connections formed on the polymer bumps by a detachable end surface,
- zumindest auf der Unterseite des Substrats ausgebildete Leiterzüge, die die Außenanschlüsse mit Innenanschlüssen verbinden, und- Conductor tracks formed at least on the underside of the substrate, which connect the external connections to internal connections, and
- mindestens einen auf dem Substrat angeordneten Chip, dessen Anschlüsse mit den Innenanschlüssen elektrisch leitend verbunden sind.- At least one chip arranged on the substrate, the connections of which are electrically conductively connected to the internal connections.
Neben der einfachen und kostengünstigen Herstellung der Polymerhöcker beim Spritzgießen des Substrats kann auch die Herstellung der Außenanschlüsse auf den Polymerhöckern mit minimalem Aufwand zusammen mit der bei der MID-Technologie bzw. der SIL-Technik üblichen Herstellung der Leiterzüge vorgenommen werden. Durch die bei der SIL-Technik bevorzugte Laser- feinstrukturierung können die Außenanschlüsse auf den Polymerhöckern mit hohen Anschlußzahlen in einem feinen Raster realisiert werden.In addition to the simple and cost-effective production of the polymer bumps during injection molding of the substrate, the production of the external connections on the polymer bumps can also be carried out with minimal effort together with the production of the conductor tracks which is customary in the MID technology or the SIL technology. Thanks to the laser fine structuring preferred for SIL technology, the external connections on the polymer bumps with high numbers of connections can be realized in a fine grid.
Hervorzuheben ist ferner, daß die Temperaturausdehnung der Polymerhöcker den Temperaturausdehnungen des Substrats und der das Modul aufnehmenden Verdrahtung entspricht. Hierdurch wird auch bei häufigen Temperaturschwankungen eine hohe Zu- verlässigkeit der Lötverbindung erreicht.It should also be emphasized that the temperature expansion of the polymer bumps corresponds to the temperature expansion of the substrate and the wiring that receives the module. As a result, a high reliability of the soldered connection is achieved even with frequent temperature fluctuations.
Aus der US-A-5 477 087 ist es auch bekannt, die elastischen Eigenschaften und das Temperaturverhalten von Polymerhöckern bei der Kontaktierung von elektronischen Komponenten wie z. B. Halbleitern auszunutzen. Hierzu wird auf die Aluminium- Elektroden der elektronischen Komponenten zunächst jeweils eine Barriere-Metallschicht aufgebracht, worauf auf diesen Metallschichten Polymerhöcker ausgebildet werden. Die fertig ausgebildeten Polymerhöcker werden dann mit einer Schicht eines Metalls überzogen, das einen niedrigen Schmelzpunkt besitzt .From US-A-5 477 087 it is also known to describe the elastic properties and the temperature behavior of polymer bumps when contacting electronic components such as. B. exploit semiconductors. For this purpose, a barrier metal layer is first applied to the aluminum electrodes of the electronic components, and then onto this Metal layers of polymer bumps are formed. The finished polymer bumps are then coated with a layer of a metal that has a low melting point.
Werden Polymer Stud Grid Arrays oder andere Komponenten mit metallisierten Polymerhöckern mit Verdrahtungen wie z. B. Leiterplatten durch Reflowlöten verbunden, so besteht die Gefahr, daß das aufgeschmolzene Lot entlang der Metallisierung der Polymerhöcker nach oben gezogen wird. Dieses bei etwa 75% der Polymerhöcker auftretende Phänomen führt dann aber seinerseits zu nicht reproduzierbaren Lotschichtdicken unter den Polymerhöckern und gegebenenfalls zu Kurzschlüssen mit benachbarten Leiterbahnen.Are polymer stud grid arrays or other components with metallized polymer bumps with wiring such. B. circuit boards connected by reflow soldering, there is a risk that the molten solder is pulled up along the metallization of the polymer bumps. However, this phenomenon, which occurs in about 75% of the polymer bumps, in turn leads to non-reproducible solder layer thicknesses under the polymer bumps and, if appropriate, to short circuits with adjacent conductor tracks.
Der im Anspruch 1 angegebenen Erfindung liegt das Problem zugrunde, bei einem Substrat mit Polymerhöckern für die Lötverbindung mit einer Verdrahtung reproduzierbare Lotschichtdicken unter den Polymerhöckern zu gewährleisten.The invention specified in claim 1 is based on the problem of ensuring reproducible solder layer thicknesses under the polymer bumps in the case of a substrate with polymer bumps for the solder connection with a wiring.
Der Erfindung liegt die Erkenntnis zugrunde, daß durch eine Geometrie des Polymerhöckers mit mindestens einer Erhöhung die hierdurch gebildete Stufe oder die hierdurch gebildeten Stufen ein Hochziehen des geschmolzenen Lotes verhindern. Da- mit ergeben sich reproduzierbare Lotschichtdicken unter den Polymerhöckern, die ihrerseits eine hohe Zuverlässigkeit der Lötverbindungen gewährleisten. Eine Gefahr von Kurzschlüssen durch hochgezogenes Lot kann ebenfalls ausgeschlossen werden.The invention is based on the finding that, by means of a geometry of the polymer bump with at least one elevation, the step or steps formed thereby prevent the molten solder from being pulled up. This results in reproducible solder layer thicknesses under the polymer bumps, which in turn ensure high reliability of the soldered connections. A risk of short circuits due to solder being pulled up can also be excluded.
Vorteilhafte Ausgestaltungen der Erfindung sind in den Unteransprüchen angegeben.Advantageous embodiments of the invention are specified in the subclaims.
Die Ausgestaltung nach Anspruch 2 ist insbesondere für die Herstellung von Substraten mit integralen Polymerhöckern durch Spritzgießen geeignet. Dabei haben die im Anspruch 3 angegebenen Abmessungen für die zylinderförmigen Erhöhungen bei Polymer Stud Grid Arrays zu besonders zuverlässigen Lötverbindungen geführt.The embodiment according to claim 2 is particularly suitable for the production of substrates with integral polymer bumps by injection molding. The dimensions given in claim 3 for the cylindrical elevations polymer stud grid arrays lead to particularly reliable solder connections.
Die in den Ansprüchen 4, 5 und 6 angegebenen Varianten für die Geometrie der Polymerhöcker verhindern durch die Stufen ebenfalls ein Hochziehen des Lotes. Damit ergibt sich die Möglichkeit, die Geometrie der Polymerhöcker auf besondere Anwendungsformen abzustimmen.The variants for the geometry of the polymer bumps specified in claims 4, 5 and 6 also prevent the solder from being pulled up by the steps. This makes it possible to adapt the geometry of the polymer bumps to special application forms.
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und werden im folgenden näher beschrieben.Embodiments of the invention are shown in the drawing and are described in more detail below.
Es zeigenShow it
Figur 1 einen abgebrochen dargestellten Schnitt durch einFigure 1 shows a broken section through a
Substrat mit integral angeformten, abgestuften Polymerhöckern,Substrate with integrally molded, graduated polymer bumps,
Figur 2 einen Polymerhöcker des Substrats gemäß Figur 1 mit der darauf aufgebrachten Metallisierung und mit einem vom Polymerhöcker wegführenden Leiterzug,FIG. 2 shows a polymer bump of the substrate according to FIG. 1 with the metallization applied thereon and with a conductor path leading away from the polymer bump,
Figur 3 die Lötverbindung des in Figur 2 dargestellten Polymerhöckers mit einer Verdrahtung,FIG. 3 shows the solder connection of the polymer bump shown in FIG. 2 with a wiring,
Figur 4 eine erste Variante mit einem zweifach abgestuften Polymerhöcker,FIG. 4 shows a first variant with a two-stage polymer bump,
Figur 5 eine zweite Variante für die Polymerhöcker mit mehre- ren auf einer Stufe angeordneten Erhöhungen undFIG. 5 shows a second variant for the polymer bumps with several elevations and arranged on one step
Figur 6 eine dritte Variante für die Polymerhöcker mit einer ringförmigen Erhöhung.Figure 6 shows a third variant for the polymer bumps with an annular elevation.
Figur 1 zeigt einen Schnitt durch ein Substrat S, auf dessen Unterseite U zur Bildung eines Polymer Stud Grid Arrays beim Spritzgießen des Substrats mitgeformte Polymerhöcker PS bzw. Polymer Studs angeordnet sind. Es ist erkennbar, daß die leicht konisch ausgebildeten Polymerhocker PS an ihrem unteren Ende jeweils mit zylmderforangen Erhöhungen E versehen sind. Die Durchmesser der zylinderformigen Erhöhungen E sind derart bemessen, daß sich jeweils als Übergang zum restlichen Polymerhocker PS eine ringförmige Stufe ST ergibt. Im dargestellten Ausfuhrungsbeispiel weist ein Polymerhocker PS m seinem Sockeibereich einen Durchmesser D von 400 μm auf, wahrend die Hohe H als Abstand zwischen der Unterseite U des Substrats S und der Stufe ST 400 um betragt. Der Durchmesser d der zylindrischen Erhöhung E betragt 160 μm, wahrend die Hohe h der zylindrischen Erhöhung E 50 μm betragt.FIG. 1 shows a section through a substrate S, on the underside U of which, to form a polymer stud grid array during injection molding of the substrate, molded polymer bumps PS or Polymer studs are arranged. It can be seen that the slightly conical polymer stools PS are each provided with cylindrical increases E at their lower ends. The diameters of the cylindrical elevations E are dimensioned such that an annular step ST results in each case as a transition to the remaining polymer stool PS. In the exemplary embodiment shown, a polymer stool PS m has a diameter D of 400 μm in its sock area, while the height H is the distance between the underside U of the substrate S and the step ST 400 μm. The diameter d of the cylindrical elevation E is 160 μm, while the height h of the cylindrical elevation E is 50 μm.
Figur 2 zeigt einen Polymerhocker PS gemäß Figur 1 nach der Laserfemststrukturierung einer ganzflachig auf das Substrat S aufgebrachten Metallschicht . Es ist zu erkennen, daß der Polymerhocker PS einschließlich der zylindrischen Erhöhung E mit einer Metallisierung M versehen ist und daß von dem Polymerhocker PS auf der Unterseite U des Substrats S ein Leiter- zug LZ wegfuhrt.FIG. 2 shows a polymer stool PS according to FIG. 1 after the laser permanent structuring of a metal layer applied over the entire surface of the substrate S. It can be seen that the polymer stool PS including the cylindrical elevation E is provided with a metallization M and that a conductor path LZ leads away from the polymer stool PS on the underside U of the substrate S.
Figur 3 zeigt die Lotverbindung des in Figur 2 dargestellten Polymerhockers PS mit einer Verdrahtung V, die im dargestellten Ausfuhrungsbeispiel als Leiterplatte LP mit auf der Ober- seite angeordneten Anschluß-Pads AP ausgebildet ist. Es ist deutlich zu erkennen, daß das gesamte Lot L beim Reflowloten im Bereich zwischen der Stufe ST und dem Anschluß-Pad AP verbleibt und nicht wie bei Polymerhockern ohne Abstufung seitlich bis zu den Leiterzugen LZ hochgezogen wird. Durch die Geometrie der abgestuften Polymerhocker PS sind somit reproduzierbare Schichtdicken des Lotes L gewahrleistet.FIG. 3 shows the solder connection of the polymer stool PS shown in FIG. 2 with a wiring V which, in the exemplary embodiment shown, is designed as a printed circuit board LP with connection pads AP arranged on the upper side. It can be clearly seen that the entire solder L remains with the reflow soldering in the area between the step ST and the connection pad AP and is not pulled up laterally up to the conductor lines LZ as in polymer stools without gradation. The geometry of the graduated polymer stool PS ensures reproducible layer thicknesses of the solder L.
Bei der in Figur 4 dargestellten ersten Variante sind die an ein Substrat Sl integral angeformten Polymerhocker mit PS be- zeichnet. Durch eine zweifache Abstufung der PolymerhockerIn the first variant shown in FIG. 4, the polymer stools integrally molded onto a substrate S1 are designated PS. With a double gradation of the polymer stool
PS1 sind eine ringförmige Erhöhung El und eine zylinderformi- ge Erhöhung E10 gebildet. Die zugehörigen ringförmigen Stufen sind mit ST1 bzw. mit ST10 bezeichnet.PS1 are an annular elevation El and a cylindrical ge increase E10 formed. The associated ring-shaped steps are designated ST1 and ST10.
Bei der in Figur 5 dargestellten zweiten Variante sind die an ein Substrat S2 integral angeformten Polymerhöcker mit PS2 bezeichnet. Auf einer als Plattform ausgebildeten Stufe ST2 sind insgesamt vier im Abstand zueinander angeordnete zylin- derförmige Erhöhungen E2 vorgesehen.In the second variant shown in FIG. 5, the polymer bumps integrally molded onto a substrate S2 are designated PS2. On a stage ST2 designed as a platform, a total of four cylindrical ridges E2 arranged at a distance from one another are provided.
Bei der in Figur 6 dargestellten dritten Variante sind die an ein Substrat S3 integral angeformten Polymerhöcker mit PS3 bezeichnet. Auf einer ebenfalls als Plattform ausgebildeten Stufe ST3 befindet sich hier eine ringförmige Erhöhung E3.In the third variant shown in FIG. 6, the polymer bumps integrally molded onto a substrate S3 are designated PS3. On a step ST3, which is also designed as a platform, there is an annular elevation E3.
Neben den in den Figuren 1 bis 6 dargestellten leicht kegelstumpfförmigen Polymerhöckern können auch andere Querschnittsformen der Polymerhöcker oder der Erhöhungen verwendet werden. Von entscheidender Bedeutung ist jedoch auch hier die Ausbildung mindestens einer Stufe, die ein seitliches Hochziehen des Lotes beim Reflowlöten verhindert. In addition to the slightly frustoconical polymer bumps shown in FIGS. 1 to 6, other cross-sectional shapes of the polymer bumps or the elevations can also be used. Of crucial importance here, however, is the formation of at least one step, which prevents the solder from being pulled up sideways during reflow soldering.

Claims

Patentansprüche claims
1. Substrat (S; Sl; S2; S3) mit mindestens zwei metallisierten Polymerhockern (PS; PS1; PS2; PS3) für die Lotverbindung mit einer Verdrahtung (V) und mit von den Polymerhockern (PS; PS1; PS2; PS3) auf der Unterseite (U) des Substrats (S; Sl; S2; S3) wegführenden Leiterzugen (LZ) , wobei die Polymerhocker (PS; PS1;PS2; PS3) mindestens eine Stufe (ST; ST1, ST10; ST2; ST3) zur Bildung mindestens einer Erhöhung (E; El; E10; E2; E3) aufweisen.1. Substrate (S; Sl; S2; S3) with at least two metallized polymer stools (PS; PS1; PS2; PS3) for the solder connection with a wiring (V) and with the polymer stools (PS; PS1; PS2; PS3) the underside (U) of the substrate (S; Sl; S2; S3) leading conductor lines (LZ), wherein the polymer stool (PS; PS1; PS2; PS3) at least one step (ST; ST1, ST10; ST2; ST3) for formation have at least one increase (E; El; E10; E2; E3).
2. Substrat (S) nach Anspruch gekennzeichnet durch eine konzentrisch zum Polymerhocker (PS) angeordnete, zylm- derformige Erhöhung (E) .2. substrate (S) according to claim characterized by a concentric to the polymer stool (PS) arranged, zylm- shaped increase (E).
3. Substrat (S) nach Anspruch 2, dadurch gekennzeichnet, daß die zylmderformige Erhöhung (E) einen Durchmesser (d) zwischen 100 μm und 300 μm und eine Hohe (h) zwischen 25 μm und 250 μm aufweist.3. Substrate (S) according to claim 2, characterized in that the cylindrical increase (E) has a diameter (d) between 100 microns and 300 microns and a height (h) between 25 microns and 250 microns.
4. Substrat (Sl) nach Anspruch 1, dadurch gekennzeichnet, daß Polymerhocker (PS1) mit zwei Erhöhungen (El; E10) und zwei Stufen (ST1; ST10) vorgesehen sind.4. substrate (Sl) according to claim 1, characterized in that polymer stool (PS1) with two elevations (El; E10) and two stages (ST1; ST10) are provided.
5. Substrat (S2) nach Anspruch 1, dadurch gekennzeichnet, daß Polymerhocker (PS2) mit mehreren auf einer Stufe (ST2) im Abstand zueinander angeordneten Erhöhungen (E2) vorgesehen sind.5. Substrate (S2) according to claim 1, characterized in that polymer stools (PS2) are provided with several on a step (ST2) spaced elevations (E2).
6. Substrat (S3) nach Anspruch 1, dadurch gekennzeichnet, daß Polymerhocker (PS3) mit auf einer Stufe (ST3) angeordneten, ringförmigen Erhöhungen (E3) vorgesehen sind. 6. substrate (S3) according to claim 1, characterized in that polymer stool (PS3) with on a step (ST3) arranged, annular increases (E3) are provided.
EP00938553A 1999-05-20 2000-05-11 Substrate with at least two metallized polymer bumps for soldered connection to wiring Withdrawn EP1186031A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19923247 1999-05-20
DE19923247 1999-05-20
PCT/DE2000/001497 WO2000072378A1 (en) 1999-05-20 2000-05-11 Substrate with at least two metallized polymer bumps for soldered connection to wiring

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EP1186031A1 true EP1186031A1 (en) 2002-03-13

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JP (1) JP2003500858A (en)
KR (1) KR100426044B1 (en)
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DE10145348C1 (en) * 2001-09-14 2003-03-27 Siemens Dematic Ag Intermediate carrier for electronic component has suction used for removal of excess solder at foot of contact projections formed integral with plastics carrier body
DE10217698B4 (en) * 2002-04-20 2008-04-24 Festo Ag & Co. Electrical switching arrangement with an injection-molded circuit carrier
DE10217700A1 (en) * 2002-04-20 2003-11-06 Festo Ag & Co Injection-molded circuit board, carries ramped tracks terminating at studs with laser-beam activated upper surfaces forming flip-chip connections
DE10227305A1 (en) * 2002-06-19 2003-09-04 Siemens Dematic Ag Electrical multiple layer component module used in polymer stud grid array technology comprises a second three-dimensional substrate arranged on first three-dimensional substrate with intermediate connections connected to contacts
JP2005353740A (en) 2004-06-09 2005-12-22 Toshiba Corp Semiconductor element and semiconductor device
DE102015005205A1 (en) * 2015-04-23 2016-10-27 Multiple Dimensions Ag Carrier body for receiving electronic circuits

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JPH0832183A (en) * 1994-05-12 1996-02-02 Furukawa Electric Co Ltd:The Semiconductor chip package
EP0971405A3 (en) * 1994-09-23 2000-05-10 Siemens S.A. Method for manufacturing a substrate for a polymer stud grid array
JPH0969401A (en) * 1995-08-31 1997-03-11 Oki Electric Ind Co Ltd Surface mounting component
US5736790A (en) * 1995-09-21 1998-04-07 Kabushiki Kaisha Toshiba Semiconductor chip, package and semiconductor device
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JP2003500858A (en) 2003-01-07
CN1352805A (en) 2002-06-05

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