Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/70—Bipolar devices
  • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
  • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
  • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
  • H01L29/7395—Vertical transistors, e.g. vertical IGBT
  • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
  • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/02—Bonding areas; Manufacturing methods related thereto
  • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
  • H01L2224/0601—Structure
  • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
  • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
  • H01L2224/13001—Core members of the bump connector
  • H01L2224/1302—Disposition
  • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
  • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/13—Discrete devices, e.g. 3 terminal devices
  • H01L2924/1304—Transistor
  • H01L2924/1305—Bipolar Junction Transistor [BJT]
  • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

• the gate signal for IGBT chips with a minimum surface area of 0.2 cm 2 is first distributed over the periphery of the chips with the aid of a gate runner (see DE 196 12 516 AI). Narrow stripes (gate fingers) then lead the signal inside the chip (clearly seen in EP 0 755 076 A2). Both the gate runner and the gate finger are made of an AI metallization. It is also possible to start the signal from a - 2 -
• the design rule usually used states that the distance x of the gate fingers must meet the following condition.
• gate fingers require complex and expensive solder metallization, if cathode-side soldering is required, and place high demands on the passivation. Passivation weaknesses lead to gate-emitter short circuits that manifest themselves as early failures and can only be detected with complex burn-in tests. Similar problems occur with pressure contacting.
• the object of the invention is to provide an IGBT that can be manufactured in a simple manner and nevertheless switches on homogeneously. This object is solved by the features of the independent claims. - 3 -
• the gate current in the IGBT chip is passed on directly from the gate connection via the polysilicon layers of the gate electrodes to the IGBT emity cells without the use of gate fingers.
• the gate signal can be supplied to the IGBT chip via a gate connection (gate pad) arranged in a corner or, according to a second exemplary embodiment, via a central gate connection.
• the invention thus turns away diametrically from the prevailing view that, starting from a certain chip size, homogeneous switching on can only be achieved using gate fingers. Rather, the inventors recognized for the first time that different design rules apply to homogeneous switching off of an IGBT than to MOS transistors. In particular, the inventors have recognized that maximum power loss density is always homogeneous when the plasma distribution is still homogeneous.
• a bipolar component behaves fundamentally different from a unipolar element such as a MOS transistor, in particular when the MOS current is no longer sufficient to maintain the external current. After this point in time there is a transition from bipolar current to pure hole current, associated with clearing the main junction. Once this process is complete, the full current is carried through holes and the space charge zone builds up.
• the plasma distribution is still quite homogeneous laterally. Therefore, the very inhomogeneous current distribution is quickly homogenized. At the time of the maximum power loss, the current distribution is almost homogeneous. Therefore, the safe operating area is not reduced and the switch-off energy is hardly changed. As a consequence, IGBTs can be built without a gate finger, even if a minimum area of 0.2 cm 2 that applies to gate fingerless MOS transistors is exceeded.
• FIGS. 2a and 2b show an exemplary embodiment of an IGBT chip 1 according to the invention.
• a first main connection 3 is shown, which is connected by an insulation - 4 -
• gate frame 8 is surrounded.
• the gate frame 8 is connected to a gate connection 4, of which e.g. Can lead bond wires to the corresponding housing connection.
• gate fingers 6 are provided in the prior art according to FIGS. 1 a and 1 b, which distribute the gate signal from the gate connection 4 over the chip surface.
• Figure la A plan view of an IGBT chip according to the prior art
• Figure lb A perspective view of part of the IGBT chip according to Figure la
• Figure 2a A plan view of an IGBT chip according to the invention according to a first embodiment
• Figure 2b A perspective view of part of the IGBT chip according to Figure 2a
• Figure 3 A plan view of an IGBT chip according to the invention in a second embodiment
• Figure 4 A section through an IGBT chip according to the invention
• Figure 5 A plan view of a polysilicon layer.
• FIGS. 1 a and 1 b show a gate fingerless IGBT chip 1 according to the invention from above or in perspective with a first, visible skin connector 3 and a second, not shown main connector and a gate connector 4, which in the embodiment shown in Figures 2a and 2b on Edge, in particular in a corner of the IGBT chip 1 is arranged.
• FIGS. 1 a and 1 b which represent the prior art, no gate fingers 6 are provided, but the gate signal is distributed from the gate connection 4 via a gate frame 8 over the periphery.
• the gate frame 8 is also in direct operative connection with the gate electrodes 5. It preferably has a resistance of less than 5 ohms.
• the first main connection 3 is thus formed by a surface which is convex except for a recess for the gate connection 4, wherein in the case of the embodiment according to FIGS. 2a and 2b its convex surface area is surrounded by the gate frame 8. If a plurality of gate connections 4 are present, the essentially convex surface of the first main connection has a corresponding number of recesses. Insulation 7 is provided between the large-area first main connection (shown as metallization), which is formed in particular by the cathode of the IGBT, and the gate connection 4 and the gate frame 8. According to the invention, the gate connection 4 or the gate frame 8 is connected directly to the polysilicon layers of the gate electrodes 5 of the IGBT, ie without interposing gate fingers.
• the gate connection 4 can also be arranged centrally on the IGBT chip 1.
• Figure 3 shows this embodiment. Again, the gate connection 4 is surrounded by insulation 7, which decouples it from the main connection 3.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Ceramic Engineering (AREA)
• Thyristors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)

Applications Claiming Priority (5)

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• 1999
  • 1999-02-25 WO PCT/CH1999/000086 patent/WO1999044240A1/de active Application Filing
  • 1999-02-25 JP JP2000533906A patent/JP2002505525A/ja active Pending
  • 1999-02-25 US US09/622,839 patent/US6576936B1/en not_active Expired - Lifetime
  • 1999-02-25 CN CNB998033847A patent/CN1183603C/zh not_active Expired - Lifetime
  • 1999-02-25 EP EP99904672A patent/EP1060517A1/de not_active Ceased

Non-Patent Citations (1)

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