GB2268332A - Power transistor with reduced gate resistance and inductance - Google Patents

Power transistor with reduced gate resistance and inductance Download PDF

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Publication number
GB2268332A
GB2268332A GB9312934A GB9312934A GB2268332A GB 2268332 A GB2268332 A GB 2268332A GB 9312934 A GB9312934 A GB 9312934A GB 9312934 A GB9312934 A GB 9312934A GB 2268332 A GB2268332 A GB 2268332A
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Prior art keywords
gate
chip
fet
pads
mosfet
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GB9312934A
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GB9312934D0 (en
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Rayette Ann Fisher
William Andrew Hennessy
Charles Steven Korman
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General Electric Co
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General Electric Co
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Publication of GB9312934D0 publication Critical patent/GB9312934D0/en
Publication of GB2268332A publication Critical patent/GB2268332A/en
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The gate resistance and inductance of power transistors, such as MOSFETS, on a chip are substantially reduced and evenly distributed among the individual MOSFET cells of the chip. The gate terminal of a power MOSFET includes a plurality of gate pads coupled to each other by a gate runner (26) along the periphery of the chip; the number and locations of the gate pads (22) depending on predetermined values of gate resistance, gate inductance, and on-state resistance of the MOSFET, As a result, resistive and inductive losses are reduced; gating of the individual MOSFET cells is substantially synchronized; and device gain is improved. Hence, device efficiency is improved by reducing the time required to reach the minimum on-state resistance thereof. The invention also applies to the base pads of bipolar transistors. <IMAGE>

Description

IMPROVED DISCRETE POWER TRANSISTOR WITH REDUCED GATE RESISTANCE AND INDUCTANCE Field of the Invention The present invention relates generally to discrete power transistors and, more particularly, to an improved discrete power field effect transistor (FET), e.g., a metal oxide semiconductor field effect transistor (MOSFET), having reduced gate resistance and inductance, which is suitable for high-frequency resonant and square-wave circuit applications.
Backaround of the Invention A discrete power MOSFET chip typically includes a plurality of parallel-connected MOSFET cells with a gate runner, e.g., of aluminum, along the periphery of the chip. The gate resistance of such a MOSFET chip includes the resistances of: the internal gate element array or "web" which modulates the conductive characteristics of each MOSFET cell; the peripheral gate runner; wire bond contacts and leads; and external device leads. The farther away a particular MOSFET cell on the chip is from the gate runner, the longer, more resistive and inductive the current path is thereto, resulting in gate turn-on signal propagation delays to individual MOSFET cells, therefore increasing the time required for the device to reach its minimum on-state resistance. As the operating frequency increases, these effects become even more significant.Accordingly, it is desirable to reduce the resistance and inductance of the gate interconnect of a discrete power MOSFET chip in order to achieve high efficiency at high frequencies, thus making such chips suitable for high-frequency resonant and square-wave drive applications.
Summary of the Invention The present invention is set forth in claim 1.
The cumulative gate resistance and inductance #f an improved discrete power transistor (e.g., a MOSFET) according to the present invention are substantially reduced and evenly distributed among the individual MOSFET cells of the chip. The gate terminal of the improved MOSFET comprises a plurality of gate pads coupled to each other by a gate runner, e.g., aluminum, along the periphery of the chip; the number and locations of the gate pads depending on predetermined required values of gate resistance, gate inductance, and on-state resistance of the MOSFET. As a result, resistive and inductive losses due to gate parasitics are reduced, and gating of the individual MOSFET cells is substantially synchronized. According to one embodiment, the power MOSFET chip is rectangular with four gate pads located in the respective corners of the chip.
Brief Descri#tion of the Drawings The features and advantages of the present invention will become apparent from the following detailed description of the invention when read with the accompanying drawings in which: Figure 1 schematically illustrates a conventional discrete power MOSFET chip; Figure 2 schematically illustrates one embodiment of an improved discrete power MOSFET according to the present invention; and Figure 3 schematically illustrates an alternative embodiment of the MOSFET of Figure 2.
Detailed Description of the Invention Figure 1 schematically illustrates a conventional discrete power MOSFET chip 10. (Although the invention is described herein with reference to a MOSFET, it is to be understood that the principles of the present invention apply to other suitable types of transistors, such as, for example, bipolar junction transistors (BJT's) or other types of FET's.) MOSFET chip 10 includes a layer of gate polysilicon, metal, or metal silicide 12 with a plurality of individual MOSFET cells 14 fabricated therein. Typically, the density of cells 14 is on the order of millions per square inch. A gate runner 16, typically of aluminum, is shown as being disposed along the outer periphery of the chip.However, the configuration of Figure 1 is given by way of example only as other MOSFET configurations have the gate runner in, or partially in, the interior of the chip. The gate terminals of the individual MOSFET cells are each connected in parallel via the gate element "web" and gate runner 16 which is, in turn, connected to a gate pad 18.
Disadvantageously, the farther away a particular MOSFET cell is located from gate pad 18, the longer the gate interconnect path length thereto.
Resistance and inductance increase with increased gate interconnect path length, resulting in a lack of gate signal synchronization, longer turn-on times, and lower device efficiency.
Figure 2 schematically illustrates an improved discrete power MOSFET 20 according to one embodiment of the present invention including a plurality of gate pads 22 connected together by a single gate runner 26 illustrated as being situated along the entire periphery of the chip. An exemplary gate runner 26 is on the order of, for example, 10-15 Fm wide, and each gate pad 22 is at least, for example, 16 mil2, assuming a wire bond fabricated with a 1 mil diameter wire is used. The gate terminal of each MOSFET cell 14 is connected in parallel, via the gate element "web", to gate runner 26. As a result, the gate resistance and inductance are significantly reduced and more evenly distributed, resulting in lower losses and improved MOSFET switching synchronization.Furthermore, the MOSFET reaches its minimum on-state resistance more quickly, therefore increasing device efficiency. (The device on-state resistance is defined herein as the total resistance between the drain and source terminals with the device in its on-state condition.) The mean path-length from gate pad 22 to individual cell 14 is reduced if more gate pads are employed and appropriately distributed along the gate runner. However, since each gate pad requires sufficient area to wire bond or otherwise connect the gate terminals thereto, adding multiple gate pads means fewer cells for the same size chip, resulting in an increased on-state resistance for the device. The optimum number of gate pads for a particular application thus depends on a compromise between predetermined values of gate resistance, gate inductance, and on-state resistance.Alternatively, the chip could be made larger to accommodate extra gate pad area, but manufacturing yield would be reduced thereby.
Figure 3 illustrates an alternative embodiment of a MOSFET 30 according to the present invention wherein the number of gate pads is infinite; i.e., the gate runner 36 is relatively wide and the gate terminal of the device is nearly continuously connected to the gate runner by vias 37. The device of Figure 3 may be implemented, for example, using high density interconnect (HDI) technology, such as described in commonly assigned U.S. Pat; No.
4,960,613, issued Oct. 2, 1990 and incorporated by reference herein#. In a suitable HDI implementation of the device of Figure 3, the gate runner, including extensions 39 within the interior of the device, is on the order of, for example, 2 mils wide.
The advantages of lower resistance and inductance through the use of multiple gate (or base) pads in accordance with the present invention are realized in other types of transistors, such as, for example, BJT's or other types of FET's. In particular, in BJT's, since the base and emitter resistance are inversely proportional to the gain, the use of multiple gate pads in accordance with the present invention has the effect of increasing the gain.
While the preferred embodiments of the present invention have been shown and described herein, it will be obvious that such embodiments are provided by way of example only. Numerous variations, changes and substitutions will occur to those of skill in the art without departing from the invention herein. Accordingly, it is intended that the invention be limited only by the scope of the appended claims.

Claims (8)

CLAIMS:
1. An improved discrete power transistor of the type comprising a plurality of parallel-coupled transistor cells in a silicon chip, said transistor having gate or base, drain or collector, and source or emitter terminals, wherein the improvement comprises: said gate or base terminal comprising a plurality of gate or base pads coupled to each other by a single gate or base runner, the number and locations of said gate or base pads depending on predetermined values of gate or base resistance, gate or base inductance, and on-state resistance of said transistor.
2. The transistor of claim 1 wherein said transistor is a FET.
3. The FET of claim 2 wherein said gate runner is situated along the periphery of said chip.
4. The FET of claim 3 wherein said chip is substantially rectangular, said FET having four gate pads, each of said gate pads being located in a corner of said chip.
5. The FET of claim 2, comprising a MOSFET.
6. The FET of claim 2 wherein the number of said gate pads approaches an infinite number of point locations along said, gate runner.
7. The FET of claim 6 wherein said FET is implemented in a high density interconnect structure.
8. A power transistor as claimed in claim 1 and si#stantiaily as described with refer#oe to tI# dr#dngs.
GB9312934A 1992-06-25 1993-06-23 Power transistor with reduced gate resistance and inductance Withdrawn GB2268332A (en)

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US90431092A 1992-06-25 1992-06-25

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999044240A1 (en) * 1998-02-27 1999-09-02 Asea Brown Boveri Ag Bipolar transistor with an insulated gate electrode
DE10053986A1 (en) * 2000-10-31 2002-05-08 Forschungszentrum Juelich Gmbh Introducing and removing hydrogen using an electrically contacted proton conductor, comprises applying a current to the conductor so that protons are generated at an anode and recombining the protons at a cathode to form hydrogen
EP1460689A2 (en) * 2003-03-17 2004-09-22 Analog Power Intellectual Properties Limited Electronic devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109994445B (en) * 2017-12-29 2023-08-22 三垦电气株式会社 Semiconductor element and semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670219A (en) * 1970-12-07 1972-06-13 Motorola Inc Current limiting transistor
US3808474A (en) * 1970-10-29 1974-04-30 Texas Instruments Inc Semiconductor devices
GB1482337A (en) * 1974-10-29 1977-08-10 Raytheon Co Field effect transistor device
EP0041844A2 (en) * 1980-06-10 1981-12-16 Fujitsu Limited Semiconductor integrated circuit devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808474A (en) * 1970-10-29 1974-04-30 Texas Instruments Inc Semiconductor devices
US3670219A (en) * 1970-12-07 1972-06-13 Motorola Inc Current limiting transistor
GB1482337A (en) * 1974-10-29 1977-08-10 Raytheon Co Field effect transistor device
EP0041844A2 (en) * 1980-06-10 1981-12-16 Fujitsu Limited Semiconductor integrated circuit devices

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999044240A1 (en) * 1998-02-27 1999-09-02 Asea Brown Boveri Ag Bipolar transistor with an insulated gate electrode
US6576936B1 (en) 1998-02-27 2003-06-10 Abb (Schweiz) Ag Bipolar transistor with an insulated gate electrode
DE10053986A1 (en) * 2000-10-31 2002-05-08 Forschungszentrum Juelich Gmbh Introducing and removing hydrogen using an electrically contacted proton conductor, comprises applying a current to the conductor so that protons are generated at an anode and recombining the protons at a cathode to form hydrogen
EP1460689A2 (en) * 2003-03-17 2004-09-22 Analog Power Intellectual Properties Limited Electronic devices
EP1460689A3 (en) * 2003-03-17 2005-07-20 Analog Power Intellectual Properties Limited Electronic devices
US6963140B2 (en) 2003-03-17 2005-11-08 Analog Power Intellectual Properties Transistor having multiple gate pads

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