EP1060517A1 - Bipolar transistor with an insulated gate electrode - Google Patents

Bipolar transistor with an insulated gate electrode

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Publication number
EP1060517A1
EP1060517A1 EP99904672A EP99904672A EP1060517A1 EP 1060517 A1 EP1060517 A1 EP 1060517A1 EP 99904672 A EP99904672 A EP 99904672A EP 99904672 A EP99904672 A EP 99904672A EP 1060517 A1 EP1060517 A1 EP 1060517A1
Authority
EP
European Patent Office
Prior art keywords
gate
connection
igbt
bipolar transistor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99904672A
Other languages
German (de)
French (fr)
Inventor
Friedhelm Bauer
Hans-Rudolf Zeller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Schweiz AG
Original Assignee
ABB Semiconductors Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19808154A external-priority patent/DE19808154A1/en
Priority claimed from DE1998123170 external-priority patent/DE19823170A1/en
Application filed by ABB Semiconductors Ltd filed Critical ABB Semiconductors Ltd
Publication of EP1060517A1 publication Critical patent/EP1060517A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the gate signal for IGBT chips with a minimum surface area of 0.2 cm 2 is first distributed over the periphery of the chips with the aid of a gate runner (see DE 196 12 516 AI). Narrow stripes (gate fingers) then lead the signal inside the chip (clearly seen in EP 0 755 076 A2). Both the gate runner and the gate finger are made of an AI metallization. It is also possible to start the signal from a - 2 -
  • the design rule usually used states that the distance x of the gate fingers must meet the following condition.
  • gate fingers require complex and expensive solder metallization, if cathode-side soldering is required, and place high demands on the passivation. Passivation weaknesses lead to gate-emitter short circuits that manifest themselves as early failures and can only be detected with complex burn-in tests. Similar problems occur with pressure contacting.
  • the object of the invention is to provide an IGBT that can be manufactured in a simple manner and nevertheless switches on homogeneously. This object is solved by the features of the independent claims. - 3 -
  • the gate current in the IGBT chip is passed on directly from the gate connection via the polysilicon layers of the gate electrodes to the IGBT emity cells without the use of gate fingers.
  • the gate signal can be supplied to the IGBT chip via a gate connection (gate pad) arranged in a corner or, according to a second exemplary embodiment, via a central gate connection.
  • the invention thus turns away diametrically from the prevailing view that, starting from a certain chip size, homogeneous switching on can only be achieved using gate fingers. Rather, the inventors recognized for the first time that different design rules apply to homogeneous switching off of an IGBT than to MOS transistors. In particular, the inventors have recognized that maximum power loss density is always homogeneous when the plasma distribution is still homogeneous.
  • a bipolar component behaves fundamentally different from a unipolar element such as a MOS transistor, in particular when the MOS current is no longer sufficient to maintain the external current. After this point in time there is a transition from bipolar current to pure hole current, associated with clearing the main junction. Once this process is complete, the full current is carried through holes and the space charge zone builds up.
  • the plasma distribution is still quite homogeneous laterally. Therefore, the very inhomogeneous current distribution is quickly homogenized. At the time of the maximum power loss, the current distribution is almost homogeneous. Therefore, the safe operating area is not reduced and the switch-off energy is hardly changed. As a consequence, IGBTs can be built without a gate finger, even if a minimum area of 0.2 cm 2 that applies to gate fingerless MOS transistors is exceeded.
  • FIGS. 2a and 2b show an exemplary embodiment of an IGBT chip 1 according to the invention.
  • a first main connection 3 is shown, which is connected by an insulation - 4 -
  • gate frame 8 is surrounded.
  • the gate frame 8 is connected to a gate connection 4, of which e.g. Can lead bond wires to the corresponding housing connection.
  • gate fingers 6 are provided in the prior art according to FIGS. 1 a and 1 b, which distribute the gate signal from the gate connection 4 over the chip surface.
  • Figure la A plan view of an IGBT chip according to the prior art
  • Figure lb A perspective view of part of the IGBT chip according to Figure la
  • Figure 2a A plan view of an IGBT chip according to the invention according to a first embodiment
  • Figure 2b A perspective view of part of the IGBT chip according to Figure 2a
  • Figure 3 A plan view of an IGBT chip according to the invention in a second embodiment
  • Figure 4 A section through an IGBT chip according to the invention
  • Figure 5 A plan view of a polysilicon layer.
  • FIGS. 1 a and 1 b show a gate fingerless IGBT chip 1 according to the invention from above or in perspective with a first, visible skin connector 3 and a second, not shown main connector and a gate connector 4, which in the embodiment shown in Figures 2a and 2b on Edge, in particular in a corner of the IGBT chip 1 is arranged.
  • FIGS. 1 a and 1 b which represent the prior art, no gate fingers 6 are provided, but the gate signal is distributed from the gate connection 4 via a gate frame 8 over the periphery.
  • the gate frame 8 is also in direct operative connection with the gate electrodes 5. It preferably has a resistance of less than 5 ohms.
  • the first main connection 3 is thus formed by a surface which is convex except for a recess for the gate connection 4, wherein in the case of the embodiment according to FIGS. 2a and 2b its convex surface area is surrounded by the gate frame 8. If a plurality of gate connections 4 are present, the essentially convex surface of the first main connection has a corresponding number of recesses. Insulation 7 is provided between the large-area first main connection (shown as metallization), which is formed in particular by the cathode of the IGBT, and the gate connection 4 and the gate frame 8. According to the invention, the gate connection 4 or the gate frame 8 is connected directly to the polysilicon layers of the gate electrodes 5 of the IGBT, ie without interposing gate fingers.
  • the gate connection 4 can also be arranged centrally on the IGBT chip 1.
  • Figure 3 shows this embodiment. Again, the gate connection 4 is surrounded by insulation 7, which decouples it from the main connection 3.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to an IGBT (Insulated Gate Bipolar Transistor) which is simple to produce but still switches on homogeneously. To this end, the inventive transistor does not have any gate fingers and starting from the gate terminal, the gate current in the IGBT chip is transmitted directly to the IGBT unit cells via the polysilicon layers of the gate electrodes.

Description

B E S C H R E I B U N G DESCRIPTION
BIPOLARTRANSISTOR MIT ISOLIERTER GATEELEKTRODEBIPOLAR TRANSISTOR WITH INSULATED GATE ELECTRODE
Technisches GebietTechnical field
Die Erfindung bezieht sich auf das Gebiet der Halbleitertechnologie. Sie betrifft insbesondere einen IGBT (Insulated Gate Bipolar Transistor) nach dem Oberbe- griff des ersten Anspruchs. Ein solcher IGBT ist beispielsweise aus der Deutschen Offenlegungsschrift DE 196 12 516 AI bekannt.The invention relates to the field of semiconductor technology. It relates in particular to an IGBT (Insulated Gate Bipolar Transistor) according to the preamble of the first claim. Such an IGBT is known, for example, from German Offenlegungsschrift DE 196 12 516 AI.
Stand der TechnikState of the art
In IGBTs nach dem Stand der Technik wird das Gate Signal bei IGBT-Chips mit einer Mindestoberfläche von 0.2 cm2 zunächst mit Hilfe eines Gate Runners über die Peripherie der Chips verteilt (siehe DE 196 12 516 AI). Schmale Streifen (Gatefinger) führen dann das Signal ins Innere des Chips (deutlich zu sehen in EP 0 755 076 A2). Sowohl der Gate Runner, wie auch die Gate Finger bestehen aus einer AI Metallisierung. Es ist auch möglich, das Signal ausgehend von ei- - 2 -In IGBTs according to the prior art, the gate signal for IGBT chips with a minimum surface area of 0.2 cm 2 is first distributed over the periphery of the chips with the aid of a gate runner (see DE 196 12 516 AI). Narrow stripes (gate fingers) then lead the signal inside the chip (clearly seen in EP 0 755 076 A2). Both the gate runner and the gate finger are made of an AI metallization. It is also possible to start the signal from a - 2 -
nem in einer Ecke oder zentral angeordneten Gatepad über Gatefinger über die Chipoberfläche zu verteilen (siehe Figur 1). Die üblicherweise verwendete Designregel besagt, dass der Abstand x der Gate Finger folgende Bedingung erfüllen muss.to be distributed in a corner or centrally arranged gate pad via gate fingers over the chip surface (see FIG. 1). The design rule usually used states that the distance x of the gate fingers must meet the following condition.
x « Ä -x «Ä -
R ist der Schichtwiderstand des Poly Siliziums, welches das Signal vom Gatefinger zum physikalischen Gate führt, c die MOS Kapazität pro Fläche des Gates und, τ die charakteristische Schaltzeit des IGBTs gegeben durch r = RGate ■ Ct0, ■ . RGate ist der Gate Vorwiderstand und Ctot die totale MOS Kapazität des Chips. Typische Werte sind c = 30 nF/cm2 , R = 30 Ohm und τ = 200 nsec. Das resultiert in x«0.47 cm. Ist die obige Bedingung erfüllt, so ist - unabhängig vom Gate- Vorwiderstand - die Spannungsverteilung im Gate zu jedem Zeitpunkt während des Schaltens flach und damit die Stromdichte homogen.R is the sheet resistance of the poly silicon, which leads the signal from the gate finger to the physical gate, c the MOS capacitance per area of the gate and, τ the characteristic switching time of the IGBT given by r = R gate ■ C t0 , ■ . R Gate is the gate series resistor and C tot is the total MOS capacity of the chip. Typical values are c = 30 nF / cm 2 , R = 30 ohms and τ = 200 nsec. This results in x «0.47 cm. If the above condition is met, regardless of the gate series resistor, the voltage distribution in the gate is flat at all times during switching and thus the current density is homogeneous.
Gate Finger erfordern jedoch eine komplexe und teure Lötmetallisierung, falls kathodenseitiges Löten erforderlich ist, und stellen hohe Anforderungen an die Passivierung. Passivierungsschwächen führen zu Gate- Emitter Kurzschlüssen die sich als Frühausfälle manifestieren und nur mit aufwendigen Burn-in Tests erfasst werden können. Ähnliche Probleme treten bei der Druckkontaktierung auf.However, gate fingers require complex and expensive solder metallization, if cathode-side soldering is required, and place high demands on the passivation. Passivation weaknesses lead to gate-emitter short circuits that manifest themselves as early failures and can only be detected with complex burn-in tests. Similar problems occur with pressure contacting.
Darstellung der ErfindungPresentation of the invention
Aufgabe der Erfindung ist es, einen IGBT anzugeben, der auf einfache Weise hergestellt werden kann und trotzdem homogen einschaltet. Diese Aufgabe wird durch die Merkmale der unabhängigen Ansprüche gelöst. - 3 -The object of the invention is to provide an IGBT that can be manufactured in a simple manner and nevertheless switches on homogeneously. This object is solved by the features of the independent claims. - 3 -
Kern der Erfindung ist es also, dass der Gatestrom im IGBT-Chip ausgehend vom Gateanschluss unmittelbar über die Polysiliziumschichten der Gateelektroden zu den IGBT-Emheitszellen weitergeleitet wird ohne Verwendung von Gate- fingern. Das Gatesignal kann nach einem ersten Ausführungsbeispiel über einen in einer Ecke angeordneten Gateanschluss (Gatepad) oder gemass einem zweiten Ausführungsbeispiel über einen zentralen Gateanschluss dem IGBT-Chip zugeführt werden.The essence of the invention is therefore that the gate current in the IGBT chip is passed on directly from the gate connection via the polysilicon layers of the gate electrodes to the IGBT emity cells without the use of gate fingers. According to a first exemplary embodiment, the gate signal can be supplied to the IGBT chip via a gate connection (gate pad) arranged in a corner or, according to a second exemplary embodiment, via a central gate connection.
Die Erfindung wendet sich somit diametral ab von der herrschenden Ansicht, dass ab einer gewissen Chipgrösse homogenes Einschalten nur unter Verwendung von Gatefingern erreicht werden kann. Vielmehr haben die Erfinder erstmals erkannt, dass für homogenes Abschalten eines IGBTs andere Designregeln gelten als für MOS Transistoren. Die Erfinder haben insbesondere erkannt, dass maximale Verlustleistungsdichte immer homogen ist, wenn die Plasmavertei- lung noch homogen ist. Ein bipolares Bauelement verhält sich insbesondere in dem Zeitpunkt, in dem der MOS-Strom nicht mehr genügt, um den äusseren Strom aufrecht zu erhalten, prinzipiell anders als ein unipolares Element wie z.B. ein MOS Transistor. Nach diesem Zeitpunkt erfolgt ein Übergang von bipolarem Strom zu reinem Löcherstrom, verbunden mit einem Ausräumen der Hauptjunction. Sobald dieser Prozess abgeschlossen ist, wird der volle Strom von Löchern getragen und die Raumladungszone baut sich auf. Die Plasmaverteilung ist aber lateral immer noch recht homogen. Deshalb wird auch die sehr inhomogene Stromverteilung rasch homogenisiert. Zum Zeitpunkt der maximalen Verlustleistung ist die Stromverteilung nahezu homogen. Deshalb wird die Safe Operating Area nicht reduziert und die Abschaltenergie kaum verändert. Als Konsequenz lassen sich IGBTs ohne Gate Finger bauen, auch wenn eine für gatefingerlose MOS Transistoren geltende Mindestfläche von 0.2 cm2 überschritten wird.The invention thus turns away diametrically from the prevailing view that, starting from a certain chip size, homogeneous switching on can only be achieved using gate fingers. Rather, the inventors recognized for the first time that different design rules apply to homogeneous switching off of an IGBT than to MOS transistors. In particular, the inventors have recognized that maximum power loss density is always homogeneous when the plasma distribution is still homogeneous. A bipolar component behaves fundamentally different from a unipolar element such as a MOS transistor, in particular when the MOS current is no longer sufficient to maintain the external current. After this point in time there is a transition from bipolar current to pure hole current, associated with clearing the main junction. Once this process is complete, the full current is carried through holes and the space charge zone builds up. The plasma distribution is still quite homogeneous laterally. Therefore, the very inhomogeneous current distribution is quickly homogenized. At the time of the maximum power loss, the current distribution is almost homogeneous. Therefore, the safe operating area is not reduced and the switch-off energy is hardly changed. As a consequence, IGBTs can be built without a gate finger, even if a minimum area of 0.2 cm 2 that applies to gate fingerless MOS transistors is exceeded.
Die Figuren 2a und 2b zeigen ein Ausführungsbeispiel eines erfindungsgemässen IGBT-Chips 1. Dargestellt ist ein erster Hauptanschluss 3, der von einer Isolie- - 4 -FIGS. 2a and 2b show an exemplary embodiment of an IGBT chip 1 according to the invention. A first main connection 3 is shown, which is connected by an insulation - 4 -
rung 7 und einem Gaterahmen 8 umgeben ist. Der Gaterahmen 8 steht in Verbindung mit einem Gateanschluss 4, von welchem z.B. Bonddrähte zum entsprechenden Gehäuseanschluss führen können. Im Gegensatz dazu sind beim Stand der Technik nach den Figuren la und lb Gatefinger 6 vorgesehen, die das Gate- signal ausgehend vom Gateanschluss 4 über die Chipoberfläche verteilen.tion 7 and a gate frame 8 is surrounded. The gate frame 8 is connected to a gate connection 4, of which e.g. Can lead bond wires to the corresponding housing connection. In contrast to this, gate fingers 6 are provided in the prior art according to FIGS. 1 a and 1 b, which distribute the gate signal from the gate connection 4 over the chip surface.
Die Vorteile der Erfindung sind insbesondere darin zu sehen, dass durch den Wegfall der Gatefinger eine einfache und billige Ausführung der Lötmetallisierung ermöglicht wird, - die einfachere Technologie eine höhere Zuverlässigkeit bei der Druckkontak- tierung der Chips ermöglicht.The advantages of the invention can be seen in particular in that the omission of the gate fingers enables simple and inexpensive execution of the soldering metallization, and the simpler technology enables greater reliability in the pressure contacting of the chips.
Kurze Beschreibung der ZeichnungenBrief description of the drawings
Im folgenden wird die Erfindung anhand von Zeichnungen weiter erläutert. Es zeigen:In the following the invention is further explained with reference to drawings. Show it:
Figur la: Eine Aufsicht auf einen IGBT-Chip nach dem Stand der Technik; Figur lb: Eine perspektivische Darstellung eines Teils des IGBT-Chips gemass Figur la; Figur 2a: Eine Aufsicht auf einen IGBT-Chip nach der Erfindung nach einem ersten Ausführungsbeispiel; Figur 2b: Eine perspektivische Darstellung eines Teils des IGBT-Chips gemass Figur 2a;Figur 3: Eine Aufsicht auf einen IGBT-Chip nach der Erfindung nach einem zweiten Ausführungsbeispiel; Figur 4: Einen Schnitt durch einen IGBT-Chip nach der Erfindung Figur 5: Eine Aufsicht auf eine Polysiliziumschicht.Figure la: A plan view of an IGBT chip according to the prior art; Figure lb: A perspective view of part of the IGBT chip according to Figure la; Figure 2a: A plan view of an IGBT chip according to the invention according to a first embodiment; Figure 2b: A perspective view of part of the IGBT chip according to Figure 2a Figure 3: A plan view of an IGBT chip according to the invention in a second embodiment; Figure 4: A section through an IGBT chip according to the invention Figure 5: A plan view of a polysilicon layer.
Die in den Figuren verwendeten Bezugszeichen sind in der Bezugszeichenliste zusammengefasst aufgelistet. - 5 -The reference symbols used in the figures are listed in summary form in the list of reference symbols. - 5 -
Wege zur Ausführung der ErfindungWays of Carrying Out the Invention
In Vorversuchen wurde ein langsamer 2.5 kV Chip mit einer Mindestchipoberflä- che von 0,2 cm"2 ohne Gate Finger gebaut und seine Eigenschaften gemessen. Sie waren innerhalb der Fehlergrenze ununterscheidbar von der Version mit Gate Finger. Die Befürchtung bestand jedoch, ein schneller Chip würde ohne Gate Finger unter extrem inhomogenen Stromverteilungen abschalten und deshalb hohe Schaltverluste, langsame Transienten und kleine SOA aufweisen. Analytische Rechnungen, numerische Simulationen des Schaltverhaltens sowie Schaltversuche von schnellen IGBTs ohne Gate Finger habe jedoch verblüffende Resultate gezeigt. Es zeigte sich, dass eine Signalausbreitungszeit vergleichbar mit der Schaltzeit τ nicht notwendigerweise zu einer inhomogenen Sromverteilung beim Abschalten führt. Die Versuche zeigten auch, dass das Einschalten im Vergleich zum Abschalten unkritisch ist.In preliminary tests, a slow 2.5 kV chip with a minimum chip surface area of 0.2 cm "2 was built without a gate finger and its properties measured. They were indistinguishable from the version with a gate finger within the error limit. However, there was a fear of a fast chip would switch off under extremely inhomogeneous current distributions without a gate finger and would therefore have high switching losses, slow transients and small SOA. However, analytical calculations, numerical simulations of the switching behavior and switching attempts by fast IGBTs without gate fingers have shown amazing results. It was found that a signal propagation time is comparable with the switching time τ does not necessarily lead to an inhomogeneous current distribution when switching off. The experiments also showed that switching on is not critical in comparison with switching off.
Für den Fall, dass die Gateansteuerung von der Chipperipherie erfolgt und dassIn the event that the gate control takes place from the chip periphery and that
R - cR - c
gewählt wird, tritt beim Abschalten nämlich zunächst eine Stromumverteilung auf. Die äusseren Teile des Chips beginnen abzuschalten, die Last hält den totalen Strom konstant und kommutiert Strom ins Zentrum des Chips. Zu dem Zeitpunkt ist die Anodenspannung noch im wesentlichen Null.is selected, a current redistribution occurs when switching off. The outer parts of the chip start to switch off, the load keeps the total current constant and commutates current into the center of the chip. At that point, the anode voltage is still essentially zero.
Zu diesem Zeitpunkt genügt der MOS Strom nicht mehr, um den äusseren Strom aufrecht zu erhalten. In einem reinen MOS Transistor setzt jetzt der Spannungsanstieg ein. Der Spannungsanstieg koppelt über die Gate-Anoden (Miller) Kapazität Ladung ins Gate, derart, dass die Spannungsverteilung über das Gate konstant bleibt und der Strom nicht weiter abfällt. Sobald die volle Lastspannung erreicht ist, bricht der Regelmechanismus ab, die Gatespannung sinkt und das Bauelement schaltet ab. Der Kern der Erfindung ist nun, dass erkannt und vorteilhaft ausgenutzt wurde, dass sich ein bipolares Bauelement ab dem o.g. Zeitpunkt prinzipiell anders verhält. Nach diesem Zeitpunkt erfolgt ein Übergang von bipolarem Strom zu rei- nem Löcherstrom, verbunden mit einem Ausräumen der Hauptjunction. Sobald dieser Prozess abgeschlossen ist, wird der volle Strom von Löchern getragen und die Raumladungszone baut sich auf. Die Plasmaverteilung ist aber lateral immer noch recht homogen. Deshalb wird auch die zu diesem Zeitpunkt sehr inhomogene Stromverteilung rasch homogenisiert. Zum Zeitpunkt der maximalen Ver- lustleistung ist die Stromverteilung nahezu homogen. Deshalb wird die SafeAt this point, the MOS current is no longer sufficient to maintain the external current. The voltage rise now begins in a pure MOS transistor. The voltage rise couples charge into the gate via the gate anode (Miller) capacitance in such a way that the voltage distribution over the gate remains constant and the current does not drop any further. As soon as the full load voltage is reached, the control mechanism stops, the gate voltage drops and the component switches off. The essence of the invention is that it has been recognized and advantageously used that a bipolar component basically behaves differently from the above-mentioned point in time. After this point in time there is a transition from bipolar current to pure hole current, associated with clearing the main junction. Once this process is complete, the full current is carried through holes and the space charge zone builds up. The plasma distribution is still quite homogeneous laterally. For this reason, the very inhomogeneous current distribution is quickly homogenized. At the time of the maximum power loss, the current distribution is almost homogeneous. That is why the safe
Operating Area nicht reduziert und die Abschaltenergie kaum verändert. Damit können IGBTs gebaut werden, die ohne Gatefinger auskommen.Operating area not reduced and the switch-off energy hardly changed. This allows IGBTs to be built that do not need a gate finger.
Die Figuren 2a und 2b zeigen einen erfindungsgemässen, gatefingerlosen IGBT Chip 1 von oben beziehungsweise in perspektivischer Darstellung mit einem ersten, sichtbaren Hautpschluss 3 und einem zweiten, nicht dargestellten Hauptanschluss sowie einem Gateanschluss 4, welcher in der in den Figuren 2a und 2b dargestellten Ausführungsform am Rand, insbesondere in einer Ecke des IGBT-Chips 1 angeordnet ist. Im Gegensatz zu den Figuren la und lb, die den Stand der Technik darstellen, sind keine Gatefinger 6 vorgesehen, sondern das Gatesignal wird ausgehend vom Gateanschluss 4 über einen Gaterahmen 8 über die Peripherie verteilt. Wie in Figur 2b sichtbar ist, steht auch der Gaterahmen 8 in unmittelbarer Wirkverbindung mit den Gateelektroden 5. Vorzugsweise weist er einen Widerstand von kleiner als 5 Ohm auf.Figures 2a and 2b show a gate fingerless IGBT chip 1 according to the invention from above or in perspective with a first, visible skin connector 3 and a second, not shown main connector and a gate connector 4, which in the embodiment shown in Figures 2a and 2b on Edge, in particular in a corner of the IGBT chip 1 is arranged. In contrast to FIGS. 1 a and 1 b, which represent the prior art, no gate fingers 6 are provided, but the gate signal is distributed from the gate connection 4 via a gate frame 8 over the periphery. As can be seen in FIG. 2b, the gate frame 8 is also in direct operative connection with the gate electrodes 5. It preferably has a resistance of less than 5 ohms.
Der erste Hauptanschluss 3 ist somit durch eine Fläche gebildet, welche bis auf eine Aussparung für den Gateanschluss 4 konvex ist, wobei im Falle der Ausführungsform gemass den Figuren 2a und 2b sein konvex ausgebildeter Flächenbereich vom Gaterahmen 8 umgeben ist. Sind mehrere Gateanschlüsse 4 vorhanden, so weist die im wesentlichen konvexe Fläche des ersten Hauptanschlusses eine entsprechende Anzahl Ausnehmungen auf. Zwischen dem grossflächigen ersten Hauptanschluss (dargestellt als Metallisierung), der insbesondere von der Kathode des IGBTs gebildet wird, und dem Gateanschluss 4 und dem Gaterahmen 8 ist eine Isolierung 7 vorgesehen. Nach der Erfindung ist der Gateanschluss 4 bzw. der Gaterahmen 8 mit den Polysiliziumschichten der Gateelektroden 5 des IGBTs direkt, d.h. ohne Zwischenschalten von Gatefingern verbunden. Figur 4 zeigt dies im Schnitt. Die Polysilizium- schicht 5 des IGBTs ist direkt mit dem Gateanschluss 4 verbunden. Die übrigen Polysiliziumschichten 5 der IGBT-Einheitszellen 2 sind im Bauelement parallelgeschaltet. Eine Ausführungsform einer Anordnung der Polysiliziumschichten 5 ist in Figur 5 dargestellt. Sie deckt in diesem Fall den Chip grossflächig ab und weist Ausnehmungen 5' auf. In Figur 4 ist auch die Isolierung 7, die zwischen dem Gateanschluss 4 und dem ersten Hauptanschluss 3 vorgesehen ist, bzw. der dafür vorgesehene Graben, deutlich zu sehen.The first main connection 3 is thus formed by a surface which is convex except for a recess for the gate connection 4, wherein in the case of the embodiment according to FIGS. 2a and 2b its convex surface area is surrounded by the gate frame 8. If a plurality of gate connections 4 are present, the essentially convex surface of the first main connection has a corresponding number of recesses. Insulation 7 is provided between the large-area first main connection (shown as metallization), which is formed in particular by the cathode of the IGBT, and the gate connection 4 and the gate frame 8. According to the invention, the gate connection 4 or the gate frame 8 is connected directly to the polysilicon layers of the gate electrodes 5 of the IGBT, ie without interposing gate fingers. Figure 4 shows this in section. The polysilicon layer 5 of the IGBT is connected directly to the gate connection 4. The remaining polysilicon layers 5 of the IGBT unit cells 2 are connected in parallel in the component. An embodiment of an arrangement of the polysilicon layers 5 is shown in FIG. 5. In this case, it covers the chip over a large area and has recesses 5 '. The insulation 7, which is provided between the gate connection 4 and the first main connection 3, or the trench provided for this purpose, can also be clearly seen in FIG.
Selbstverständlich kann der Gateanschluss 4 auch zentral auf dem IGBT-Chip 1 angeordnet sein. Figur 3 zeigt diese Ausführungsform. Wiederum ist der Gateanschluss 4 von einer Isolierung 7 umgeben, die ihn von dem Hauptanschluss 3 abkoppelt. Of course, the gate connection 4 can also be arranged centrally on the IGBT chip 1. Figure 3 shows this embodiment. Again, the gate connection 4 is surrounded by insulation 7, which decouples it from the main connection 3.
- 8 -- 8th -
BezugszeichenlisteReference list
1 IGBT-Chip1 IGBT chip
2 IGBT-Einheitszelle 3 erster Hauptanschluss2 IGBT unit cell 3 first main connection
4 Gateanschluss (Gatepad)4 gate connection (gatepad)
5 Gateelektrode 5' Ausnehmung5 gate electrode 5 'recess
6 Gatefinger 7 Isolierung6 gate fingers 7 insulation
8 Gaterahmen 8 gate frames

Claims

- 9 -PATENTANSPRUECHE - 9 -PATENT CLAIMS
1. Bipolartransistor mit isolierter Gateelektrode (IGBT) umfassend mindestens einen IGBT-Chip (1) mit einer Mehrzahl von parallelgeschalteten IGBT-Einheitszellen (2), pro Chip einem ersten (3) und zweitem Hauptanschluss und mindestens einem Gateanschluss (4), der mit den Gateelektroden (5) der IGBT-Einheitszellen (2) in elektrischer Wirkverbindung steht, wobei die Gateelektroden (5) durch elektrisch parallelgeschaltete Polysiliziumschichten gebildet werden, dadurch gekennzeichnet, dass der IGBT-Chip (1) eine gatefingerlose Fläche in einer Grosse aufweist, welche bei gatefingerlosen MOS-Transistoren zu einem inhomogenen Abschalten führt, und dass die Polysiliziumschichten mit dem oder jedem Gateanschluss (4) in unmittelbarer Wirkver- bindung verbunden sind.1. Bipolar transistor with insulated gate electrode (IGBT) comprising at least one IGBT chip (1) with a plurality of IGBT unit cells (2) connected in parallel, a first (3) and a second main connection and at least one gate connection (4) per chip the gate electrodes (5) of the IGBT unit cells (2) are in electrical operative connection, the gate electrodes (5) being formed by electrically parallel polysilicon layers, characterized in that the IGBT chip (1) has a gate fingerless area of a size which in the case of gate fingerless MOS transistors leads to inhomogeneous switching off and that the polysilicon layers are connected to the or each gate connection (4) in a direct operative connection.
2. Bipolartransistor mit isolierter Gateelektrode (IGBT) umfassend mindestens einen IGBT-Chip (1) mit einer Mehrzahl von parallelgeschalteten IGBT-Einheitszellen (2), pro Chip einem ersten (3) und zweitem Hauptanschluss und mindestens einem Gateanschluss (4), der mit den2. Bipolar transistor with insulated gate electrode (IGBT) comprising at least one IGBT chip (1) with a plurality of IGBT unit cells (2) connected in parallel, a first (3) and a second main connection and at least one gate connection (4) per chip the
Gateelektroden (5) der IGBT-Einheitszellen (2) in elektrischer Wirkverbindung steht, wobei die Gateelektroden (5) durch elektrisch parallelgeschaltete Polysiliziumschichten gebildet werden, dadurch gekennzeichnet, dass jeder IGBT-Chip (1) eine Fläche von mindestens 0.2 cm2 aufweist und dass die Polysiliziumschichten mit dem oder jedem Gateanschluss (4) in unmittelbarer Wirkverbindung verbunden sind.Gate electrodes (5) of the IGBT unit cells (2) are in electrical operative connection, the gate electrodes (5) being formed by electrically parallel polysilicon layers, characterized in that each IGBT chip (1) has an area of at least 0.2 cm 2 and that the polysilicon layers are connected to the or each gate connection (4) in a direct operative connection.
3. Bipolartransistor nach einem der Ansprüche 1 oder 2, dadurch ge- kennzeichnet, dass der erste Hauptanschluss (3) durch eine Fläche ge- - 10 -3. Bipolar transistor according to one of claims 1 or 2, characterized in that the first main connection (3) through a surface - 10 -
bildet ist, welche bis auf mindestens eine Aussparung für den mindestens einen Gateanschluss (4) konvex ist.is formed, which is convex except for at least one recess for the at least one gate connection (4).
4. Bipolartransistor mit isolierter Gateelektrode nach einem der Ansprü- ehe 1 oder 2, dadurch gekennzeichnet, dass der Gateanschluss (4) am4. Bipolar transistor with insulated gate electrode according to one of claims 1 or 2, characterized in that the gate terminal (4) on
Rand des IGBT-Chips (1), insbesondere in einer Ecke, angeordnet ist.Edge of the IGBT chip (1), in particular in a corner.
5. Bipolartransistor nach Anspruch 4, dadurch gekennzeichnet, dass ein den IGBT-Chip (1) umgebender, metallisierter Gaterahmen (8) vorge- sehen ist, der mit dem Gateanschluss (4) elektrisch verbunden ist, und dass zwischen dem auf derselben Chipseite wie der Gateanschluss angeordneten, ersten Hauptanschluss (3) und dem Gaterahmen (8) bzw. dem Gateanschluss (4) eine Isolierung (7) vorgesehen ist.5. Bipolar transistor according to claim 4, characterized in that a metallized gate frame (8) surrounding the IGBT chip (1) is provided, which is electrically connected to the gate connection (4), and between that on the same chip side as the gate connection arranged, the first main connection (3) and the gate frame (8) or the gate connection (4) an insulation (7) is provided.
6. Bipolartransistor nach Anspruch 5, dadurch gekennzeichnet, dass der Gaterahmen (8) einen Schichtwiderstand von kleiner als 5 Ohm aufweist.6. Bipolar transistor according to claim 5, characterized in that the gate frame (8) has a sheet resistance of less than 5 ohms.
7. Bipolartransistor nach den Ansprüchen 3 und 5, dadurch gekenn- zeichnet, dass der Gaterahmen (8) den konvex ausgebildeten Flächenbereich des ersten Hauptanschlusses (3) umgibt.7. Bipolar transistor according to claims 3 and 5, characterized in that the gate frame (8) surrounds the convex surface area of the first main connection (3).
8. Bipolartransistor nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass der Gateanschluss (4) im wesentlichen im Zentrum des IGBT-Chips (1) angeordnet ist und von einer Isolierung (7) umgeben ist. 8. Bipolar transistor according to one of claims 1 or 2, characterized in that the gate terminal (4) is arranged substantially in the center of the IGBT chip (1) and is surrounded by insulation (7).
EP99904672A 1998-02-27 1999-02-25 Bipolar transistor with an insulated gate electrode Ceased EP1060517A1 (en)

Applications Claiming Priority (5)

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DE19808154A DE19808154A1 (en) 1998-02-27 1998-02-27 Bipolar transistor with insulated gate (IGBT)
DE19808154 1998-02-27
DE1998123170 DE19823170A1 (en) 1998-05-23 1998-05-23 Bipolar transistor with insulated gate electrode
DE19823170 1998-05-23
PCT/CH1999/000086 WO1999044240A1 (en) 1998-02-27 1999-02-25 Bipolar transistor with an insulated gate electrode

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060151785A1 (en) * 2005-01-13 2006-07-13 Campbell Robert J Semiconductor device with split pad design
JP2015204374A (en) * 2014-04-14 2015-11-16 株式会社ジェイテクト semiconductor device
JP2015204375A (en) * 2014-04-14 2015-11-16 株式会社ジェイテクト semiconductor device
JP6476000B2 (en) * 2015-02-17 2019-02-27 三菱電機株式会社 Semiconductor device and semiconductor module
US9685438B2 (en) 2015-08-19 2017-06-20 Raytheon Company Field effect transistor having two-dimensionally distributed field effect transistor cells
US9698144B2 (en) * 2015-08-19 2017-07-04 Raytheon Company Field effect transistor having loop distributed field effect transistor cells

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5987828A (en) 1982-11-12 1984-05-21 Hitachi Ltd Semiconductor device
IE55753B1 (en) * 1983-09-06 1991-01-02 Gen Electric Power semiconductor device with main current section and emulation current section
US4783690A (en) 1983-09-06 1988-11-08 General Electric Company Power semiconductor device with main current section and emulation current section
US4644637A (en) 1983-12-30 1987-02-24 General Electric Company Method of making an insulated-gate semiconductor device with improved shorting region
US4672407A (en) 1984-05-30 1987-06-09 Kabushiki Kaisha Toshiba Conductivity modulated MOSFET
US5528058A (en) 1986-03-21 1996-06-18 Advanced Power Technology, Inc. IGBT device with platinum lifetime control and reduced gaw
US5208471A (en) 1989-06-12 1993-05-04 Hitachi, Ltd. Semiconductor device and manufacturing method therefor
WO1991003842A1 (en) 1989-08-31 1991-03-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor
JP2858404B2 (en) 1990-06-08 1999-02-17 株式会社デンソー Insulated gate bipolar transistor and method of manufacturing the same
US5448083A (en) 1991-08-08 1995-09-05 Kabushiki Kaisha Toshiba Insulated-gate semiconductor device
US5260590A (en) 1991-12-23 1993-11-09 Harris Corp. Field effect transistor controlled thyristor having improved turn-on characteristics
JPH05206469A (en) 1992-01-29 1993-08-13 Hitachi Ltd Insulated gate bipolar transistor
JPH05235345A (en) * 1992-02-20 1993-09-10 Nec Corp Semiconductor device and manufacture thereof
DE59207386D1 (en) 1992-03-13 1996-11-21 Asea Brown Boveri Power semiconductor component that can be switched off
GB2268332A (en) 1992-06-25 1994-01-05 Gen Electric Power transistor with reduced gate resistance and inductance
JP2837033B2 (en) 1992-07-21 1998-12-14 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP3163820B2 (en) 1992-07-28 2001-05-08 富士電機株式会社 Semiconductor device
JPH06244429A (en) 1992-12-24 1994-09-02 Mitsubishi Electric Corp Insulated-gate semiconductor device and manufacture thereof
DE4315178A1 (en) 1993-05-07 1994-11-10 Abb Management Ag IGBT with self-aligning cathode structure and process for its production
JPH07161992A (en) 1993-10-14 1995-06-23 Fuji Electric Co Ltd Insulated-gate bipolar transistor
JP2987040B2 (en) 1993-11-05 1999-12-06 三菱電機株式会社 Insulated gate semiconductor device
JPH07235672A (en) 1994-02-21 1995-09-05 Mitsubishi Electric Corp Insulated-gate type semiconductor device and manufacture thereof
JP3481287B2 (en) 1994-02-24 2003-12-22 三菱電機株式会社 Manufacturing method of semiconductor device
US5539232A (en) 1994-05-31 1996-07-23 Kabushiki Kaisha Toshiba MOS composite type semiconductor device
US5581100A (en) 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
US5665996A (en) 1994-12-30 1997-09-09 Siliconix Incorporated Vertical power mosfet having thick metal layer to reduce distributed resistance
JPH08186258A (en) 1995-01-06 1996-07-16 Hitachi Ltd Semiconductor device and its production
DE19512799C2 (en) 1995-04-05 1998-11-12 Siemens Ag Semiconductor component controllable by field effect
JP3384198B2 (en) 1995-07-21 2003-03-10 三菱電機株式会社 Insulated gate semiconductor device and method of manufacturing the same
JP3493903B2 (en) 1995-09-29 2004-02-03 株式会社デンソー Semiconductor device
US5744861A (en) 1995-11-13 1998-04-28 Asea Brown Boveri Ag Power semiconductor module
US5661315A (en) 1995-12-28 1997-08-26 Asea Brown Boveri Ag Controllable power semiconductor component
US6008092A (en) 1996-02-12 1999-12-28 International Rectifier Corporation Short channel IGBT with improved forward voltage drop and improved switching power loss
GB9605672D0 (en) 1996-03-18 1996-05-22 Westinghouse Brake & Signal Insulated gate bipolar transistors
JP3410286B2 (en) 1996-04-01 2003-05-26 三菱電機株式会社 Insulated gate semiconductor device
DE19651108C2 (en) 1996-04-11 2000-11-23 Mitsubishi Electric Corp High breakdown voltage gate trench type semiconductor device and its manufacturing method
JPH09331062A (en) 1996-06-11 1997-12-22 Mitsubishi Electric Corp Semiconductor device and its manufacture
DE19705276A1 (en) 1996-12-06 1998-08-20 Semikron Elektronik Gmbh IGBT with trench gate structure
JP2982785B2 (en) * 1998-04-03 1999-11-29 富士電機株式会社 Depletion type MOS semiconductor device and MOS power IC

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9944240A1 *

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