EP0974817A4 - Plaquette de circuit et detecteur, et leur procede de fabrication - Google Patents

Plaquette de circuit et detecteur, et leur procede de fabrication

Info

Publication number
EP0974817A4
EP0974817A4 EP98911191A EP98911191A EP0974817A4 EP 0974817 A4 EP0974817 A4 EP 0974817A4 EP 98911191 A EP98911191 A EP 98911191A EP 98911191 A EP98911191 A EP 98911191A EP 0974817 A4 EP0974817 A4 EP 0974817A4
Authority
EP
European Patent Office
Prior art keywords
grooves
insulating regions
circuit board
board
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98911191A
Other languages
German (de)
English (en)
Other versions
EP0974817A1 (fr
Inventor
Noriaki Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Publication of EP0974817A1 publication Critical patent/EP0974817A1/fr
Publication of EP0974817A4 publication Critical patent/EP0974817A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/68—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using thermal effects
    • G01F1/684—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
    • G01F1/6845—Micromachined devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Fluid Mechanics (AREA)
  • Measuring Volume Flow (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)
  • Measurement Of Radiation (AREA)

Abstract

L'invention porte sur la formation à l'intérieur d'une plaquette de circuit imprimé à substrat semi-conducteur de zones cylindriques isolantes électriquement continues entre la partie frontale et la partie dorsale, mais fermées dans le sens du plan. Lesdites zones, constituées d'un matériau isolant thermorésistant, sont obtenues en perçant dans la plaquette des trous ou rainures traversants, puis en en revêtant les parois de couches d'oxydes ou de nitrures, ou en les bouchant avec un matériau isolant. Dans le cas des rainures, après formation des zones isolantes, la plaquette est amincie par polissage ou autre procédé de manière à faire apparaître la rainure sur les deux faces de la plaquette. Les surfaces entourées par les zones isolantes servent d'électrodes par diffusion d'impuretés, ce qui accroît la conductivité électrique.
EP98911191A 1997-04-03 1998-04-03 Plaquette de circuit et detecteur, et leur procede de fabrication Withdrawn EP0974817A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8505997 1997-04-03
JP8505997 1997-04-03
PCT/JP1998/001540 WO1998044319A1 (fr) 1997-04-03 1998-04-03 Plaquette de circuit et detecteur, et leur procede de fabrication

Publications (2)

Publication Number Publication Date
EP0974817A1 EP0974817A1 (fr) 2000-01-26
EP0974817A4 true EP0974817A4 (fr) 2006-09-13

Family

ID=13848075

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98911191A Withdrawn EP0974817A4 (fr) 1997-04-03 1998-04-03 Plaquette de circuit et detecteur, et leur procede de fabrication

Country Status (5)

Country Link
US (2) US6353262B1 (fr)
EP (1) EP0974817A4 (fr)
KR (1) KR100337658B1 (fr)
CN (1) CN1187800C (fr)
WO (1) WO1998044319A1 (fr)

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FR2805709B1 (fr) 2000-02-28 2002-05-17 Commissariat Energie Atomique Connexion electrique entre deux faces d'un substrat et procede de realisation
WO2002023630A2 (fr) * 2000-09-13 2002-03-21 Applied Materials, Inc. Trous d'interconnexion en bloc de silicium micro-usines destines au transfert de signaux electriques vers l'arriere d'une plaquette de silicium
US6743731B1 (en) * 2000-11-17 2004-06-01 Agere Systems Inc. Method for making a radio frequency component and component produced thereby
DE10205026C1 (de) * 2002-02-07 2003-05-28 Bosch Gmbh Robert Halbleitersubstrat mit einem elektrisch isolierten Bereich, insbesondere zur Vertikalintegration
EP1351288B1 (fr) * 2002-04-05 2015-10-28 STMicroelectronics Srl Procédé pour fabriquer une interconnexion isolée à travers un corps semi-conducteur et dispositif semi-conducteur correspondant
EP1396705B1 (fr) 2002-08-27 2016-12-21 Sensirion Holding AG Détecteur d'écoulement avec des passages et procédé pour sa fabrication
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
JP4517843B2 (ja) * 2004-12-10 2010-08-04 エルピーダメモリ株式会社 半導体装置
US20070042563A1 (en) * 2005-08-19 2007-02-22 Honeywell International Inc. Single crystal based through the wafer connections technical field
JP2008516252A (ja) * 2005-09-20 2008-05-15 ビ−エイイ− システムズ パブリック リミテッド カンパニ− センサー装置
EP1987535B1 (fr) * 2006-02-01 2011-06-01 Silex Microsystems AB Procédé de réalisation d'interconnexions verticales
JP4845187B2 (ja) * 2006-02-07 2011-12-28 株式会社山武 センサのパッケージ構造及びこれを有するフローセンサ
EP2002477B1 (fr) * 2006-03-27 2011-12-21 Philips Intellectual Property & Standards GmbH Méthode de fabrication d'une interconnxion transversale sur substrat faiblement ohmique pour des plaquettes à semi-conducteur
EP1873822A1 (fr) * 2006-06-27 2008-01-02 STMicroelectronics S.r.l. Contact avant-arrière de dispositifs électroniques avec défauts induits pour améliorer la conductivité
US7544605B2 (en) * 2006-11-21 2009-06-09 Freescale Semiconductor, Inc. Method of making a contact on a backside of a die
JP4497165B2 (ja) * 2007-02-05 2010-07-07 株式会社デンソー 半導体装置の製造方法
WO2009050207A1 (fr) * 2007-10-15 2009-04-23 Interuniversitair Microelectronica Centrum Vzw Procédé de fabrication d'interconnexions électriques et dispositifs associés
US8099218B2 (en) * 2007-11-30 2012-01-17 Caterpillar Inc. Paving system and method
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DE102007060632A1 (de) * 2007-12-17 2009-06-18 Robert Bosch Gmbh Verfahren zum Herstellen eines Kappenwafers für einen Sensor
EP2259307B1 (fr) * 2009-06-02 2019-07-03 Napra Co., Ltd. Dispositif électronique
EP2457065A1 (fr) 2009-07-22 2012-05-30 Koninklijke Philips Electronics N.V. Circuit intégré à capteur de flux thermique à faible temps de réponse et haute sensibilité
JP5514559B2 (ja) * 2010-01-12 2014-06-04 新光電気工業株式会社 配線基板及びその製造方法並びに半導体パッケージ
JP5209075B2 (ja) 2010-05-21 2013-06-12 有限会社 ナプラ 電子デバイス及びその製造方法
FR2964793B1 (fr) * 2010-09-09 2014-04-11 Ipdia Dispositif d'interposition
TW201242122A (en) * 2011-04-15 2012-10-16 Chi Mei Lighting Tech Corp Light-emitting diode device
EP2602818A1 (fr) * 2011-12-09 2013-06-12 Ipdia Dispositif interposeur
TWI503934B (zh) * 2013-05-09 2015-10-11 Advanced Semiconductor Eng 半導體元件及其製造方法及半導體封裝結構
CN106104770B (zh) * 2014-03-12 2019-02-15 株式会社晶磁电子日本 层叠半导体集成电路装置
CN106017587A (zh) * 2016-05-12 2016-10-12 北京启芯传感科技有限公司 镂空热膜式流量传感器及其制作集成方法
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
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US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) * 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
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US5511428A (en) * 1994-06-10 1996-04-30 Massachusetts Institute Of Technology Backside contact of sensor microstructures
DE19511198A1 (de) * 1995-03-27 1996-10-02 Bosch Gmbh Robert Verfahren zur Herstellung von Strukturen, insbesondere für ein Mikrodosiersystem

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US5511428A (en) * 1994-06-10 1996-04-30 Massachusetts Institute Of Technology Backside contact of sensor microstructures
DE19511198A1 (de) * 1995-03-27 1996-10-02 Bosch Gmbh Robert Verfahren zur Herstellung von Strukturen, insbesondere für ein Mikrodosiersystem

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Title
See also references of WO9844319A1 *

Also Published As

Publication number Publication date
US6353262B1 (en) 2002-03-05
US20020074615A1 (en) 2002-06-20
KR100337658B1 (ko) 2002-05-24
KR20010005947A (ko) 2001-01-15
US6475821B2 (en) 2002-11-05
CN1259205A (zh) 2000-07-05
WO1998044319A1 (fr) 1998-10-08
CN1187800C (zh) 2005-02-02
EP0974817A1 (fr) 2000-01-26

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