WO2002023630A2 - Trous d'interconnexion en bloc de silicium micro-usines destines au transfert de signaux electriques vers l'arriere d'une plaquette de silicium - Google Patents

Trous d'interconnexion en bloc de silicium micro-usines destines au transfert de signaux electriques vers l'arriere d'une plaquette de silicium Download PDF

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Publication number
WO2002023630A2
WO2002023630A2 PCT/US2001/026447 US0126447W WO0223630A2 WO 2002023630 A2 WO2002023630 A2 WO 2002023630A2 US 0126447 W US0126447 W US 0126447W WO 0223630 A2 WO0223630 A2 WO 0223630A2
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WIPO (PCT)
Prior art keywords
wafer
stack
wafers
forming
chip
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Application number
PCT/US2001/026447
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English (en)
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WO2002023630A3 (fr
Inventor
Harald S. Gross
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Applied Materials, Inc.
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Publication date
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to AU2001286711A priority Critical patent/AU2001286711A1/en
Publication of WO2002023630A2 publication Critical patent/WO2002023630A2/fr
Publication of WO2002023630A3 publication Critical patent/WO2002023630A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to making electrical interconnects in columns or modules of integrated chips.
  • U.S. Patent No. 5,656,553 illustrates a prior art approach to the problem of making microcolumns of chips.
  • the assembly and subsequent contacting of the IC's in the stack is done after dicing the chips or chip arrays out of the silicon wafers.
  • the interconnections can be said to be "three dimensional” only in the rather limited sense that "side surface metallization" is applied to the peripheral edges of planar arrays of integrated chips subsequent to the dicing of the wafer stack.
  • the assembly and contacting of the chips in the stack is done at the wafer level prior to dicing.
  • the djcing is the last process step.
  • no additional process steps after dicing are needed in order to form the contact pads on each layer of the chip stack, because again all pads are formed at the wafer level before dicing.
  • the interconnects are implemented in a fully three dimensional manner at the wafer level.
  • the technique of the present invention permits the manufacturing of a stack of IC's and/or MEMS (microelectromechanical systems) that are electrically interconnected at the wafer level before dicing into chips.
  • MEMS microelectromechanical systems
  • Such MEMS are typically made using the same fabrication techniques as are used in the semiconductor industry generally. (As used herein, the term "chip” is meant to be broad enough to include such MEMS.) Therefore, a much higher density of IC's and/or MEMS is possible compared to the conventional packaging of IC's and/or MEMS.
  • the interconnects are more robust than with conventional wire bonding.
  • the present invention includes a method for making electrical interconnects by using portions of the silicon chips themselves as electrical feedthroughs ("block vias").
  • the block vias are configured so as to lead to one layer of the column that is electrically connected to the environment.
  • Using block vias it is possible, for example, to assemble one hundred or more columns at the same time from a 4" wafer.
  • the present invention includes a method for making electrical interconnects by using "cutouts" from the chips. To make the cutouts, the same fabrication processes involved in forming block vias are used. The cutout technique allows the contacting of all the layers in the stack.
  • both the block via and cutout techniques permit the transfer of multiple electrical signals from one side of a wafer to the other through the wafer itself.
  • the electrical interconnections are implemented in a novel manner at the wafer level prior to dicing.
  • Figure 1 a is a side cut-away view of a stack of three chips showing the use of block vias according to the present invention.
  • Figure 1 b is a side view of a stack of three chips showing the use of cutouts according to the present invention.
  • Figures 2a, 2b, 2c, and 2d show a series of cross-sectional and top views of a wafer at different points during a fabrication process according to the present invention.
  • Figure 3 shows an exploded view of a chip stack and illustrates the formation of electrical interconnects according to the present invention.
  • Figure 4 shows a perspective view of a portion of one wafer (with a block via) of a wafer stack (after the stack has been diced) and a top view of a portion of the wafer (with block via) prior to dicing.
  • Figure 1a illustrates the use of the block vias in a stack of three chips.
  • a "block via” is a region of a wafer layer or chip layer that has been isolated from the rest of the layer so as to serve as an electrical feedthrough through the layer. Between block via A and the rest of chip I, a trench is etched through the wafer. The same is done with respect to block via B and chip II as well as block via C and chip III. To avoid electrical shorting of the chips, an insulating material such as silicon oxide may be deposited on the backside of chips I and II except for the via regions A and B. Region A could be an octupol electrode of the microcolumn and is therefore electrically connected to C by way of block via B.
  • Block vias can be used in the fabrication of a variety of microcolumns, such as a microcolumn of a miniaturized scanning electron microscope, for example, for leading all the electrical signals of the microcolumn to a cpmmon carrier such as an I C header.
  • Figure 1b shows a stack of three chips I'.ll', and III' with two cutouts D and E.
  • a "cutout" is a recess passing through one or more layers in a stack of chip layers or wafer layers so as to provide a contact pad for an electrical interconnect to be made at the bottom of the recess.
  • the electrical connections to the chips can be made by wire bonding to the contact pads provided by the cutouts.
  • Figure 1b shows a wire bond connection 10 to a pad created by cutout D and another wire bond connection 20 to a second pad created by cutout E.
  • the same fabrication processes are used as with the block vias.
  • the patterns of all the blocks may preferably be the same because it is necessary that all the blocks drop out of the wafers during the etching of the trenches. Then each chip in the stack can readily be electrically contacted using the cutouts, for example, by wire bonding from the top.
  • microcolumns comprising glass chips (which are portions of wafers in which a thin silicon layer is bonded to a glass layer made of pyrex glass or other glass, and circuit features are formed on the silicon layer) and microcolumns comprising chips which are portions of "silicon on insulator” (SOI) wafers.
  • Glass chips are sometimes used in applications in which very high voltages are applied to circuit elements, and ultrasonic drilling instead of etching can be employed to manufacture microcolumns comprising glass chips.
  • Figures 2a, 2b, 2c, and 2d show an example of a fabrication methodology for making block vias in a wafer 40.
  • the block via 30 can be fabricated from the backside of the wafer either after or before the manufacturing of an IC or MEMS is completed on the front side.
  • the cross-sectional view of Fig. 2a shows the wafer at a stage where a photoresist mask 47 has been placed on the wafer for Deep Reactive Ion Etching (DRIE) through the wafer.
  • the mask shape in this case is in the form of a "U" as is shown in the top view (on the right side) of Fig. 2a.
  • Other etching or drilling techniques such as laser drilling, or even cutting with a saw, are employed in alternative embodiments to form the trench for defining the block via.
  • a photoresist layer 48 on the bottom can serve as an etch stop or other materials can also be employed for this purpose.
  • the width T of the etched trench 35 depends on the breakdown voltage of the application. At the current time minimum gaps of 15 micrometers can be etched successfully through a wafer. If necessary the gap can be extended to a width of a few hundreds of micrometers if high voltages are to be used. In this case a recess also has to be fabricated on parts of the chip near the block via.
  • an insulating material 68 is grown onto the wafer as shown in the cross-sectional view of Fig. 2c by an appropriate deposition technique such as the evaporation of silicon oxide through a shadow mask.
  • the portion of Fig. 2c on the right is a top view of the wafer corresponding to the cross-sectional view on the left side of Fig. 2c).
  • a thermal oxide that grows not only on the surface but also on the side wall of the block vias may used in order to meet particular requirements.
  • a conductive material 78 like gold is grown onto the block vias and parts of the insulating layer 68.
  • a stack of wafers including one or more wafers with the block vias formed as described above
  • Other bonding techniques like soldering or gluing could also be applied.
  • the right portion of Fig. 4 is a top view of a portion of a wafer (in which block via 30 of Fig. 2d has been formed) of a wafer stack prior to dicing, showing a dicing line (DL) along which the wafer is to be diced.
  • the left portion of Figure 4 is a perspective view of a portion of the wafer (with block via 3.0) after the wafer stack has been diced along line DL.
  • the electrical connection between the block via and the chip is removed so that the outline of the "U" shaped trench becomes a closed curve. Accordingly, the block vias have to differ in size from one chip to another in the stack in order to carry each other.
  • the etched shape is a square (closed curve) instead of a "U"
  • a "cutout” is formed at the edge of each chip before dicing.
  • the square shaped blocks then fall out of the wafer during processing.
  • the cutout technique aflows the contacting of a chip in the wafer without the need for a cutout further down in the stack, for example by wire bonding from the top.
  • Fig. 3 shows an exploded view of a chip stack formed in accordance with the invention with different block via sizes.
  • part 3 of layer 90 (which layer may be a MEMS) is ultimately connected electrically to pad 125 of the IC carrier 120.
  • Part 3 could be a freestanding electrode that is etched out of the wafer.
  • Part 3 is also electrically connected to an electrical contact on the top of IC 1 in chip layer 110 using block vias 105 and 115 and with a press on contact f.
  • the ground of IC 1 is connected to a contact on the IC carrier 120.
  • a contact pad on top of IC 2 (on chip layer 100) is connected to block via 108 with a press on contact e and the block vias 108 and 118 are connected with the IC carrier 120 using contact 123.
  • the ground of IC 2 is connected with a contact on the IC carrier.
  • Part 4 of the MEMS is connected using contact d to another pad of IC 2.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Micromachines (AREA)

Abstract

L'invention concerne un procédé de fabrication d'interconnexions électriques en 3D au niveau d'une plaquette pour une colonne ou un module de microcircuits intégrés avant le découpage en dés d'une pile de plaquettes en piles de microcircuits intégrés. Un aspect de la présente invention comprend un procédé de fabrication d'interconnexions électriques utilisant des parties de microcircuits intégrés de silicium comme trous d'interconnexion (« trous d'interconnexion en bloc »). Ces trous d'interconnexion en bloc sont configurés de façon à conduire à une couche de la colonne connectée électriquement à l'environnement. Un autre aspect de l'invention comprend un procédé de fabrication d'interconnexions électriques utilisant des découpes des microcircuits intégrés. Contrairement aux antériorités, les techniques faisant appel aux trous d'interconnexion en bloc et aux découpes permettent un transfert de signaux électriques multiples d'un côté de la plaquette à l'autre par la plaquette.
PCT/US2001/026447 2000-09-13 2001-08-23 Trous d'interconnexion en bloc de silicium micro-usines destines au transfert de signaux electriques vers l'arriere d'une plaquette de silicium WO2002023630A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001286711A AU2001286711A1 (en) 2000-09-13 2001-08-23 Micromachined silicon block vias for transferring electrical signals to the backside of a silicon wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66064500A 2000-09-13 2000-09-13
US09/660,645 2000-09-13

Publications (2)

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WO2002023630A2 true WO2002023630A2 (fr) 2002-03-21
WO2002023630A3 WO2002023630A3 (fr) 2003-03-20

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PCT/US2001/026447 WO2002023630A2 (fr) 2000-09-13 2001-08-23 Trous d'interconnexion en bloc de silicium micro-usines destines au transfert de signaux electriques vers l'arriere d'une plaquette de silicium

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006134233A1 (fr) * 2005-06-17 2006-12-21 Vti Technologies Oy Capteur de mouvement micromécanique et son procédé de fabrication
WO2007034240A2 (fr) * 2005-09-20 2007-03-29 Bae Systems Plc Capteur

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
EP0974817A1 (fr) * 1997-04-03 2000-01-26 Yamatake Corporation Plaquette de circuit et detecteur, et leur procede de fabrication
WO2000035007A1 (fr) * 1998-12-08 2000-06-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Procede pour l'integration verticale de plans de circuit actifs et circuit integre vertical produit a l'aide de celui-ci
EP1151962A1 (fr) * 2000-04-28 2001-11-07 STMicroelectronics S.r.l. Structure de connexion électrique entre un premier et un second matériau semi-conducteur superposé, composite comportant la même structure de connexion électrique et procédé de fabrication associé

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
US5292686A (en) * 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
EP0974817A1 (fr) * 1997-04-03 2000-01-26 Yamatake Corporation Plaquette de circuit et detecteur, et leur procede de fabrication
WO2000035007A1 (fr) * 1998-12-08 2000-06-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Procede pour l'integration verticale de plans de circuit actifs et circuit integre vertical produit a l'aide de celui-ci
EP1151962A1 (fr) * 2000-04-28 2001-11-07 STMicroelectronics S.r.l. Structure de connexion électrique entre un premier et un second matériau semi-conducteur superposé, composite comportant la même structure de connexion électrique et procédé de fabrication associé

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006134233A1 (fr) * 2005-06-17 2006-12-21 Vti Technologies Oy Capteur de mouvement micromécanique et son procédé de fabrication
US7682861B2 (en) 2005-06-17 2010-03-23 Vti Technologies Oy Method for manufacturing a micromechanical motion sensor, and a micromechanical motion sensor
WO2007034240A2 (fr) * 2005-09-20 2007-03-29 Bae Systems Plc Capteur
WO2007034240A3 (fr) * 2005-09-20 2007-11-29 Bae Systems Plc Capteur

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Publication number Publication date
WO2002023630A3 (fr) 2003-03-20
AU2001286711A1 (en) 2002-03-26

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