DE69809623T2 - Logische MOS-Schaltung und Halbleitervorrichtung - Google Patents

Logische MOS-Schaltung und Halbleitervorrichtung

Info

Publication number
DE69809623T2
DE69809623T2 DE69809623T DE69809623T DE69809623T2 DE 69809623 T2 DE69809623 T2 DE 69809623T2 DE 69809623 T DE69809623 T DE 69809623T DE 69809623 T DE69809623 T DE 69809623T DE 69809623 T2 DE69809623 T2 DE 69809623T2
Authority
DE
Germany
Prior art keywords
semiconductor device
mos circuit
logical
logical mos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69809623T
Other languages
English (en)
Other versions
DE69809623D1 (de
Inventor
Yuichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69809623D1 publication Critical patent/DE69809623D1/de
Publication of DE69809623T2 publication Critical patent/DE69809623T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
DE69809623T 1997-04-18 1998-04-15 Logische MOS-Schaltung und Halbleitervorrichtung Expired - Lifetime DE69809623T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10205997A JP3178799B2 (ja) 1997-04-18 1997-04-18 Ｍｏｓ論理回路及びこのｍｏｓ論理回路を備えた半導体装置

Publications (2)

Publication Number Publication Date
DE69809623D1 DE69809623D1 (de) 2003-01-09
DE69809623T2 true DE69809623T2 (de) 2003-09-18

Family

ID=14317206

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69809623T Expired - Lifetime DE69809623T2 (de) 1997-04-18 1998-04-15 Logische MOS-Schaltung und Halbleitervorrichtung
DE69833231T Expired - Lifetime DE69833231T2 (de) 1997-04-18 1998-04-15 MOS-Logikschaltung und Halbleiterbauteil mit einer solchen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69833231T Expired - Lifetime DE69833231T2 (de) 1997-04-18 1998-04-15 MOS-Logikschaltung und Halbleiterbauteil mit einer solchen

Country Status (6)

Country Link
US (2) US6144227A (de)
EP (2) EP0872958B1 (de)
JP (1) JP3178799B2 (de)
KR (1) KR100324940B1 (de)
DE (2) DE69809623T2 (de)
TW (1) TW451554B (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3519001B2 (ja) 1998-10-15 2004-04-12 シャープ株式会社 ラッチ回路およびフリップフロップ回路
JP2001036388A (ja) * 1999-07-16 2001-02-09 Sharp Corp レベルシフト回路および半導体装置
IT1313847B1 (it) * 1999-11-25 2002-09-24 St Microelectronics Srl Decodificatore per memorie avente configurazione ottimizzata.
JP2001186007A (ja) 1999-12-24 2001-07-06 Sharp Corp 金属酸化膜半導体トランジスタ回路およびそれを用いた半導体集積回路
JP2003101407A (ja) * 2001-09-21 2003-04-04 Sharp Corp 半導体集積回路
US7196369B2 (en) * 2002-07-15 2007-03-27 Macronix International Co., Ltd. Plasma damage protection circuit for a semiconductor device
US7256622B2 (en) * 2004-12-08 2007-08-14 Naveen Dronavalli AND, OR, NAND, and NOR logical gates
US7170816B2 (en) * 2004-12-16 2007-01-30 Macronix International Co., Ltd. Method and apparatus for passing charge from word lines during manufacture
JP2007019811A (ja) * 2005-07-07 2007-01-25 Oki Electric Ind Co Ltd ドミノｃｍｏｓ論理回路
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7750682B2 (en) * 2008-03-10 2010-07-06 International Business Machines Corporation CMOS back-gated keeper technique
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG192532A1 (en) 2008-07-16 2013-08-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9490249B2 (en) 2014-04-30 2016-11-08 Macronix International Co., Ltd. Antenna effect discharge circuit and manufacturing method
TWI703727B (zh) * 2019-03-20 2020-09-01 立積電子股份有限公司 積體電路

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140725A (ja) * 1983-01-31 1984-08-13 Nec Corp 論理回路
NL8801119A (nl) * 1988-04-29 1989-11-16 Philips Nv Logische geintegreerde schakeling met transmissiepoorten met lage drempelspanning.
JPH02283123A (ja) * 1989-04-25 1990-11-20 Seiko Epson Corp 半導体装置
US5200907A (en) * 1990-04-16 1993-04-06 Tran Dzung J Transmission gate logic design method
US5399921A (en) * 1993-12-14 1995-03-21 Dobbelaere; Ivo J. Dynamic complementary pass-transistor logic circuit
JP3246816B2 (ja) * 1993-12-16 2002-01-15 株式会社日立製作所 論理回路の構成方法
EP0739097B1 (de) * 1995-04-21 2004-04-07 Nippon Telegraph And Telephone Corporation MOSFET Schaltung und ihre Anwendung in einer CMOS Logikschaltung
US5548231A (en) * 1995-06-02 1996-08-20 Translogic Technology, Inc. Serial differential pass gate logic design
JP3195203B2 (ja) * 1995-06-06 2001-08-06 株式会社東芝 半導体集積回路
JPH0964283A (ja) * 1995-08-30 1997-03-07 Kawasaki Steel Corp パストランジスタ論理回路
US5821778A (en) * 1996-07-19 1998-10-13 Texas Instruments Incorporated Using cascode transistors having low threshold voltages
JP3195256B2 (ja) * 1996-10-24 2001-08-06 株式会社東芝 半導体集積回路
JP3241619B2 (ja) * 1996-12-25 2001-12-25 シャープ株式会社 Ｃｍｏｓ論理回路

Also Published As

Publication number Publication date
JP3178799B2 (ja) 2001-06-25
EP0872958B1 (de) 2002-11-27
US6320423B1 (en) 2001-11-20
KR19980081498A (ko) 1998-11-25
EP0872958A2 (de) 1998-10-21
EP0872958A3 (de) 1999-09-15
EP1191695A3 (de) 2003-07-23
DE69833231D1 (de) 2006-04-06
EP1191695A2 (de) 2002-03-27
KR100324940B1 (ko) 2002-07-03
DE69809623D1 (de) 2003-01-09
DE69833231T2 (de) 2006-09-28
US6144227A (en) 2000-11-07
EP1191695B1 (de) 2006-01-18
TW451554B (en) 2001-08-21
JPH10294663A (ja) 1998-11-04

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