DE69804122D1 - Quellenseitig mit zwei auswahl-transistoren verbundene nand-schwebegatterspeicherzelle und programmierverfahren - Google Patents

Quellenseitig mit zwei auswahl-transistoren verbundene nand-schwebegatterspeicherzelle und programmierverfahren

Info

Publication number
DE69804122D1
DE69804122D1 DE69804122T DE69804122T DE69804122D1 DE 69804122 D1 DE69804122 D1 DE 69804122D1 DE 69804122 T DE69804122 T DE 69804122T DE 69804122 T DE69804122 T DE 69804122T DE 69804122 D1 DE69804122 D1 DE 69804122D1
Authority
DE
Germany
Prior art keywords
nand
memory cell
source side
selection transistors
cell connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69804122T
Other languages
English (en)
Other versions
DE69804122T2 (de
Inventor
Pau-Ling Chen
Buskirk Michael Van
Charles Hollmer
Quang Le
Shoichi C O Fujitsu L Kawamura
Chung-You Hu
Yu Sun
Sameer Haddad
Chi Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Fujitsu Ltd
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Advanced Micro Devices Inc filed Critical Fujitsu Ltd
Publication of DE69804122D1 publication Critical patent/DE69804122D1/de
Application granted granted Critical
Publication of DE69804122T2 publication Critical patent/DE69804122T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69804122T 1997-09-30 1998-04-10 Quellenseitig mit zwei auswahl-transistoren verbundene nand-schwebegatterspeicherzelle und programmierverfahren Expired - Lifetime DE69804122T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/940,674 US5912489A (en) 1996-06-18 1997-09-30 Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory
PCT/US1998/007289 WO1999017294A1 (en) 1997-09-30 1998-04-10 Dual source side polysilicon select gate structure and programming method

Publications (2)

Publication Number Publication Date
DE69804122D1 true DE69804122D1 (de) 2002-04-11
DE69804122T2 DE69804122T2 (de) 2002-10-31

Family

ID=25475235

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69804122T Expired - Lifetime DE69804122T2 (de) 1997-09-30 1998-04-10 Quellenseitig mit zwei auswahl-transistoren verbundene nand-schwebegatterspeicherzelle und programmierverfahren

Country Status (6)

Country Link
US (3) US5912489A (de)
EP (1) EP1019914B1 (de)
JP (1) JP2001518696A (de)
KR (1) KR100494377B1 (de)
DE (1) DE69804122T2 (de)
WO (1) WO1999017294A1 (de)

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US6879505B2 (en) * 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
US7221588B2 (en) * 2003-12-05 2007-05-22 Sandisk 3D Llc Memory array incorporating memory cells arranged in NAND strings
US20050128807A1 (en) * 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
JP4698605B2 (ja) 2004-11-30 2011-06-08 スパンション エルエルシー 半導体装置および半導体装置の制御方法
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KR100754894B1 (ko) * 2005-04-20 2007-09-04 삼성전자주식회사 더미 메모리 셀을 가지는 낸드 플래시 메모리 장치
US7196930B2 (en) * 2005-04-27 2007-03-27 Micron Technology, Inc. Flash memory programming to reduce program disturb
US7295478B2 (en) * 2005-05-12 2007-11-13 Sandisk Corporation Selective application of program inhibit schemes in non-volatile memory
JP2007060544A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc 温度係数が小さいパワー・オン・リセットを生成する方法及び装置
JP2007058772A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc バンド・ギャップ基準から可変出力電圧を生成する方法及び装置
JP2007059024A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc 温度補償された読み出し・検証動作をフラッシュ・メモリにおいて生成するための方法及び装置
US7394693B2 (en) * 2005-08-31 2008-07-01 Micron Technology, Inc. Multiple select gate architecture
US7433231B2 (en) * 2006-04-26 2008-10-07 Micron Technology, Inc. Multiple select gates with non-volatile memory cells
US7489556B2 (en) * 2006-05-12 2009-02-10 Micron Technology, Inc. Method and apparatus for generating read and verify operations in non-volatile memories
US7616490B2 (en) * 2006-10-17 2009-11-10 Sandisk Corporation Programming non-volatile memory with dual voltage select gate structure
US7696035B2 (en) * 2006-11-13 2010-04-13 Sandisk Corporation Method for fabricating non-volatile memory with boost structures
US7508703B2 (en) * 2006-11-13 2009-03-24 Sandisk Corporation Non-volatile memory with boost structures
WO2008063970A2 (en) * 2006-11-13 2008-05-29 Sandisk Corporation Operation nand non-volatile memory with boost electrodes
US7508710B2 (en) * 2006-11-13 2009-03-24 Sandisk Corporation Operating non-volatile memory with boost structures
KR100790823B1 (ko) * 2006-12-14 2008-01-03 삼성전자주식회사 리드 디스터브를 개선한 불휘발성 반도체 메모리 장치
US8208305B2 (en) * 2009-12-23 2012-06-26 Intel Corporation Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources lines
US8659944B2 (en) * 2010-09-01 2014-02-25 Macronix International Co., Ltd. Memory architecture of 3D array with diode in memory string
JP2013246844A (ja) 2012-05-24 2013-12-09 Toshiba Corp 不揮発性半導体記憶装置
US9159406B2 (en) 2012-11-02 2015-10-13 Sandisk Technologies Inc. Single-level cell endurance improvement with pre-defined blocks
US9224474B2 (en) 2013-01-09 2015-12-29 Macronix International Co., Ltd. P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US9076535B2 (en) 2013-07-08 2015-07-07 Macronix International Co., Ltd. Array arrangement including carrier source
US9117526B2 (en) 2013-07-08 2015-08-25 Macronix International Co., Ltd. Substrate connection of three dimensional NAND for improving erase performance
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721964B2 (en) 2014-06-05 2017-08-01 Macronix International Co., Ltd. Low dielectric constant insulating material in 3D memory
US11211399B2 (en) 2019-08-15 2021-12-28 Micron Technology, Inc. Electronic apparatus with an oxide-only tunneling structure by a select gate tier, and related methods

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JP3004043B2 (ja) * 1990-10-23 2000-01-31 株式会社東芝 不揮発性半導体メモリ装置
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KR960006722B1 (ko) * 1993-03-12 1996-05-22 삼성전자주식회사 낸드형 쎌구조를 가지는 불휘발성 반도체집적회로
JP3207592B2 (ja) * 1993-03-19 2001-09-10 株式会社東芝 不揮発性半導体記憶装置
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KR0145475B1 (ko) * 1995-03-31 1998-08-17 김광호 낸드구조를 가지는 불휘발성 반도체 메모리의 프로그램장치 및 방법
KR0170296B1 (ko) * 1995-09-19 1999-03-30 김광호 비휘발성 메모리소자
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KR0170714B1 (ko) * 1995-12-20 1999-03-30 김광호 낸드형 플래쉬 메모리 소자 및 그 구동방법
US5793677A (en) * 1996-06-18 1998-08-11 Hu; Chung-You Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
US5912489A (en) * 1996-06-18 1999-06-15 Advanced Micro Devices, Inc. Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory
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KR100255957B1 (ko) * 1997-07-29 2000-05-01 윤종용 전기적으로 소거 및 프로그램 가능한 메모리 셀들을 구비한반도체 메모리 장치

Also Published As

Publication number Publication date
US5999452A (en) 1999-12-07
EP1019914A1 (de) 2000-07-19
WO1999017294A1 (en) 1999-04-08
EP1019914B1 (de) 2002-03-06
US6266275B1 (en) 2001-07-24
DE69804122T2 (de) 2002-10-31
US5912489A (en) 1999-06-15
KR100494377B1 (ko) 2005-06-10
KR20010015679A (ko) 2001-02-26
JP2001518696A (ja) 2001-10-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU LTD., KAWASAKI, KANAGAWA, JP

Owner name: SPANSION LLC ((N.D.GES.D. STAATES DELAWARE), SUNNY

8327 Change in the person/name/address of the patent owner

Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SUNNYV