DE69126268T2 - Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärken, angesteuert durch ein Speisespannungseinschaltrücksetzsignal - Google Patents

Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärken, angesteuert durch ein Speisespannungseinschaltrücksetzsignal

Info

Publication number
DE69126268T2
DE69126268T2 DE69126268T DE69126268T DE69126268T2 DE 69126268 T2 DE69126268 T2 DE 69126268T2 DE 69126268 T DE69126268 T DE 69126268T DE 69126268 T DE69126268 T DE 69126268T DE 69126268 T2 DE69126268 T2 DE 69126268T2
Authority
DE
Germany
Prior art keywords
driven
power
memory device
semiconductor memory
reset signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69126268T
Other languages
English (en)
Other versions
DE69126268D1 (de
Inventor
William Carl Slemmer
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69126268D1 publication Critical patent/DE69126268D1/de
Application granted granted Critical
Publication of DE69126268T2 publication Critical patent/DE69126268T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE69126268T 1990-09-26 1991-09-23 Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärken, angesteuert durch ein Speisespannungseinschaltrücksetzsignal Expired - Fee Related DE69126268T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/588,600 US5124951A (en) 1990-09-26 1990-09-26 Semiconductor memory with sequenced latched row line repeaters

Publications (2)

Publication Number Publication Date
DE69126268D1 DE69126268D1 (de) 1997-07-03
DE69126268T2 true DE69126268T2 (de) 1997-12-11

Family

ID=24354530

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69126268T Expired - Fee Related DE69126268T2 (de) 1990-09-26 1991-09-23 Halbleiterspeicheranordnung mit verriegelten Zeilenleitungszwischenverstärken, angesteuert durch ein Speisespannungseinschaltrücksetzsignal

Country Status (5)

Country Link
US (1) US5124951A (de)
EP (1) EP0478254B1 (de)
JP (1) JPH05266669A (de)
KR (1) KR920006978A (de)
DE (1) DE69126268T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04106784A (ja) * 1990-08-28 1992-04-08 Fujitsu Ltd 半導体集積回路
US5258952A (en) * 1990-12-14 1993-11-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with separate time-out control for read and write operations
US5245584A (en) * 1990-12-20 1993-09-14 Vlsi Technology, Inc. Method and apparatus for compensating for bit line delays in semiconductor memories
US5566127A (en) * 1992-01-15 1996-10-15 Motorola, Inc. Method for building a compiled static RAM
JP2725570B2 (ja) * 1993-11-02 1998-03-11 日本電気株式会社 半導体メモリ装置
KR960009955B1 (en) * 1994-02-07 1996-07-25 Hyundai Electronics Ind Semiconductor memory device
US5783958A (en) * 1996-01-19 1998-07-21 Sgs-Thomson Microelectronics, Inc. Switching master slave circuit
JPH09231764A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc バーストカウンタ回路及びその動作方法
JP3173387B2 (ja) * 1996-09-20 2001-06-04 日本電気株式会社 半導体記憶装置及びデコード回路
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
US5784331A (en) * 1996-12-31 1998-07-21 Sgs-Thomson Microelectronics, Inc. Multiple access memory device
US5835441A (en) * 1997-08-21 1998-11-10 Micron Technology, Inc. Column select latch for SDRAM
EP0991191B1 (de) * 1998-09-09 2003-07-30 Texas Instruments Incorporated Verfahren und Vorrichtung zur Reduzierung der Verlustleistung in einer Schaltung
US6115310A (en) * 1999-01-05 2000-09-05 International Business Machines Corporation Wordline activation delay monitor using sample wordline located in data-storing array
US6185135B1 (en) 1999-01-05 2001-02-06 International Business Machines Corporation Robust wordline activation delay monitor using a plurality of sample wordlines
US7124221B1 (en) 1999-10-19 2006-10-17 Rambus Inc. Low latency multi-level communication interface
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US6690198B2 (en) * 2002-04-02 2004-02-10 Infineon Technologies Ag Repeater with reduced power consumption
US6678200B2 (en) * 2002-05-14 2004-01-13 Hewlett-Packard Development Company, Lp. Systems and methods for communicating with memory blocks
GB2409776B (en) * 2002-05-14 2005-10-12 Hewlett Packard Co Systems and methods for communicating with memory blocks
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) * 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
KR100613448B1 (ko) * 2004-10-07 2006-08-21 주식회사 하이닉스반도체 데이터 가속회로 및 이를 이용한 데이터 전송회로
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7557604B2 (en) * 2005-05-03 2009-07-07 Oki Semiconductor Co., Ltd. Input circuit for mode setting
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
KR100842743B1 (ko) * 2006-10-27 2008-07-01 주식회사 하이닉스반도체 고집적 반도체 장치
JP5240056B2 (ja) * 2009-05-12 2013-07-17 富士通セミコンダクター株式会社 半導体メモリおよびシステム
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US11100966B2 (en) * 2020-01-09 2021-08-24 Winbond Electronics Corp. Array edge repeater in memory device
KR102324988B1 (ko) * 2020-02-05 2021-11-11 윈본드 일렉트로닉스 코포레이션 메모리 장치의 어레이 에지 리피터

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents
JPS5894187A (ja) * 1981-11-28 1983-06-04 Mitsubishi Electric Corp 半導体記憶装置
JPS5940393A (ja) * 1982-08-31 1984-03-06 Nec Corp メモリ回路
JPS62180607A (ja) * 1986-02-04 1987-08-07 Fujitsu Ltd 半導体集積回路
US5008856A (en) * 1987-06-29 1991-04-16 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
JPH0194592A (ja) * 1987-10-06 1989-04-13 Fujitsu Ltd 半導体メモリ

Also Published As

Publication number Publication date
KR920006978A (ko) 1992-04-28
US5124951A (en) 1992-06-23
EP0478254A2 (de) 1992-04-01
EP0478254B1 (de) 1997-05-28
DE69126268D1 (de) 1997-07-03
EP0478254A3 (en) 1993-06-16
JPH05266669A (ja) 1993-10-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee