DE69033229T2 - Anschlussfläche für Halbleiteranordnung - Google Patents

Anschlussfläche für Halbleiteranordnung

Info

Publication number
DE69033229T2
DE69033229T2 DE69033229T DE69033229T DE69033229T2 DE 69033229 T2 DE69033229 T2 DE 69033229T2 DE 69033229 T DE69033229 T DE 69033229T DE 69033229 T DE69033229 T DE 69033229T DE 69033229 T2 DE69033229 T2 DE 69033229T2
Authority
DE
Germany
Prior art keywords
terminal area
semiconductor arrangement
semiconductor
arrangement
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033229T
Other languages
English (en)
Other versions
DE69033229D1 (de
Inventor
Seiichi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69033229D1 publication Critical patent/DE69033229D1/de
Application granted granted Critical
Publication of DE69033229T2 publication Critical patent/DE69033229T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
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    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2924/0001—Technical content checked by a classifier
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DE69033229T 1989-04-27 1990-04-26 Anschlussfläche für Halbleiteranordnung Expired - Fee Related DE69033229T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1105912A JPH02285638A (ja) 1989-04-27 1989-04-27 半導体装置

Publications (2)

Publication Number Publication Date
DE69033229D1 DE69033229D1 (de) 1999-09-09
DE69033229T2 true DE69033229T2 (de) 1999-12-16

Family

ID=14420077

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033229T Expired - Fee Related DE69033229T2 (de) 1989-04-27 1990-04-26 Anschlussfläche für Halbleiteranordnung

Country Status (5)

Country Link
US (1) US5036383A (de)
EP (1) EP0395072B1 (de)
JP (1) JPH02285638A (de)
KR (1) KR930010981B1 (de)
DE (1) DE69033229T2 (de)

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JP2616227B2 (ja) * 1990-11-24 1997-06-04 日本電気株式会社 半導体装置
JP2765673B2 (ja) * 1992-06-04 1998-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション メタライゼーション層及びその形成方法
US5316976A (en) * 1992-07-08 1994-05-31 National Semiconductor Corporation Crater prevention technique for semiconductor processing
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US5249728A (en) * 1993-03-10 1993-10-05 Atmel Corporation Bumpless bonding process having multilayer metallization
JP2944840B2 (ja) * 1993-03-12 1999-09-06 株式会社日立製作所 電力用半導体装置
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice
US5483105A (en) * 1994-04-25 1996-01-09 International Business Machines Corporation Module input-output pad having stepped set-back
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
KR100475734B1 (ko) * 1997-10-14 2005-06-23 삼성전자주식회사 와이어본딩충격에대한완충특성을갖는반도체장치의패드및그제조방법
US7804115B2 (en) 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
KR100350936B1 (ko) 1998-02-25 2002-08-30 시티즌 도케이 가부시키가이샤 반도체 장치
JP3121311B2 (ja) * 1998-05-26 2000-12-25 日本電気株式会社 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法
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JPH02285638A (ja) 1990-11-22
DE69033229D1 (de) 1999-09-09
EP0395072A3 (de) 1991-07-17
EP0395072A2 (de) 1990-10-31
EP0395072B1 (de) 1999-08-04
US5036383A (en) 1991-07-30
KR930010981B1 (ko) 1993-11-18
KR900017136A (ko) 1990-11-15

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