KR930010981B1 - 반도체장치 - Google Patents

반도체장치 Download PDF

Info

Publication number
KR930010981B1
KR930010981B1 KR1019900005982A KR900005982A KR930010981B1 KR 930010981 B1 KR930010981 B1 KR 930010981B1 KR 1019900005982 A KR1019900005982 A KR 1019900005982A KR 900005982 A KR900005982 A KR 900005982A KR 930010981 B1 KR930010981 B1 KR 930010981B1
Authority
KR
South Korea
Prior art keywords
film
polysilicon
bonding pad
layer
semiconductor device
Prior art date
Application number
KR1019900005982A
Other languages
English (en)
Other versions
KR900017136A (ko
Inventor
세이치 모리
Original Assignee
가부시키가이샤 도시바
아오이 죠이치
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바, 아오이 죠이치 filed Critical 가부시키가이샤 도시바
Publication of KR900017136A publication Critical patent/KR900017136A/ko
Application granted granted Critical
Publication of KR930010981B1 publication Critical patent/KR930010981B1/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

내용 없음.

Description

반도체장치
제1a도는 본 발명의 제1실시예에 따른 본딩패드부의 구조를 나타낸 단면도.
제2b도는 본 발명의 제2실시예에 따른 본딩패드부의 구조를 나타낸 단면도.
제2도는 종래의 본딩패드의 구조를 나타낸 단면도.
제3도는 본 발명의 제1, 제2실시예 및 종래예에 있어서 초음파본딩을 행한 때의 크랙발생빈도 및 전기적 리크발생빈도의 상대비교도.
* 도면의 주요부분에 대한 부호의 설명
101, 201 : 실리콘기판 102,202 : 필드 산화막
103 : 폴리실리콘막(제1층의 게이트재료) 104 : ONO 절연막
1051: 폴리실리콘막
1052: MoSi막(제2층의 게이트재료)
106, 203 : 장벽금속층 107, 204 : 금속전극층
108 : 층간절연막 109, 205 : 패시베이션막
110 : 폴리실리콘막(제3층의 재료) 120, 206 : 본딩와이어
[산업상의 이용분야]
본 발명은 반도체장치에 관한 것으로, 특히 본딩패드의 구조에 관한 것이다.
[종래의 기술 및 그 문제점]
일반적으로, 반도체기판내에 형성된 소자의 전기적 특성을 외부로 취출하기 위해 소자들을 결선하고 있는 전극배선에 금속선을 본딩시키는 부분을 본딩패드라 한다.
이하, 도면을 참조해서 본딩패드의 구조를 설명한다.
제2도는 종래의 본딩패드의 구조를 나타낸 단면도로서, 이 제2도에 도시된 바와같이 Si 기판(201)상에 형성된 절연산화막(202 ; 필드산화막)상에 본딩패드를 형성한다. 본딩패드는 통상 배선구조와 동일하기 때문에 장벽금속층(203) 및 금속전극(204)으로 구성되고, 그 주위에 패시베이션(passivation)막(205)이 형성되어 있다. 그리고 이 본딩패드(203,204)에 와어어(206)를 본딩한다. 이 경우, 장벽금속층(203)으로는 예컨대 Ti층이 사용되고, 금속전극(204)으로는 Al 또는 Al합금(Al-Si-Cu 등)이 사용된다.
그런데, 상기와 같은 구조에서는 본딩패드(203,204)과 실리콘기판(201)간에 존재하는 절연산화막(202)의 기계적인 강도가 부족하기 때문에 와이어본딩할 때 이 절연산화막(202)에 크랙(207)이 발생하게 되어, 반도체장치를 동작시키기 위해 외부로부터 본딩패드(203,204)와 실리콘기판(201)간에 리크(leak)전류가 생길 우려가 있었다.
즉, 상기한 바와같은 종래의 반도체장치의 본딩패딩구조에서는, 본딩패드와 반도체기판간에 존재하는 막의 기계적 강도가 낮기 때문에 와이어본딩할 때 크랙이 발생하게 됨으로써, 리크전류가 생겨 반도체장치의 신뢰성이 저하된다고 하는 문제가 있었다.
[발명의 목적]
이에 본 발명은 상술한 문제를 고려해서 발명된 것으로, 본딩패드부의 전기적 내입을 향상시켜 신뢰성 높은 반도체장치를 제공하고자 함에 그 목적이 있다.
[발명의 구성]
상기 목적을 달성하기 위해 본 발명의 반도체장치는, 반도체기판과, 이 반도체기판상에 형성된 절연막, 이 절연막상에 형성되어 본딩패드로서 이용되는 금속전극층 및, 이 금속전극층에 접속된 본딩와이어를 갖춘 반도체장치에 있어서, 상기 절연막과 상기 금속전극층간에 제1폴리실리콘막과, 제1산화막과 이 제1산화막상에 형성된 질화막 및 이 질화막상에 형성된 제2산화막을 구비한 복합막 및, 이 복합막상에 형성된 제2폴리실리콘막을 더 갖춘 것을 특징으로 한다.
[작용]
상기와 같이 구성된 본 발명의 본딩패딩구조에서는, 반도체기판과 금속전극층간에 산화막 및 질화막으로 구성된 전기적 내압성이 높은 경질(硬質)의 복합막과 연질(軟質)의 폴리실리콘막을 설치함으로써, 기계적 강도가 향상된다.
[실시예]
이하, 도면을 참조해서 본 발명의 실시예를 상세히 설명한다.
제1도(a)는 본 발명의 제1실시예에 따른 본딩패드부의 구조를 나타낸 단면도이다. 이 제1도(a)에 도시된 바와같이 본 발명의 제1실시예에 다른 본딩패드부는 예컨대 EPROM(Electrically Programmable Read Only Memory ; 전기적으로 프로그램이 가능한 독출전용 메모리)과 같은 2층 게이트구조의 디바이스로서, 실리콘기판(101)상에 절연산화막(102 ; 필드산화막)이 예컨대 5000Å정도 형성되어 있고, 그 상부에 EPROM의 부유게이트(제1층의 게이트재료)로 사용되는 폴리실리콘막(103)이 예컨대 2000Å정도 형성되어 있다. 더욱이, 그 상부에 폴리실리콘층간막으로서 산화막-질화막-산화막(Oxide-Nitride-Oxide)의 3층 절연막(104 ; 이하, ONO 절연막이라 칭한다)이 형성되어 있고, 그 상부에 EPROM의 제어게이트(제2층의 게이트재료)로서 사용되는 폴리실리콘(1051) 및 MoSi막(1052)으로 이루어진 폴리사이드막(105)이 5000Å 정도 형성되어 있다.
이 폴리사이드막(105)상에 설치된 접속구멍(contact hole)에 Ti로 이루어진 장벽금속층(106)이 500Å정도 형성되고, 그 상부에 Al로 이루어진 금속전극층(107)이 8000Å정도 형성된 2층 금속배선구조로 되어 있다. 본딩패드는 이 장벽금속층(106) 및 금속전극층(107)으로 구성된다. 또, 이 본딩패드(106,107)를 둘러싸도록 층간절연막(108) 및 패시베이션막(109)이 설치되어 있고, 이 본딩패드(106,107)에 와이어(120)가 접속되어 있다. 이 경우, 층간절연막(108)으로서는 예컨대 PSG막 또는 BPSG막 등이 사용되고, 패시베이션막(109)으로는 PSG막 또는 SiN막이 사용되고 있다.
이 실시예의 본딩패드구조에 의하면, 2층의 폴리실리콘층(103,1051)간에 사용된 ONO 절연막(104)은 경질의 막으로서, 이 막에 연질의 폴리실리콘막을 조합시킴으로써 본딩패드(106,107)와 기판(101)간의 기계적 강도를 보다 높일 수 있게 되고, 그에 따라 크랙이 발생할 위험성을 억제하여 리크전류를 방지할 수 있게 된다. 또, ONO 절연막(104)은 절연내압이 매우 높은 막으로서, 가령 크랙이 아랫쪽의 산화막에 발생하더라도 ONO막(104)에는 크랙이 발생하지 않게 되므로, 이 ONO 절연막(104)에 의해 절연성을 확보할 수 있게 된다. 따라서, 신뢰성 높은 반도체장치를 얻을 수 있게 된다.
또, 본딩패드(106,107)의 아래에 2층의 폴리실리콘층(103,1051)을 적층함으로써 막두께를 두껍게 해서 기계적 강도를 증가시켜 와이어본딩시에 크랙발생을 방지함과 더불어 크랙으로의 수분이나 가동이온(可動 ion)등의 불순물이 침입하는 것을 방지할 수 있게 된다.
제1도(b)는 본 발명의 제2실시예에 따른 본딩패드부의 구조를 나타낸 단면도이다. 이 제1도(b)에 도시된 바와같이 본 발명의 제2실시예에 따른 본딩패드부는 제1실시예의 본딩패드부의 기계적 강도를 더욱 증대시킨 것으로, 실리콘기판(101)상에 순차적으로 적층된 절연산화막(102 ; 필드산화막), 폴리실리콘막(103), ONO 절연막(104), MoSi 폴리사이드막(105)까지는 제1실시예의 구조와 동일하지만, 더욱이 그 상부에 PSG막 또는 BPSG막으로 이루어진 층간절연막(108)이 형성되며, 이 층간절연막(108)의 상부에 제3층의 재료로서 예컨대 폴리실리콘층(110)이 1000Å정도 형성되며 그 위에 Ti로 이루어진 장벽금속층(106) 및 Al로 이루어진 금속전극층(107)의 2층의 금속배선층이 형성된 구조로 되어 있다.
본 발명의 제2실시예에서는, 제1실시예와 마찬가지로 2층의 연질의 폴리실리콘층(103,1051)과 이들 층간에 사용된 결질의 ONO 절연막(104)의 조합에 의해 본딩패드(106,107)와 기판(101)간의 기계적 강도를 높일 수 있게 되고, 그에 따라 크랙발생의 위험성을 억제하여 리크전류를 방지할 수 있게 된다. 또, 전기적 내압성이 높은 막인 ONO 절연막(104)에 의해 확보할 수 있게 된다. 따라서, 신회성 높은 반도체 장치를 얻을 수 있게 된다.
또, 본딩패드의 아래에 2층의 폴리실리콘층(103,1051)을 적층하고, 그 위에 층간절연막(108)과 그 상부의 폴리실리콘층(110)을 설치함으로써, 막두께를 두껍게 해서 기계적 강도를 보다 높일 수 있게 되고, 그에 다라 와이어본딩시의 크랙발생을 방지할 수 있게 된다.
제3도는 본 발명의 제1, 제2실시예 및 종래예에 있어서 초음파본딩을 행한 때의 본딩패드와 반도체기판간에 존재하는 막에서의 크랙발생빈도 및 본딩패드에 전압을 인가한 때 본딩패드와 반도체기판간에서 생기는 전기적 리크의 발생빈도의 상대비교를 나타낸 도면이다. 종축은 크랙발생 및 전기적 리크발생의 빈도를 나타내고 있는바, 종래예를 1로 하였다. 제1실시예의 경우, 크랙발생빈도는 0.5로 되어 종래예의 반으로 감소되고, 전기적 리크의 발생빈도는 0이다. 제2실시예의 경우에서는, 크랙발생빈도 및 전기적 리크발생빈도가 모두 0으로 되어 있다. 이로부터, 본 발명의 실시예에 의하면 종래예에 비해 본딩패드부의 전기적 내압이 높아지는 것을 알 수 있으며, 특히 제2실시예에서는 전기적 내압이 보다 높아지는 것을 알 수 있다. 이 제2실시예에 따른 본딩패드구조에서는, 상기 제1실시예에 비해 층간절연막(108)과 제3층의 재료인 폴리실리콘막(110)이 설치됨으로써 막두께가 증가되어 보다 전기적 내압이 높아져서 신뢰성 높은 반도체장치를 얻을 수 있게 된다.
본 발명의 특징은, 특허청구의 범위 제1항에 기재된 바와같이 본딩패드의 아래에 질화막을 2개의 산화막으로 협지된 구조의 복합막을 설치하고, 더욱이 이 복합막을 2개의 폴리실리콘막으로 협지한 점에 있다. 상기 제1및 제2실시예는, 본 발명의 EPROM에 적용하고, EPROM의 부유게이트 형성공정 및 제어게이트 형성공정과 동일한 공정에서 상술한 2개의 폴리실리콘막을 형성하고 있다. 따라서, 상기 제1 및 제2실시예에 의하면, 공정을 추가하지 않고 본 발명을 실시할 수 있게 된다. 그렇지만, 본 발명은 EPROM만을 대상으로 하는 것이 아니라 본딩패드를 구비한 반도체장치 전반에 적용할 수 있는 것이다. 예컨대, 실리콘게이트 MOS트랜지스터를 갖춘 반도체장치에 본 발명을 적용하는 경우는, 상술한 2개의 폴리실리콘막의 한쪽을 트랜지스터의 게이트전극 형성공정과 동일한 공정에서 형성하는 것이 가능하다. 또, 폴리실리콘배선을 갖춘 반도체장치에 본 발명을 적용하는 경우는, 상술한 2개의 폴리실리콘막의 한쪽을 배선형성공정과 동일한 공정에서 형성하는 것이 가능하다. 또, 폴리실리콘층이 없는 반도체장치에 본 발명을 적용하는 경우는, 상술한 2개의 폴리실리콘막을 형성하기 위한 공정을 추가하면 좋다.
또한 상술한 실시예에서는 제1층, 제2층의 게이트재료 및 제3층의 재료가 폴리실리콘 또는 폴리사이드인 경우에 대해 설명했지만, 본 발명은 이에 한정되지 않는다. 더욱이, 제1층, 제2층, 제3층의 재료가 폴리사이드구조와 같이 2종류 이상의 층의 적층구조로 되어 있어서 좋다.
한편, 본 발명의 특허청구의 범위의 각 구성요건에 병기한 참조부호는 본 발명의 이해를 용이하게 하기 위한 것으로서, 본 발명의 기술적 범위를 도면에 도시된 실시예에 한정할 의도로 병기한 것은 아니다.
[발명의 효과]
이상에서 설명한 바와같이 본 발명의 본딩패드구조에 의하면, 본딩패드와 기판의 전기적 내압성을 높여 신뢰성 높은 반도체장치를 얻을 수 있게 된다.

Claims (3)

  1. 반도체기판(101)과, 이 반도체기판(101)상에 형성된 절연막(102), 이 절연막(102)상에 형성되어 본딩패드로서 이용되는 금속전극층(106,107) 및, 이 금속전극층(106,107)에 접속된 본딩와이어(120)를 갖춘 반도체장치에 있어서, 상기 절연막(102)과 상기 금속전극층(106,107)간에 제1폴리실리콘막(103)과, 제1산화막과 이 제1산화막상에 형성된 질화막 및 이 질화막상에 형성된 제2산화막을 구비한 복합막(104) 및, 이 복합막(104)상에 형성된 제2폴리실리콘막(1051)을 더 갖춘 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 금속전극층(106,107)과 상기 제2폴리실리콘막(1051)간에 고용된 금속막 또는 고융점 금속실리사이드로 이루어지는 막(1052)을 더 갖춘 것을 특징으로 한느 반도체장치.
  3. 제2항에 있어서, 상기 막(1052)과 상기 금속전극층(106,107)간에 층간절연막(108)을 더 갖춘 것을 특징으로 하는 반도체장치.
KR1019900005982A 1989-04-27 1990-04-27 반도체장치 KR930010981B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP01-105912 1989-04-27
JP1105912A JPH02285638A (ja) 1989-04-27 1989-04-27 半導体装置

Publications (2)

Publication Number Publication Date
KR900017136A KR900017136A (ko) 1990-11-15
KR930010981B1 true KR930010981B1 (ko) 1993-11-18

Family

ID=14420077

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900005982A KR930010981B1 (ko) 1989-04-27 1990-04-27 반도체장치

Country Status (5)

Country Link
US (1) US5036383A (ko)
EP (1) EP0395072B1 (ko)
JP (1) JPH02285638A (ko)
KR (1) KR930010981B1 (ko)
DE (1) DE69033229T2 (ko)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5180623A (en) * 1989-12-27 1993-01-19 Honeywell Inc. Electronic microvalve apparatus and fabrication
JP2616227B2 (ja) * 1990-11-24 1997-06-04 日本電気株式会社 半導体装置
JP2765673B2 (ja) * 1992-06-04 1998-06-18 インターナショナル・ビジネス・マシーンズ・コーポレイション メタライゼーション層及びその形成方法
US5316976A (en) * 1992-07-08 1994-05-31 National Semiconductor Corporation Crater prevention technique for semiconductor processing
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US5249728A (en) * 1993-03-10 1993-10-05 Atmel Corporation Bumpless bonding process having multilayer metallization
JP2944840B2 (ja) * 1993-03-12 1999-09-06 株式会社日立製作所 電力用半導体装置
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice
US5483105A (en) * 1994-04-25 1996-01-09 International Business Machines Corporation Module input-output pad having stepped set-back
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5661081A (en) * 1994-09-30 1997-08-26 United Microelectronics Corporation Method of bonding an aluminum wire to an intergrated circuit bond pad
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
KR100475734B1 (ko) * 1997-10-14 2005-06-23 삼성전자주식회사 와이어본딩충격에대한완충특성을갖는반도체장치의패드및그제조방법
CN1148794C (zh) * 1998-02-25 2004-05-05 时至准钟表股份有限公司 半导体装置
US7804115B2 (en) 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
JP3121311B2 (ja) * 1998-05-26 2000-12-25 日本電気株式会社 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法
US6268282B1 (en) * 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6037668A (en) 1998-11-13 2000-03-14 Motorola, Inc. Integrated circuit having a support structure
US6191481B1 (en) 1998-12-18 2001-02-20 Philips Electronics North America Corp. Electromigration impeding composite metallization lines and methods for making the same
US6020647A (en) * 1998-12-18 2000-02-01 Vlsi Technology, Inc. Composite metallization structures for improved post bonding reliability
US8021976B2 (en) 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6828683B2 (en) * 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7235499B1 (en) * 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
JP3327244B2 (ja) * 1999-03-12 2002-09-24 日本電気株式会社 半導体装置
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
JP2001118927A (ja) * 1999-10-22 2001-04-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002076051A (ja) * 2000-09-01 2002-03-15 Nec Corp 半導体装置のボンディングパッド構造及びボンディング方法
US6440860B1 (en) * 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
KR100403619B1 (ko) * 2001-02-21 2003-10-30 삼성전자주식회사 열적/기계적 스트레스에 저항성이 강한 반도체 소자의 본드패드 및 그 형성방법
US6465895B1 (en) 2001-04-05 2002-10-15 Samsung Electronics Co., Ltd. Bonding pad structures for semiconductor devices and fabrication methods thereof
JP3943416B2 (ja) * 2002-03-07 2007-07-11 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3967199B2 (ja) * 2002-06-04 2007-08-29 シャープ株式会社 半導体装置及びその製造方法
JP3724464B2 (ja) * 2002-08-19 2005-12-07 株式会社デンソー 半導体圧力センサ
US6686665B1 (en) * 2002-09-04 2004-02-03 Zeevo, Inc. Solder pad structure for low temperature co-fired ceramic package and method for making the same
US20120299187A1 (en) * 2011-05-27 2012-11-29 Broadcom Corporation Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products
JP2016028417A (ja) 2014-07-11 2016-02-25 ローム株式会社 電子装置
DE102018105462A1 (de) 2018-03-09 2019-09-12 Infineon Technologies Ag Halbleitervorrichtung, die ein bondpad und einen bonddraht oder -clip enthält

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
US4136434A (en) * 1977-06-10 1979-01-30 Bell Telephone Laboratories, Incorporated Fabrication of small contact openings in large-scale-integrated devices
US4276557A (en) * 1978-12-29 1981-06-30 Bell Telephone Laboratories, Incorporated Integrated semiconductor circuit structure and method for making it
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
US4398335A (en) * 1980-12-09 1983-08-16 Fairchild Camera & Instrument Corporation Multilayer metal silicide interconnections for integrated circuits
JPS5921034A (ja) * 1982-07-27 1984-02-02 Toshiba Corp 半導体装置
US4613956A (en) * 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric
JPS59204276A (ja) * 1983-05-06 1984-11-19 Nec Corp 絶縁ゲ−ト電界効果半導体装置
US4823181A (en) * 1986-05-09 1989-04-18 Actel Corporation Programmable low impedance anti-fuse element
US4824803A (en) * 1987-06-22 1989-04-25 Standard Microsystems Corporation Multilayer metallization method for integrated circuits
JP2503022B2 (ja) * 1987-07-23 1996-06-05 三井東圧化学株式会社 ４▲’▼−ヒドロキシビフェニル−３−カルボン酸の製造方法
JP2735193B2 (ja) * 1987-08-25 1998-04-02 株式会社東芝 不揮発性半導体装置及びその製造方法
US4872050A (en) * 1988-03-15 1989-10-03 Mitsubishi Denki Kabushiki Kaisha Interconnection structure in semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
EP0395072A3 (en) 1991-07-17
JPH02285638A (ja) 1990-11-22
DE69033229T2 (de) 1999-12-16
DE69033229D1 (de) 1999-09-09
EP0395072B1 (en) 1999-08-04
EP0395072A2 (en) 1990-10-31
US5036383A (en) 1991-07-30
KR900017136A (ko) 1990-11-15

Similar Documents

Publication Publication Date Title
KR930010981B1 (ko) 반도체장치
US5023699A (en) Resin molded type semiconductor device having a conductor film
JP3354424B2 (ja) 半導体装置および半導体装置の製造方法
US6756675B1 (en) Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal
US6864562B1 (en) Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film
KR960002092B1 (ko) 반도체장치
US5468998A (en) Resin molded type semiconductor device having a conductor film
US11817427B2 (en) Semiconductor device having through silicon vias and manufacturing method thereof
KR20020053695A (ko) 반도체 장치
US6576970B2 (en) Bonding pad structure of semiconductor device and method for fabricating the same
US5229642A (en) Resin molded type semiconductor device having a conductor film
KR870000350B1 (ko) 다측 배선(多重配線)구조를 가진 전자장치(電子裝置)
JPH0194664A (ja) 電界効果トランジスタ
US20090184428A1 (en) Semiconductor device and method for manufacturing the same
US5552639A (en) Resin molded type semiconductor device having a conductor film
US20080185682A1 (en) High Voltage Metal-On-Passivation Capacitor
JPH031538A (ja) 半導体装置
JPS6018934A (ja) 半導体装置
CN100499125C (zh) 半导体装置
CN100590858C (zh) 半导体装置
JPH01130545A (ja) 樹脂封止型半導体装置
KR19990061338A (ko) 본딩 패드를 구비한 반도체 소자
JPH06349886A (ja) 半導体装置及びその製造方法
US7498194B2 (en) Semiconductor arrangement
KR100410708B1 (ko) 반도체장치 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20091028

Year of fee payment: 17

EXPY Expiration of term