DE69025916T2 - Herstellungsverfahren für eine halbleitervorrichtung - Google Patents

Herstellungsverfahren für eine halbleitervorrichtung

Info

Publication number
DE69025916T2
DE69025916T2 DE69025916T DE69025916T DE69025916T2 DE 69025916 T2 DE69025916 T2 DE 69025916T2 DE 69025916 T DE69025916 T DE 69025916T DE 69025916 T DE69025916 T DE 69025916T DE 69025916 T2 DE69025916 T2 DE 69025916T2
Authority
DE
Germany
Prior art keywords
cover
windows
silicon dioxide
semiconductor
dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025916T
Other languages
German (de)
English (en)
Other versions
DE69025916D1 (de
Inventor
Ewen Gillespie
Richard Rodrigues
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Microelectronics Ltd filed Critical Seagate Microelectronics Ltd
Publication of DE69025916D1 publication Critical patent/DE69025916D1/de
Application granted granted Critical
Publication of DE69025916T2 publication Critical patent/DE69025916T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W10/30—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H10P76/40—
    • H10W10/031—
    • H10W20/021—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/163—Thick-thin oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
DE69025916T 1989-10-04 1990-10-04 Herstellungsverfahren für eine halbleitervorrichtung Expired - Fee Related DE69025916T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8922331A GB2237445B (en) 1989-10-04 1989-10-04 A semiconductor device fabrication process
PCT/GB1990/001528 WO1991005365A1 (en) 1989-10-04 1990-10-04 A semiconductor device fabrication process

Publications (2)

Publication Number Publication Date
DE69025916D1 DE69025916D1 (de) 1996-04-18
DE69025916T2 true DE69025916T2 (de) 1996-09-26

Family

ID=10664022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025916T Expired - Fee Related DE69025916T2 (de) 1989-10-04 1990-10-04 Herstellungsverfahren für eine halbleitervorrichtung

Country Status (7)

Country Link
US (1) US5679586A (enExample)
EP (1) EP0447522B1 (enExample)
JP (1) JPH0732164B2 (enExample)
DE (1) DE69025916T2 (enExample)
GB (1) GB2237445B (enExample)
SG (1) SG72609A1 (enExample)
WO (1) WO1991005365A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6017785A (en) * 1996-08-15 2000-01-25 Integrated Device Technology, Inc. Method for improving latch-up immunity and interwell isolation in a semiconductor device
US6001701A (en) * 1997-06-09 1999-12-14 Lucent Technologies Inc. Process for making bipolar having graded or modulated collector
KR100374243B1 (ko) * 1998-10-08 2003-03-03 미쓰비시덴키 가부시키가이샤 반도체장치 및 그의 제조방법과 반도체장치 보호회로
US6716363B1 (en) 1999-04-20 2004-04-06 Seagate Technology Llc Electrode patterning for a differential PZT activator

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE72967C (de) * TH. HELLER in Berlin S.O., Obmgasse 5 a Form zur Herstellung von Glasstöpseln für Tropfgläser
DE244607C (enExample) *
US3928081A (en) * 1973-10-26 1975-12-23 Signetics Corp Method for fabricating semiconductor devices using composite mask and ion implantation
US3928082A (en) * 1973-12-28 1975-12-23 Texas Instruments Inc Self-aligned transistor process
US3933528A (en) * 1974-07-02 1976-01-20 Texas Instruments Incorporated Process for fabricating integrated circuits utilizing ion implantation
US4151019A (en) * 1974-12-27 1979-04-24 Tokyo Shibaura Electric Co., Ltd. Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques
US4018627A (en) * 1975-09-22 1977-04-19 Signetics Corporation Method for fabricating semiconductor devices utilizing oxide protective layer
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
JPS57157541A (en) * 1981-03-24 1982-09-29 Toshiba Corp Manufacture of semiconductor device
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
DE3133468A1 (de) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen in siliziumgate-technologie
JPS5955054A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体装置の製造方法
JPS60175451A (ja) * 1984-02-20 1985-09-09 Matsushita Electronics Corp 半導体装置の製造方法
US4577391A (en) * 1984-07-27 1986-03-25 Monolithic Memories, Inc. Method of manufacturing CMOS devices
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4717678A (en) * 1986-03-07 1988-01-05 International Business Machines Corporation Method of forming self-aligned P contact
JPH0812918B2 (ja) * 1986-03-28 1996-02-07 株式会社東芝 半導体装置の製造方法
US4760033A (en) * 1986-04-08 1988-07-26 Siemens Aktiengesellschaft Method for the manufacture of complementary MOS field effect transistors in VLSI technology
US5141881A (en) * 1989-04-20 1992-08-25 Sanyo Electric Co., Ltd. Method for manufacturing a semiconductor integrated circuit
JPH06101540B2 (ja) * 1989-05-19 1994-12-12 三洋電機株式会社 半導体集積回路の製造方法

Also Published As

Publication number Publication date
JPH0732164B2 (ja) 1995-04-10
DE69025916D1 (de) 1996-04-18
EP0447522A1 (en) 1991-09-25
US5679586A (en) 1997-10-21
EP0447522B1 (en) 1996-03-13
GB2237445A (en) 1991-05-01
GB2237445B (en) 1994-01-12
JPH0732164B1 (enExample) 1995-04-10
GB8922331D0 (en) 1989-11-22
SG72609A1 (en) 2000-09-19
WO1991005365A1 (en) 1991-04-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: DERZEIT KEIN VERTRETER BESTELLT

8327 Change in the person/name/address of the patent owner

Owner name: SEAGATE TECHNOLOGY, INC. (N.D.GES.D.STAATES DELAWA

8327 Change in the person/name/address of the patent owner

Owner name: SEAGATE TECHNOLOGY LLC, SCOTTS VALLEY, CALIF., US

8339 Ceased/non-payment of the annual fee