DE60227475D1 - Halbleiterbauelement - Google Patents

Halbleiterbauelement

Info

Publication number
DE60227475D1
DE60227475D1 DE60227475T DE60227475T DE60227475D1 DE 60227475 D1 DE60227475 D1 DE 60227475D1 DE 60227475 T DE60227475 T DE 60227475T DE 60227475 T DE60227475 T DE 60227475T DE 60227475 D1 DE60227475 D1 DE 60227475D1
Authority
DE
Germany
Prior art keywords
semiconductor component
semiconductor
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60227475T
Other languages
English (en)
Inventor
Akira Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Application granted granted Critical
Publication of DE60227475D1 publication Critical patent/DE60227475D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE60227475T 2001-11-13 2002-11-13 Halbleiterbauelement Expired - Lifetime DE60227475D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001347121A JP3737045B2 (ja) 2001-11-13 2001-11-13 半導体装置

Publications (1)

Publication Number Publication Date
DE60227475D1 true DE60227475D1 (de) 2008-08-21

Family

ID=19160178

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60227475T Expired - Lifetime DE60227475D1 (de) 2001-11-13 2002-11-13 Halbleiterbauelement

Country Status (3)

Country Link
EP (1) EP1310998B1 (de)
JP (1) JP3737045B2 (de)
DE (1) DE60227475D1 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3833189B2 (ja) * 2003-05-27 2006-10-11 株式会社リコー 半導体装置及びその製造方法
JP2004363234A (ja) * 2003-06-03 2004-12-24 Renesas Technology Corp 半導体装置の製造方法
JP4493596B2 (ja) * 2003-07-31 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置
JP4546054B2 (ja) * 2003-08-29 2010-09-15 パナソニック株式会社 半導体装置の製造方法
JP4761431B2 (ja) * 2003-09-09 2011-08-31 セイコーインスツル株式会社 半導体装置の製造方法
JP4459655B2 (ja) * 2004-02-27 2010-04-28 セイコーインスツル株式会社 半導体集積回路装置
JP2006040947A (ja) 2004-07-22 2006-02-09 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4567396B2 (ja) * 2004-08-10 2010-10-20 セイコーインスツル株式会社 半導体集積回路装置
JP4575079B2 (ja) * 2004-08-10 2010-11-04 セイコーインスツル株式会社 半導体集積回路装置
KR100817958B1 (ko) 2004-09-30 2008-03-31 가부시키가이샤 리코 반도체장치 및 그 제조방법
JP4163169B2 (ja) * 2004-10-29 2008-10-08 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2006222410A (ja) * 2004-11-10 2006-08-24 Ricoh Co Ltd 半導体装置及びその製造方法
JP4646891B2 (ja) * 2004-11-10 2011-03-09 株式会社リコー 半導体装置及びその製造方法
US20060099765A1 (en) * 2004-11-11 2006-05-11 International Business Machines Corporation Method to enhance cmos transistor performance by inducing strain in the gate and channel
JP4333714B2 (ja) * 2006-08-31 2009-09-16 セイコーエプソン株式会社 半導体装置の設計方法および半導体装置の設計プログラム
JP5008363B2 (ja) * 2006-09-15 2012-08-22 株式会社リコー 半導体装置
JP2008182063A (ja) * 2007-01-25 2008-08-07 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5089194B2 (ja) * 2007-02-26 2012-12-05 セイコーインスツル株式会社 半導体装置及びその製造方法
JP2009032962A (ja) * 2007-07-27 2009-02-12 Panasonic Corp 半導体装置及びその製造方法
JP5568334B2 (ja) * 2010-02-24 2014-08-06 ラピスセミコンダクタ株式会社 半導体装置、及びその製造方法
JP6110686B2 (ja) * 2013-02-26 2017-04-05 旭化成エレクトロニクス株式会社 半導体装置の製造方法
JP6267987B2 (ja) * 2014-02-13 2018-01-24 エスアイアイ・セミコンダクタ株式会社 半導体装置
JP2019021659A (ja) * 2017-07-11 2019-02-07 キヤノン株式会社 半導体装置および機器
WO2019176040A1 (ja) * 2018-03-15 2019-09-19 シャープ株式会社 アクティブマトリクス基板および表示デバイス
JP6818710B2 (ja) * 2018-03-19 2021-01-20 株式会社東芝 定電圧回路
JP7267683B2 (ja) * 2018-04-25 2023-05-02 シャープ株式会社 発光素子モジュール
JP7489872B2 (ja) 2019-10-31 2024-05-24 エイブリック株式会社 半導体装置
US11587869B2 (en) 2019-10-31 2023-02-21 Ablic Inc. Semiconductor device and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
JPS5994849A (ja) * 1982-11-24 1984-05-31 Nec Corp 半導体集積回路装置
US5382916A (en) * 1991-10-30 1995-01-17 Harris Corporation Differential voltage follower
US5825068A (en) * 1997-03-17 1998-10-20 Integrated Device Technology, Inc. Integrated circuits that include a barrier layer reducing hydrogen diffusion into a polysilicon resistor
JP3262162B2 (ja) * 1998-12-14 2002-03-04 日本電気株式会社 半導体装置
US6100154A (en) * 1999-01-19 2000-08-08 Taiwan Semiconductor Manufacturing Company Using LPCVD silicon nitride cap as a barrier to reduce resistance variations from hydrogen intrusion of high-value polysilicon resistor
US6069063A (en) * 1999-04-01 2000-05-30 Taiwan Semiconductor Manufacturing Company Method to form polysilicon resistors shielded from hydrogen intrusion
US6232194B1 (en) * 1999-11-05 2001-05-15 Taiwan Semiconductor Manufacturing Company Silicon nitride capped poly resistor with SAC process

Also Published As

Publication number Publication date
EP1310998A2 (de) 2003-05-14
EP1310998B1 (de) 2008-07-09
JP2003152100A (ja) 2003-05-23
EP1310998A3 (de) 2003-08-27
JP3737045B2 (ja) 2006-01-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition