JP4567396B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
- Publication number
- JP4567396B2 JP4567396B2 JP2004233807A JP2004233807A JP4567396B2 JP 4567396 B2 JP4567396 B2 JP 4567396B2 JP 2004233807 A JP2004233807 A JP 2004233807A JP 2004233807 A JP2004233807 A JP 2004233807A JP 4567396 B2 JP4567396 B2 JP 4567396B2
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- Prior art keywords
- mos transistor
- gate electrode
- vth
- nitride film
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 23
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
(1) MOSトランジスターの製造方法において、ゲート電極を形成する工程と、前記ゲート電極と後にソースおよびドレインとなる領域上に絶縁膜を形成する工程と、ソースおよびドレインを形成する工程と、前記絶縁膜上に選択的に窒化膜を形成する工程とからなることを特徴とする半導体集積回路装置の製造方法とした。
(2) 前記窒化膜は減圧CVD法により形成され、50nm以上の膜厚を有することを特徴とする半導体集積回路装置の製造方法とした。
その詳細なメカニズムは後述する。
102 第2のMOSトランジスター
103 アクティブ領域
104 ゲート電極
105 コンタクト
106 ドレイン配線金属
107 ソース配線金属
108 窒化膜
109 絶縁膜
110 ソース拡散
111 ドレイン拡散
112 半導体基板
113 フォトレジスト
201 半導体基板
202 フォトレジスト
203 イオン注入
204 フォトレジスト
205 イオン注入
Claims (1)
- MOSトランジスターのソース拡散領域とゲート電極とのオーバラップ領域に水素が拡散することを阻止するために、前記ソース拡散領域の上部から前記ゲート電極の上部にまでのみ絶縁膜を介して配置された、その幅の前記MOSトランジスターのチャネル幅に対して占める割合が0よりは大きく1よりは小さい窒化膜を有する第1のMOSトランジスターと、
ソース拡散領域の上部からゲート電極の上部にまでのみ絶縁膜を介して配置された窒化膜を有していない、しきい値電圧の絶対値が前記第1のMOSトランジスターのしきい値電圧の絶対値よりも小さい第2のMOSトランジスターと、
を有する、マルチVthであることを特徴とする半導体集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004233807A JP4567396B2 (ja) | 2004-08-10 | 2004-08-10 | 半導体集積回路装置 |
US11/196,095 US7749880B2 (en) | 2004-08-10 | 2005-08-03 | Method of manufacturing semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004233807A JP4567396B2 (ja) | 2004-08-10 | 2004-08-10 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006054265A JP2006054265A (ja) | 2006-02-23 |
JP4567396B2 true JP4567396B2 (ja) | 2010-10-20 |
Family
ID=36031555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004233807A Expired - Fee Related JP4567396B2 (ja) | 2004-08-10 | 2004-08-10 | 半導体集積回路装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7749880B2 (ja) |
JP (1) | JP4567396B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6341063A (ja) * | 1986-08-07 | 1988-02-22 | Matsushita Electronics Corp | Mos集積回路の製造方法 |
JPH07147412A (ja) * | 1993-11-24 | 1995-06-06 | Sony Corp | 表示素子基板用半導体装置 |
JP2000058851A (ja) * | 1998-08-17 | 2000-02-25 | Sanyo Electric Co Ltd | 薄膜トランジスタ及びその製造方法、表示装置 |
JP2000183182A (ja) * | 1998-12-14 | 2000-06-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2003152100A (ja) * | 2001-11-13 | 2003-05-23 | Ricoh Co Ltd | 半導体装置 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4368085A (en) * | 1979-10-15 | 1983-01-11 | Rockwell International Corporation | SOS island edge passivation structure |
US4814854A (en) * | 1985-05-01 | 1989-03-21 | Texas Instruments Incorporated | Integrated circuit device and process with tin-gate transistor |
JPH01106470A (ja) * | 1987-10-19 | 1989-04-24 | Matsushita Electric Ind Co Ltd | 薄膜トランジタ |
JPH088311B2 (ja) * | 1988-07-05 | 1996-01-29 | 株式会社東芝 | 紫外線消去型不揮発性半導体記憶装置 |
JPH03198348A (ja) * | 1989-12-27 | 1991-08-29 | Kawasaki Steel Corp | Mos型半導体装置の製造方法 |
JPH05183156A (ja) * | 1992-01-07 | 1993-07-23 | Kawasaki Steel Corp | 半導体装置及びその製造方法 |
US5783475A (en) * | 1995-11-13 | 1998-07-21 | Motorola, Inc. | Method of forming a spacer |
US5716875A (en) * | 1996-03-01 | 1998-02-10 | Motorola, Inc. | Method for making a ferroelectric device |
US5981332A (en) * | 1997-09-30 | 1999-11-09 | Siemens Aktiengesellschaft | Reduced parasitic leakage in semiconductor devices |
US5936279A (en) * | 1997-10-20 | 1999-08-10 | United Microelectronics Corp. | Method of fabricating self-align contact window with silicon nitride side wall |
US6214673B1 (en) * | 1999-07-09 | 2001-04-10 | Intersil Corporation | Process for forming vertical semiconductor device having increased source contact area |
US6239014B1 (en) * | 1999-08-16 | 2001-05-29 | Vanguard International Semiconductor Corporation | Tungsten bit line structure featuring a sandwich capping layer |
US6399512B1 (en) * | 2000-06-15 | 2002-06-04 | Cypress Semiconductor Corporation | Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer |
US20020000605A1 (en) * | 2000-06-28 | 2002-01-03 | Chun-Mai Liu | Method of fabricating high-coupling ratio split gate flash memory cell array |
KR100376876B1 (ko) * | 2000-06-30 | 2003-03-19 | 주식회사 하이닉스반도체 | 다마신 금속 게이트에서의 자기 정렬 콘택 형성 방법 |
JP3906020B2 (ja) * | 2000-09-27 | 2007-04-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2002198368A (ja) * | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
JP3922341B2 (ja) * | 2001-01-11 | 2007-05-30 | セイコーエプソン株式会社 | 不揮発性メモリトランジスタを有する半導体装置の製造方法 |
US6531350B2 (en) * | 2001-02-22 | 2003-03-11 | Halo, Inc. | Twin MONOS cell fabrication method and array organization |
US6838344B2 (en) * | 2002-03-12 | 2005-01-04 | Halo Lsi, Inc. | Simplified twin monos fabrication method with three extra masks to standard CMOS |
US6682994B2 (en) * | 2002-04-16 | 2004-01-27 | Texas Instruments Incorporated | Methods for transistor gate formation using gate sidewall implantation |
KR100958618B1 (ko) * | 2002-12-31 | 2010-05-20 | 동부일렉트로닉스 주식회사 | 반도체 장치의 제조 방법 |
JP4459655B2 (ja) * | 2004-02-27 | 2010-04-28 | セイコーインスツル株式会社 | 半導体集積回路装置 |
JP2006032542A (ja) * | 2004-07-14 | 2006-02-02 | Seiko Instruments Inc | 半導体装置の製造方法 |
JP4575079B2 (ja) * | 2004-08-10 | 2010-11-04 | セイコーインスツル株式会社 | 半導体集積回路装置 |
US20060267106A1 (en) * | 2005-05-26 | 2006-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Novel semiconductor device with improved channel strain effect |
US8148269B2 (en) * | 2008-04-04 | 2012-04-03 | Applied Materials, Inc. | Boron nitride and boron-nitride derived materials deposition method |
-
2004
- 2004-08-10 JP JP2004233807A patent/JP4567396B2/ja not_active Expired - Fee Related
-
2005
- 2005-08-03 US US11/196,095 patent/US7749880B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6341063A (ja) * | 1986-08-07 | 1988-02-22 | Matsushita Electronics Corp | Mos集積回路の製造方法 |
JPH07147412A (ja) * | 1993-11-24 | 1995-06-06 | Sony Corp | 表示素子基板用半導体装置 |
JP2000058851A (ja) * | 1998-08-17 | 2000-02-25 | Sanyo Electric Co Ltd | 薄膜トランジスタ及びその製造方法、表示装置 |
JP2000183182A (ja) * | 1998-12-14 | 2000-06-30 | Nec Corp | 半導体装置及びその製造方法 |
JP2003152100A (ja) * | 2001-11-13 | 2003-05-23 | Ricoh Co Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2006054265A (ja) | 2006-02-23 |
US7749880B2 (en) | 2010-07-06 |
US20060079043A1 (en) | 2006-04-13 |
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