DE60225898D1 - Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung - Google Patents

Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung

Info

Publication number
DE60225898D1
DE60225898D1 DE60225898T DE60225898T DE60225898D1 DE 60225898 D1 DE60225898 D1 DE 60225898D1 DE 60225898 T DE60225898 T DE 60225898T DE 60225898 T DE60225898 T DE 60225898T DE 60225898 D1 DE60225898 D1 DE 60225898D1
Authority
DE
Germany
Prior art keywords
testing
scan
clock domains
scan cells
finding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60225898T
Other languages
English (en)
Other versions
DE60225898T2 (de
Inventor
Laung-Terng Wang
Po-Ching Hsu
Shih-Chia F Kao
Meng-Chyi Lin
Hsin-Po Wang
Hao-Jan Chao
Xiaoqing Wen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Syntest Technologies Inc
Original Assignee
Syntest Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26747802&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60225898(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Syntest Technologies Inc filed Critical Syntest Technologies Inc
Application granted granted Critical
Publication of DE60225898D1 publication Critical patent/DE60225898D1/de
Publication of DE60225898T2 publication Critical patent/DE60225898T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electric Clocks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE60225898T 2001-02-15 2002-02-13 Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung Expired - Lifetime DE60225898T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US26860101P 2001-02-15 2001-02-15
US268601P 2001-02-15
US10/067,372 US7007213B2 (en) 2001-02-15 2002-02-07 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US67372 2002-02-07
PCT/US2002/001251 WO2002067001A1 (en) 2001-02-15 2002-02-13 Multiple-capture dft system for detecting or locating crossing clock-domain faults during self-test or scan test

Publications (2)

Publication Number Publication Date
DE60225898D1 true DE60225898D1 (de) 2008-05-15
DE60225898T2 DE60225898T2 (de) 2009-05-20

Family

ID=26747802

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60225898T Expired - Lifetime DE60225898T2 (de) 2001-02-15 2002-02-13 Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung

Country Status (7)

Country Link
US (4) US7007213B2 (de)
EP (1) EP1360513B1 (de)
JP (2) JP4301813B2 (de)
CN (1) CN100414313C (de)
AT (1) ATE391300T1 (de)
DE (1) DE60225898T2 (de)
WO (1) WO2002067001A1 (de)

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US8769359B2 (en) 2001-02-15 2014-07-01 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US7007213B2 (en) * 2001-02-15 2006-02-28 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US6954887B2 (en) 2001-03-22 2005-10-11 Syntest Technologies, Inc. Multiple-capture DFT system for scan-based integrated circuits
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US7444567B2 (en) * 2002-04-09 2008-10-28 Syntest Technologies, Inc. Method and apparatus for unifying self-test with scan-test during prototype debug and production test
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Also Published As

Publication number Publication date
US20090132880A1 (en) 2009-05-21
US20070255988A1 (en) 2007-11-01
US7260756B1 (en) 2007-08-21
EP1360513A4 (de) 2005-01-19
CN100414313C (zh) 2008-08-27
JP4733191B2 (ja) 2011-07-27
US20020120896A1 (en) 2002-08-29
JP2009109512A (ja) 2009-05-21
DE60225898T2 (de) 2009-05-20
US7434126B2 (en) 2008-10-07
EP1360513A1 (de) 2003-11-12
JP2004530865A (ja) 2004-10-07
JP4301813B2 (ja) 2009-07-22
WO2002067001A1 (en) 2002-08-29
CN1623098A (zh) 2005-06-01
US7007213B2 (en) 2006-02-28
ATE391300T1 (de) 2008-04-15
US7779323B2 (en) 2010-08-17
EP1360513B1 (de) 2008-04-02

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