ATE391300T1 - Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung - Google Patents

Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung

Info

Publication number
ATE391300T1
ATE391300T1 AT02709061T AT02709061T ATE391300T1 AT E391300 T1 ATE391300 T1 AT E391300T1 AT 02709061 T AT02709061 T AT 02709061T AT 02709061 T AT02709061 T AT 02709061T AT E391300 T1 ATE391300 T1 AT E391300T1
Authority
AT
Austria
Prior art keywords
test
clock domains
scan
scan cells
detecting
Prior art date
Application number
AT02709061T
Other languages
English (en)
Inventor
Laung-Terng Wang
Po-Ching Hsu
Shih-Chia Kao
Meng-Chyi Lin
Hsin-Po Wang
Hao-Jan Chao
Xiaoqing Wen
Original Assignee
Syntest Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26747802&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE391300(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Syntest Technologies Inc filed Critical Syntest Technologies Inc
Application granted granted Critical
Publication of ATE391300T1 publication Critical patent/ATE391300T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Electric Clocks (AREA)
AT02709061T 2001-02-15 2002-02-13 Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung ATE391300T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26860101P 2001-02-15 2001-02-15
US10/067,372 US7007213B2 (en) 2001-02-15 2002-02-07 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Publications (1)

Publication Number Publication Date
ATE391300T1 true ATE391300T1 (de) 2008-04-15

Family

ID=26747802

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02709061T ATE391300T1 (de) 2001-02-15 2002-02-13 Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung

Country Status (7)

Country Link
US (4) US7007213B2 (de)
EP (1) EP1360513B1 (de)
JP (2) JP4301813B2 (de)
CN (1) CN100414313C (de)
AT (1) ATE391300T1 (de)
DE (1) DE60225898T2 (de)
WO (1) WO2002067001A1 (de)

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Also Published As

Publication number Publication date
JP2004530865A (ja) 2004-10-07
JP4733191B2 (ja) 2011-07-27
US7260756B1 (en) 2007-08-21
EP1360513B1 (de) 2008-04-02
US7434126B2 (en) 2008-10-07
EP1360513A4 (de) 2005-01-19
US20070255988A1 (en) 2007-11-01
JP4301813B2 (ja) 2009-07-22
CN1623098A (zh) 2005-06-01
CN100414313C (zh) 2008-08-27
DE60225898T2 (de) 2009-05-20
US20020120896A1 (en) 2002-08-29
JP2009109512A (ja) 2009-05-21
WO2002067001A1 (en) 2002-08-29
US7007213B2 (en) 2006-02-28
US20090132880A1 (en) 2009-05-21
US7779323B2 (en) 2010-08-17
DE60225898D1 (de) 2008-05-15
EP1360513A1 (de) 2003-11-12

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