DE69430637D1 - Vorrichtung und verfahren zum testen von integrierten schaltkreisen - Google Patents

Vorrichtung und verfahren zum testen von integrierten schaltkreisen

Info

Publication number
DE69430637D1
DE69430637D1 DE69430637T DE69430637T DE69430637D1 DE 69430637 D1 DE69430637 D1 DE 69430637D1 DE 69430637 T DE69430637 T DE 69430637T DE 69430637 T DE69430637 T DE 69430637T DE 69430637 D1 DE69430637 D1 DE 69430637D1
Authority
DE
Germany
Prior art keywords
integrated circuits
test patterns
test
testing
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430637T
Other languages
English (en)
Other versions
DE69430637T2 (de
Inventor
Wayne Needham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69430637D1 publication Critical patent/DE69430637D1/de
Publication of DE69430637T2 publication Critical patent/DE69430637T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/83—Indexing scheme relating to error detection, to error correction, and to monitoring the solution involving signatures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)
DE69430637T 1993-12-30 1994-12-02 Vorrichtung und verfahren zum testen von integrierten schaltkreisen Expired - Fee Related DE69430637T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/175,771 US5583786A (en) 1993-12-30 1993-12-30 Apparatus and method for testing integrated circuits
PCT/US1994/013804 WO1995019011A2 (en) 1993-12-30 1994-12-02 Apparatus and method for testing integrated circuits

Publications (2)

Publication Number Publication Date
DE69430637D1 true DE69430637D1 (de) 2002-06-20
DE69430637T2 DE69430637T2 (de) 2003-01-02

Family

ID=22641561

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430637T Expired - Fee Related DE69430637T2 (de) 1993-12-30 1994-12-02 Vorrichtung und verfahren zum testen von integrierten schaltkreisen

Country Status (8)

Country Link
US (1) US5583786A (de)
EP (1) EP0737337B1 (de)
JP (1) JP3749541B2 (de)
AU (1) AU1298695A (de)
DE (1) DE69430637T2 (de)
SG (1) SG47061A1 (de)
TW (1) TW352466B (de)
WO (1) WO1995019011A2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859962A (en) * 1995-12-21 1999-01-12 Ncr Corporation Automated verification of digital design
US5745500A (en) * 1996-10-22 1998-04-28 The United States Of America As Represented By The Secretary Of The Army Built-in self testing for the identification of faulty integrated circuit chips in a multichip module
US5790561A (en) * 1997-01-17 1998-08-04 Rockwell International Corporation Internal testability system for microprocessor-based integrated circuit
US5995915A (en) 1997-01-29 1999-11-30 Advanced Micro Devices, Inc. Method and apparatus for the functional verification of digital electronic systems
US6408410B1 (en) 1997-06-13 2002-06-18 Intel Corporation Method and apparatus for built in self-test of buffer circuits for speed related defects
US5978946A (en) * 1997-10-31 1999-11-02 Intel Coporation Methods and apparatus for system testing of processors and computers using signature analysis
US6389586B1 (en) 1998-01-05 2002-05-14 Synplicity, Inc. Method and apparatus for invalid state detection
US6158033A (en) * 1998-05-08 2000-12-05 S3 Incorporated Multiple input signature testing & diagnosis for embedded blocks in integrated circuits
US6249889B1 (en) * 1998-10-13 2001-06-19 Advantest Corp. Method and structure for testing embedded memories
US6557128B1 (en) * 1999-11-12 2003-04-29 Advantest Corp. Semiconductor test system supporting multiple virtual logic testers
US6424926B1 (en) * 2000-03-31 2002-07-23 Intel Corporation Bus signature analyzer and behavioral functional test method
US6754867B2 (en) 2000-12-28 2004-06-22 Intel Corporation Method of determining non-accessible device I/O pin speed using on chip LFSR and MISR as data source and results analyzer respectively
US6557132B2 (en) 2001-02-22 2003-04-29 International Business Machines Corporation Method and system for determining common failure modes for integrated circuits
US7096397B2 (en) * 2001-09-17 2006-08-22 Intel Corporation Dft technique for avoiding contention/conflict in logic built-in self-test
US7131046B2 (en) * 2002-12-03 2006-10-31 Verigy Ipco System and method for testing circuitry using an externally generated signature
US7137057B2 (en) * 2003-01-07 2006-11-14 Sun Microsystems, Inc. Method and apparatus for performing error correction code (ECC) conversion
US7228474B2 (en) * 2003-01-07 2007-06-05 Sun Microsystems, Inc. Semiconductor device and method and apparatus for testing such a device
US20040133831A1 (en) * 2003-01-07 2004-07-08 Emrys Williams Semiconductor device and method and apparatus for testing such a device
US7245357B2 (en) * 2003-12-15 2007-07-17 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US7353437B2 (en) * 2004-10-29 2008-04-01 Micron Technology, Inc. System and method for testing a memory for a memory failure exhibited by a failing memory
US7478307B1 (en) 2005-05-19 2009-01-13 Sun Microsystems, Inc. Method for improving un-correctable errors in a computer system
US7480847B2 (en) * 2005-08-29 2009-01-20 Sun Microsystems, Inc. Error correction code transformation technique
US7523342B1 (en) 2005-10-28 2009-04-21 Sun Microsystems, Inc. Data and control integrity for transactions in a computer system
US20070115833A1 (en) * 2005-11-21 2007-05-24 Gerald Pepper Varying the position of test information in data units
US9297856B2 (en) * 2013-10-23 2016-03-29 International Business Machines Corporation Implementing MISR compression methods for test time reduction
EP3081575A1 (de) 2015-04-12 2016-10-19 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Anti-plasmodium-parasiten-antikörper
JP7500994B2 (ja) * 2020-02-27 2024-06-18 セイコーエプソン株式会社 半導体装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643156A (en) * 1969-06-05 1972-02-15 Rca Corp Pulse-type circuit element-testing method
US3927371A (en) * 1974-02-19 1975-12-16 Ibm Test system for large scale integrated circuits
US4433413A (en) * 1981-10-22 1984-02-21 Siemens Corporation Built-in apparatus and method for testing a microprocessor system
US4519078A (en) * 1982-09-29 1985-05-21 Storage Technology Corporation LSI self-test method
US4635218A (en) * 1983-05-09 1987-01-06 Valid Logic Systems Method for simulating system operation of static and dynamic circuit devices
US4594711A (en) * 1983-11-10 1986-06-10 Texas Instruments Incorporated Universal testing circuit and method
US4597080A (en) * 1983-11-14 1986-06-24 Texas Instruments Incorporated Architecture and method for testing VLSI processors
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
DE3580909D1 (de) * 1985-01-04 1991-01-24 Ibm Deutschland Pruef- und diagnoseeinrichtung fuer digitalrechner.
US4801870A (en) * 1985-06-24 1989-01-31 International Business Machines Corporation Weighted random pattern testing apparatus and method
US4687988A (en) * 1985-06-24 1987-08-18 International Business Machines Corporation Weighted random pattern testing apparatus and method
US4688223A (en) * 1985-06-24 1987-08-18 International Business Machines Corporation Weighted random pattern testing apparatus and method
US4745355A (en) * 1985-06-24 1988-05-17 International Business Machines Corporation Weighted random pattern testing apparatus and method
JP2628154B2 (ja) * 1986-12-17 1997-07-09 富士通株式会社 半導体集積回路
US4817093A (en) * 1987-06-18 1989-03-28 International Business Machines Corporation Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure
JP2673298B2 (ja) * 1987-12-17 1997-11-05 三菱電機株式会社 セルフテスト機能付半導体集積回路
US5084874A (en) * 1988-09-07 1992-01-28 Texas Instruments Incorporated Enhanced test circuit
US5027355A (en) * 1989-04-14 1991-06-25 Control Data Corporation Logic circuit and design method for improved testability
US5101409A (en) * 1989-10-06 1992-03-31 International Business Machines Corporation Checkboard memory self-test
US5138619A (en) * 1990-02-15 1992-08-11 National Semiconductor Corporation Built-in self test for integrated circuit memory
US5187712A (en) * 1990-02-26 1993-02-16 At&T Bell Laboratories Pseudo-exhaustive self-test technique
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US5253255A (en) * 1990-11-02 1993-10-12 Intel Corporation Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip
US5321277A (en) * 1990-12-31 1994-06-14 Texas Instruments Incorporated Multi-chip module testing
US5260946A (en) * 1991-06-03 1993-11-09 Hughes Missile Systems Company Self-testing and self-configuration in an integrated circuit
US5331643A (en) * 1991-09-04 1994-07-19 International Business Machines Corporation Self-testing logic with embedded arrays
US5369648A (en) * 1991-11-08 1994-11-29 Ncr Corporation Built-in self-test circuit
DE69224727T2 (de) * 1991-12-16 1998-11-12 Nippon Telegraph & Telephone Schaltung mit eingebautem Selbsttest
US5329533A (en) * 1991-12-26 1994-07-12 At&T Bell Laboratories Partial-scan built-in self-test technique
US5416783A (en) * 1993-08-09 1995-05-16 Motorola, Inc. Method and apparatus for generating pseudorandom numbers or for performing data compression in a data processor

Also Published As

Publication number Publication date
US5583786A (en) 1996-12-10
AU1298695A (en) 1995-08-01
SG47061A1 (en) 1998-03-20
TW352466B (en) 1999-02-11
DE69430637T2 (de) 2003-01-02
WO1995019011A2 (en) 1995-07-13
WO1995019011A3 (en) 1995-07-27
EP0737337B1 (de) 2002-05-15
EP0737337A4 (de) 1997-04-02
JPH09508992A (ja) 1997-09-09
EP0737337A1 (de) 1996-10-16
JP3749541B2 (ja) 2006-03-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee