DE69633713D1 - Verfahren und Vorrichtung zur Prüfung von integrierten Schaltungen - Google Patents

Verfahren und Vorrichtung zur Prüfung von integrierten Schaltungen

Info

Publication number
DE69633713D1
DE69633713D1 DE69633713T DE69633713T DE69633713D1 DE 69633713 D1 DE69633713 D1 DE 69633713D1 DE 69633713 T DE69633713 T DE 69633713T DE 69633713 T DE69633713 T DE 69633713T DE 69633713 D1 DE69633713 D1 DE 69633713D1
Authority
DE
Germany
Prior art keywords
testing integrated
integrated circuits
pad
die
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69633713T
Other languages
English (en)
Other versions
DE69633713T2 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69633713D1 publication Critical patent/DE69633713D1/de
Application granted granted Critical
Publication of DE69633713T2 publication Critical patent/DE69633713T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69633713T 1995-10-31 1996-10-31 Verfahren und Vorrichtung zur Prüfung von integrierten Schaltungen Expired - Lifetime DE69633713T2 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US818695P 1995-10-31 1995-10-31
US813895P 1995-10-31 1995-10-31
US818495P 1995-10-31 1995-10-31
US710295P 1995-10-31 1995-10-31
US8138 1995-10-31
US8184 1995-10-31
US7102 1995-10-31
US8186 1998-01-16

Publications (2)

Publication Number Publication Date
DE69633713D1 true DE69633713D1 (de) 2004-12-02
DE69633713T2 DE69633713T2 (de) 2006-02-02

Family

ID=27485659

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69633713T Expired - Lifetime DE69633713T2 (de) 1995-10-31 1996-10-31 Verfahren und Vorrichtung zur Prüfung von integrierten Schaltungen

Country Status (5)

Country Link
EP (1) EP0786667B1 (de)
JP (1) JP4041550B2 (de)
KR (1) KR100402868B1 (de)
DE (1) DE69633713T2 (de)
TW (1) TW454291B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4572564B2 (ja) * 2004-04-05 2010-11-04 パナソニック株式会社 半導体装置
KR101328152B1 (ko) 2004-07-14 2013-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 무선 프로세서, 무선 메모리, 정보 처리 시스템, 및반도체장치
DE102004059505B4 (de) * 2004-12-10 2014-06-18 X-Fab Semiconductor Foundries Ag Anordnung zum Test von eingebetteten Schaltungen mit Hilfe von Testinseln
US7640379B2 (en) * 2005-02-12 2009-12-29 Broadcom Corporation System method for I/O pads in mobile multimedia processor (MMP) that has bypass mode wherein data is passed through without being processed by MMP
DE102007062711A1 (de) 2007-12-27 2009-07-02 Robert Bosch Gmbh Halbleiterwafer mit einer Vielzahl von Sensorelementen und Verfahren zum Vermessen von Sensorelementen auf einem Halbleiterwafer
TWI607670B (zh) 2009-01-08 2017-12-01 半導體能源研究所股份有限公司 發光裝置及電子裝置
US8786080B2 (en) * 2011-03-11 2014-07-22 Altera Corporation Systems including an I/O stack and methods for fabricating such systems
JP2013050860A (ja) * 2011-08-31 2013-03-14 Renesas Electronics Corp マイクロコンピュータ及びマルチマイクロコンピュータシステム
DE102013102155B4 (de) 2013-03-05 2015-04-09 Friedrich-Alexander-Universität Erlangen-Nürnberg Verfahren zum testen von bauelementen und messanordnung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092733A (en) * 1976-05-07 1978-05-30 Mcdonnell Douglas Corporation Electrically alterable interconnection
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit
JPS62220879A (ja) * 1986-03-22 1987-09-29 Hitachi Ltd 半導体装置

Also Published As

Publication number Publication date
JPH09266283A (ja) 1997-10-07
KR970023959A (ko) 1997-05-30
DE69633713T2 (de) 2006-02-02
JP4041550B2 (ja) 2008-01-30
TW454291B (en) 2001-09-11
EP0786667A3 (de) 1999-07-07
KR100402868B1 (ko) 2004-02-05
EP0786667B1 (de) 2004-10-27
EP0786667A2 (de) 1997-07-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition